Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	732005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

917720

1

T1

1537

T2

617

T3

995

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1362703	1			T1	1946		T2	480		T3	881
values[0x0]	142943	1			T1	378		T2	212		T3	335
values[0x1]	144079	1			T1	350		T2	244		T3	297

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	578765	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1070960

1

T1

1766

T2

692

T3

1102

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5350	1			T1	7		T3	2		T10	1
valid_sources[0x01]	5049	1			T1	4		T3	9		T10	3
valid_sources[0x02]	6387	1			T1	20		T3	2		T10	7
valid_sources[0x03]	5546	1			T1	10		T3	11		T11	1
valid_sources[0x04]	4901	1			T1	4		T3	1		T10	4
valid_sources[0x05]	9712	1			T1	9		T3	5		T10	2
valid_sources[0x06]	6577	1			T1	5		T3	5		T10	10
valid_sources[0x07]	4762	1			T1	6		T3	6		T13	4
valid_sources[0x08]	5035	1			T1	11		T13	1		T14	4
valid_sources[0x09]	5161	1			T1	22		T3	6		T10	4
valid_sources[0x0a]	5338	1			T1	22		T3	8		T13	1
valid_sources[0x0b]	5178	1			T1	16		T3	6		T11	1
valid_sources[0x0c]	5858	1			T1	6		T3	4		T13	8
valid_sources[0x0d]	5198	1			T1	23		T3	2		T11	1
valid_sources[0x0e]	4905	1			T1	6		T3	7		T11	1
valid_sources[0x0f]	4754	1			T1	18		T3	5		T10	1
valid_sources[0x10]	5032	1			T1	3		T3	6		T13	7
valid_sources[0x11]	5222	1			T1	16		T3	6		T10	4
valid_sources[0x12]	6311	1			T1	5		T3	16		T10	3
valid_sources[0x13]	5669	1			T1	18		T3	6		T10	5
valid_sources[0x14]	4886	1			T1	9		T3	5		T13	2
valid_sources[0x15]	5583	1			T1	14		T3	8		T13	3
valid_sources[0x16]	6481	1			T1	7		T3	4		T13	3
valid_sources[0x17]	5711	1			T1	12		T3	1		T13	4
valid_sources[0x18]	6765	1			T1	3		T3	14		T10	13
valid_sources[0x19]	5072	1			T1	8		T3	4		T14	3
valid_sources[0x1a]	5177	1			T1	12		T3	3		T10	10
valid_sources[0x1b]	4803	1			T1	9		T10	5		T13	3
valid_sources[0x1c]	6600	1			T1	15		T3	7		T11	1
valid_sources[0x1d]	5262	1			T1	5		T3	7		T13	4
valid_sources[0x1e]	4622	1			T1	10		T3	8		T13	4
valid_sources[0x1f]	5619	1			T1	3		T3	13		T13	4
valid_sources[0x20]	7040	1			T1	11		T3	9		T11	1
valid_sources[0x21]	5306	1			T1	8		T3	4		T10	2
valid_sources[0x22]	11463	1			T1	13		T3	4		T13	1
valid_sources[0x23]	7173	1			T1	14		T3	9		T13	1
valid_sources[0x24]	5086	1			T1	12		T10	1		T13	3
valid_sources[0x25]	5680	1			T1	7		T3	7		T13	2
valid_sources[0x26]	4902	1			T1	11		T3	2		T13	3
valid_sources[0x27]	8798	1			T1	10		T13	3		T14	13
valid_sources[0x28]	5929	1			T1	20		T3	7		T10	1
valid_sources[0x29]	5406	1			T1	8		T3	10		T13	1
valid_sources[0x2a]	7392	1			T1	15		T3	1		T11	1
valid_sources[0x2b]	6262	1			T1	13		T3	6		T10	15
valid_sources[0x2c]	5048	1			T1	12		T3	3		T10	1
valid_sources[0x2d]	4868	1			T1	11		T3	13		T10	2
valid_sources[0x2e]	5430	1			T1	13		T3	6		T10	7
valid_sources[0x2f]	5129	1			T1	13		T3	5		T10	5
valid_sources[0x30]	6611	1			T1	7		T3	13		T10	17
valid_sources[0x31]	6032	1			T1	9		T3	3		T10	4
valid_sources[0x32]	5190	1			T1	10		T3	2		T13	4
valid_sources[0x33]	5222	1			T1	6		T3	5		T10	4
valid_sources[0x34]	11894	1			T1	8		T3	11		T14	2
valid_sources[0x35]	5979	1			T1	6		T2	936		T3	3
valid_sources[0x36]	6527	1			T1	9		T3	11		T13	3
valid_sources[0x37]	8463	1			T1	17		T3	2		T13	3
valid_sources[0x38]	5014	1			T1	18		T3	9		T10	3
valid_sources[0x39]	5579	1			T1	12		T3	2		T10	14
valid_sources[0x3a]	5553	1			T1	9		T3	4		T10	4
valid_sources[0x3b]	4653	1			T1	18		T3	8		T13	4
valid_sources[0x3c]	5402	1			T1	3		T3	6		T11	1
valid_sources[0x3d]	5635	1			T1	15		T3	7		T13	3
valid_sources[0x3e]	6324	1			T1	16		T3	2		T11	1
valid_sources[0x3f]	4938	1			T1	16		T3	6		T10	5
valid_sources[0x40]	5230	1			T1	9		T3	18		T13	10
valid_sources[0x41]	5198	1			T1	16		T3	11		T11	1
valid_sources[0x42]	5306	1			T1	4		T3	7		T10	10
valid_sources[0x43]	5079	1			T1	10		T3	7		T10	9
valid_sources[0x44]	6640	1			T1	11		T3	6		T10	12
valid_sources[0x45]	5485	1			T1	12		T3	15		T10	2
valid_sources[0x46]	6158	1			T1	9		T3	12		T10	5
valid_sources[0x47]	4947	1			T1	12		T3	4		T10	4
valid_sources[0x48]	5328	1			T1	16		T3	8		T10	5
valid_sources[0x49]	6521	1			T1	5		T3	4		T11	2
valid_sources[0x4a]	6911	1			T1	7		T3	6		T10	5
valid_sources[0x4b]	4855	1			T1	3		T3	10		T11	2
valid_sources[0x4c]	5329	1			T1	14		T3	1		T13	5
valid_sources[0x4d]	12369	1			T1	12		T3	2		T10	2
valid_sources[0x4e]	5338	1			T1	10		T3	20		T10	4
valid_sources[0x4f]	8141	1			T1	7		T3	5		T13	4
valid_sources[0x50]	4897	1			T1	10		T3	17		T10	3
valid_sources[0x51]	5717	1			T1	7		T3	3		T10	2
valid_sources[0x52]	7499	1			T1	8		T13	2		T14	6
valid_sources[0x53]	5077	1			T1	9		T3	10		T13	2
valid_sources[0x54]	4716	1			T1	18		T3	4		T11	2
valid_sources[0x55]	5187	1			T1	12		T3	8		T10	1
valid_sources[0x56]	5276	1			T1	11		T3	4		T10	6
valid_sources[0x57]	4966	1			T1	6		T3	2		T10	1
valid_sources[0x58]	5350	1			T1	8		T3	1		T13	3
valid_sources[0x59]	4969	1			T1	16		T3	4		T13	3
valid_sources[0x5a]	6507	1			T1	5		T13	5		T14	6
valid_sources[0x5b]	5661	1			T1	3		T3	2		T10	2
valid_sources[0x5c]	5251	1			T1	10		T3	4		T10	23
valid_sources[0x5d]	5490	1			T1	9		T11	1		T13	4
valid_sources[0x5e]	5629	1			T1	19		T3	8		T10	14
valid_sources[0x5f]	5634	1			T1	9		T10	4		T11	1
valid_sources[0x60]	5780	1			T1	8		T13	6		T14	9
valid_sources[0x61]	5103	1			T1	18		T3	5		T10	3
valid_sources[0x62]	5288	1			T1	7		T13	7		T14	9
valid_sources[0x63]	6416	1			T1	8		T3	6		T13	6
valid_sources[0x64]	5416	1			T1	9		T3	11		T10	11
valid_sources[0x65]	5468	1			T1	13		T3	4		T13	2
valid_sources[0x66]	6942	1			T1	6		T3	3		T10	1
valid_sources[0x67]	8317	1			T1	3		T3	1		T13	5
valid_sources[0x68]	5701	1			T1	13		T3	6		T13	4
valid_sources[0x69]	5357	1			T1	27		T3	7		T10	7
valid_sources[0x6a]	4957	1			T1	12		T3	15		T10	19
valid_sources[0x6b]	5375	1			T1	4		T3	6		T10	9
valid_sources[0x6c]	5347	1			T1	14		T3	11		T10	4
valid_sources[0x6d]	5389	1			T1	6		T3	7		T10	1
valid_sources[0x6e]	4863	1			T1	8		T3	4		T10	1
valid_sources[0x6f]	6035	1			T1	8		T3	15		T10	2
valid_sources[0x70]	7180	1			T1	6		T3	8		T10	4
valid_sources[0x71]	5773	1			T1	14		T3	11		T13	6
valid_sources[0x72]	5590	1			T1	17		T3	10		T10	1
valid_sources[0x73]	4859	1			T1	5		T3	9		T10	2
valid_sources[0x74]	6893	1			T1	17		T3	18		T14	6
valid_sources[0x75]	5018	1			T1	7		T3	4		T11	1
valid_sources[0x76]	18381	1			T1	19		T3	2		T11	1
valid_sources[0x77]	7072	1			T1	23		T3	3		T10	4
valid_sources[0x78]	7547	1			T1	18		T3	10		T13	2
valid_sources[0x79]	5515	1			T1	18		T3	2		T14	6
valid_sources[0x7a]	5592	1			T1	17		T3	3		T13	3
valid_sources[0x7b]	6119	1			T1	9		T3	5		T11	2
valid_sources[0x7c]	7652	1			T1	11		T3	10		T10	4
valid_sources[0x7d]	5431	1			T1	16		T3	9		T10	1
valid_sources[0x7e]	7382	1			T1	4		T3	5		T10	7
valid_sources[0x7f]	6051	1			T1	7		T3	3		T10	1
valid_sources[0x80]	6620	1			T1	16		T3	8		T10	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

670939

1

T1

904

T2

220

T3

438

values[0x0]

all_enables

biggest_size

123755

1

T1

328

T2

185

T3

296

values[0x1]

all_enables

biggest_size

123026

1

T1

305

T2

212

T3

261