SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 91.67 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
false | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 330 | 1 | T66 | 4 | T67 | 4 | T68 | 12 | ||||
others[1] | 348 | 1 | T66 | 14 | T67 | 4 | T68 | 6 | ||||
others[2] | 326 | 1 | T66 | 12 | T67 | 9 | T68 | 4 | ||||
others[3] | 481 | 1 | T66 | 16 | T67 | 4 | T68 | 13 | ||||
true | 43130 | 1 | T1 | 92 | T2 | 58 | T3 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
true | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 371 | 1 | T66 | 11 | T67 | 4 | T68 | 14 | ||||
others[1] | 311 | 1 | T66 | 8 | T67 | 2 | T68 | 10 | ||||
others[2] | 280 | 1 | T66 | 6 | T67 | 8 | T68 | 6 | ||||
others[3] | 549 | 1 | T66 | 10 | T67 | 6 | T68 | 14 | ||||
false | 43126 | 1 | T1 | 92 | T2 | 58 | T3 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
false | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 290 | 1 | T66 | 12 | T67 | 2 | T68 | 4 | ||||
others[1] | 332 | 1 | T66 | 4 | T67 | 2 | T68 | 4 | ||||
others[2] | 294 | 1 | T66 | 10 | T67 | 2 | T68 | 9 | ||||
others[3] | 521 | 1 | T66 | 8 | T67 | 8 | T68 | 4 | ||||
true | 43131 | 1 | T1 | 92 | T2 | 58 | T3 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 154 | 1 | T66 | 4 | T67 | 3 | T68 | 4 | ||||
others[1] | 162 | 1 | T66 | 3 | T67 | 4 | T68 | 5 | ||||
others[2] | 161 | 1 | T66 | 1 | T67 | 3 | T68 | 6 | ||||
others[3] | 260 | 1 | T66 | 7 | T67 | 3 | T68 | 3 | ||||
false | 732371 | 1 | T1 | 92 | T2 | 58 | T3 | 1642 | ||||
true | 688396 | 1 | T3 | 1562 | T16 | 2 | T5 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 179 | 1 | T66 | 2 | T67 | 6 | T68 | 1 | ||||
others[1] | 177 | 1 | T66 | 5 | T67 | 3 | T68 | 7 | ||||
others[2] | 182 | 1 | T66 | 3 | T67 | 5 | T68 | 3 | ||||
others[3] | 316 | 1 | T66 | 6 | T67 | 2 | T68 | 8 | ||||
false | 1746598 | 1 | T1 | 93 | T2 | 59 | T3 | 1842 | ||||
true | 1702652 | 1 | T1 | 1 | T2 | 1 | T3 | 1762 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 179 | 1 | T66 | 2 | T67 | 6 | T68 | 1 | ||||
others[1] | 177 | 1 | T66 | 5 | T67 | 3 | T68 | 7 | ||||
others[2] | 182 | 1 | T66 | 3 | T67 | 5 | T68 | 3 | ||||
others[3] | 316 | 1 | T66 | 6 | T67 | 2 | T68 | 8 | ||||
false | 1746597 | 1 | T1 | 93 | T2 | 59 | T3 | 1842 | ||||
true | 1702653 | 1 | T1 | 1 | T2 | 1 | T3 | 1762 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |