Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	61527839	14268	0	0
claim_transition_if_regwen_rd_A	61527839	916	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61527839	14268	0	0
T25	22667	0	0	0
T56	37079	0	0	0
T70	3268	0	0	0
T91	176125	2	0	0
T92	228881	9	0	0
T93	0	13	0	0
T98	17477	0	0	0
T99	114914	0	0	0
T136	0	6	0	0
T137	0	3	0	0
T138	0	10	0	0
T139	0	6	0	0
T140	0	10	0	0
T141	0	12	0	0
T142	0	1	0	0
T143	9519	0	0	0
T144	413580	0	0	0
T145	38857	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61527839	916	0	0
T26	22384	0	0	0
T52	48227	0	0	0
T57	29230	0	0	0
T136	314938	14	0	0
T146	0	1	0	0
T147	0	13	0	0
T148	0	16	0	0
T149	0	8	0	0
T150	0	2	0	0
T151	0	12	0	0
T152	0	13	0	0
T153	0	8	0	0
T154	0	3	0	0
T155	103076	0	0	0
T156	21200	0	0	0
T157	24476	0	0	0
T158	6878	0	0	0
T159	1125	0	0	0
T160	11968	0	0	0