Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60001580

1

T1

7029

T2

194983

T3

60858

auto[1]

1166767

1

T4

2277

T5

198

T10

6988

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59979523

1

T1

7029

T2

194983

T3

60858

auto[1]

1188824

1

T4

2475

T5

99

T11

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5772441	1			T1	73		T2	110		T3	10265
auto[IdleSt]	15625752	1			T1	6956		T2	194873		T3	9388
auto[ClkMuxSt]	28960	1			T3	90		T5	9		T11	8
auto[CntIncrSt]	28769	1			T3	90		T5	9		T11	8
auto[CntProgSt]	1446634	1			T3	180		T5	446		T11	16
auto[TransCheckSt]	22469	1			T3	90		T5	9		T11	8
auto[TokenHashSt]	16295475	1			T3	24090		T5	171		T11	1836
auto[FlashRmaSt]	27803	1			T5	9		T11	8		T13	80
auto[TokenCheck0St]	10186	1			T5	9		T11	8		T13	29
auto[TokenCheck1St]	7404	1			T5	9		T11	8		T13	13
auto[TransProgSt]	336038	1			T5	304		T11	16		T10	112
auto[PostTransSt]	8019730	1			T3	16665		T5	1571		T11	1962
auto[ScrapSt]	217030	1			T10	319		T36	281		T37	2971
auto[EscalateSt]	4976820	1			T4	6940		T5	498		T11	490
auto[InvalidSt]	8351479	1			T4	8783		T5	256		T11	278

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1357	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	8351479	1			T4	8783		T5	256		T11	278
EscalateSt	4976820	1			T4	6940		T5	498		T11	490
ScrapSt	217030	1			T10	319		T36	281		T37	2971
PostTransSt	8019730	1			T3	16665		T5	1571		T11	1962
TransProgSt	336038	1			T5	304		T11	16		T10	112
TokenCheck1St	7404	1			T5	9		T11	8		T13	13
TokenCheck0St	10186	1			T5	9		T11	8		T13	29
FlashRmaSt	27803	1			T5	9		T11	8		T13	80
TokenHashSt	16295475	1			T3	24090		T5	171		T11	1836
TransCheckSt	22469	1			T3	90		T5	9		T11	8
CntProgSt	1446634	1			T3	180		T5	446		T11	16
CntIncrSt	28769	1			T3	90		T5	9		T11	8
ClkMuxSt	28960	1			T3	90		T5	9		T11	8
IdleSt	15625752	1			T1	6956		T2	194873		T3	9388
ResetSt	5772441	1			T1	73		T2	110		T3	10265
arcs[ResetSt=>IdleSt]	43143	1			T1	1		T2	1		T3	91
arcs[IdleSt=>ScrapSt]	231	1			T10	3		T36	1		T37	2
arcs[IdleSt=>ClkMuxSt]	28802	1			T3	90		T5	9		T11	8
arcs[ClkMuxSt=>CntIncrSt]	28769	1			T3	90		T5	9		T11	8
arcs[CntIncrSt=>PostTransSt]	1298	1			T15	10		T33	9		T34	20
arcs[CntIncrSt=>CntProgSt]	27415	1			T3	90		T5	9		T11	8
arcs[CntProgSt=>PostTransSt]	3749	1			T10	55		T15	9		T16	12
arcs[CntProgSt=>TransCheckSt]	22469	1			T3	90		T5	9		T11	8
arcs[TransCheckSt=>PostTransSt]	3188	1			T13	35		T15	15		T33	9
arcs[TransCheckSt=>TokenHashSt]	19190	1			T3	90		T5	9		T11	8
arcs[TokenHashSt=>PostTransSt]	8274	1			T3	90		T12	50		T13	6
arcs[TokenHashSt=>FlashRmaSt]	10242	1			T5	9		T11	8		T13	29
arcs[FlashRmaSt=>TokenCheck0St]	10186	1			T5	9		T11	8		T13	29
arcs[TokenCheck0St=>PostTransSt]	2721	1			T13	16		T15	11		T16	14
arcs[TokenCheck0St=>TokenCheck1St]	7404	1			T5	9		T11	8		T13	13
arcs[TokenCheck1St=>PostTransSt]	644	1			T13	13		T10	1		T16	2
arcs[TransProgSt=>PostTransSt]	5887	1			T5	9		T11	8		T10	56
arcs[IdleSt=>EscalateSt]	157	1			T49	5		T55	3		T57	8
arcs[ClkMuxSt=>EscalateSt]	33	1			T49	1		T50	2		T51	1
arcs[CntIncrSt=>EscalateSt]	56	1			T52	2		T53	2		T54	2
arcs[CntProgSt=>EscalateSt]	1197	1			T52	51		T49	27		T55	3
arcs[TransCheckSt=>EscalateSt]	91	1			T55	4		T56	8		T50	9
arcs[TokenHashSt=>EscalateSt]	673	1			T52	11		T49	6		T55	18
arcs[FlashRmaSt=>EscalateSt]	56	1			T52	1		T54	1		T56	1
arcs[TokenCheck0St=>EscalateSt]	61	1			T52	2		T55	2		T53	1
arcs[TokenCheck1St=>EscalateSt]	32	1			T49	1		T55	1		T53	2
arcs[TransProgSt=>EscalateSt]	841	1			T52	14		T49	18		T55	7
arcs[PostTransSt=>EscalateSt]	4028	1			T10	55		T15	10		T16	12
arcs[InvalidSt=>EscalateSt]	10478	1			T4	48		T5	3		T11	2

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5772265	1			T1	73		T2	110		T3	10265
auto[0]	auto[IdleSt]	15625643	1			T1	6956		T2	194873		T3	9388
auto[0]	auto[ClkMuxSt]	28940	1			T3	90		T5	9		T11	8
auto[0]	auto[CntIncrSt]	28737	1			T3	90		T5	9		T11	8
auto[0]	auto[CntProgSt]	1445822	1			T3	180		T5	446		T11	16
auto[0]	auto[TransCheckSt]	22411	1			T3	90		T5	9		T11	8
auto[0]	auto[TokenHashSt]	16295025	1			T3	24090		T5	171		T11	1836
auto[0]	auto[FlashRmaSt]	27769	1			T5	9		T11	8		T13	80
auto[0]	auto[TokenCheck0St]	10140	1			T5	9		T11	8		T13	29
auto[0]	auto[TokenCheck1St]	7381	1			T5	9		T11	8		T13	13
auto[0]	auto[TransProgSt]	335484	1			T5	304		T11	16		T10	112
auto[0]	auto[PostTransSt]	8017708	1			T3	16665		T5	1571		T11	1962
auto[0]	auto[ScrapSt]	216974	1			T10	319		T36	281		T37	2971
auto[0]	auto[EscalateSt]	3819586	1			T4	4686		T5	302		T11	490
auto[0]	auto[InvalidSt]	8346338	1			T4	8760		T5	254		T11	278
auto[1]	auto[ResetSt]	176	1			T52	5		T55	4		T53	4
auto[1]	auto[IdleSt]	109	1			T49	5		T55	2		T57	6
auto[1]	auto[ClkMuxSt]	20	1			T49	1		T50	1		T51	1
auto[1]	auto[CntIncrSt]	32	1			T53	1		T54	2		T56	1
auto[1]	auto[CntProgSt]	812	1			T52	31		T49	20		T55	2
auto[1]	auto[TransCheckSt]	58	1			T55	1		T56	7		T50	7
auto[1]	auto[TokenHashSt]	450	1			T52	8		T49	4		T55	11
auto[1]	auto[FlashRmaSt]	34	1			T52	1		T54	1		T56	1
auto[1]	auto[TokenCheck0St]	46	1			T52	2		T55	2		T54	1
auto[1]	auto[TokenCheck1St]	23	1			T49	1		T53	2		T57	1
auto[1]	auto[TransProgSt]	554	1			T52	10		T49	8		T55	4
auto[1]	auto[PostTransSt]	2022	1			T10	21		T15	4		T16	7
auto[1]	auto[ScrapSt]	56	1			T52	2		T49	1		T55	1
auto[1]	auto[EscalateSt]	1157234	1			T4	2254		T5	196		T10	6917
auto[1]	auto[InvalidSt]	5141	1			T4	23		T5	2		T10	50

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5772274	1			T1	73		T2	110		T3	10265
auto[0]	auto[IdleSt]	15625644	1			T1	6956		T2	194873		T3	9388
auto[0]	auto[ClkMuxSt]	28938	1			T3	90		T5	9		T11	8
auto[0]	auto[CntIncrSt]	28731	1			T3	90		T5	9		T11	8
auto[0]	auto[CntProgSt]	1445843	1			T3	180		T5	446		T11	16
auto[0]	auto[TransCheckSt]	22408	1			T3	90		T5	9		T11	8
auto[0]	auto[TokenHashSt]	16295024	1			T3	24090		T5	171		T11	1836
auto[0]	auto[FlashRmaSt]	27771	1			T5	9		T11	8		T13	80
auto[0]	auto[TokenCheck0St]	10149	1			T5	9		T11	8		T13	29
auto[0]	auto[TokenCheck1St]	7383	1			T5	9		T11	8		T13	13
auto[0]	auto[TransProgSt]	335475	1			T5	304		T11	16		T10	112
auto[0]	auto[PostTransSt]	8017638	1			T3	16665		T5	1571		T11	1962
auto[0]	auto[ScrapSt]	216985	1			T10	319		T36	281		T37	2971
auto[0]	auto[EscalateSt]	3797761	1			T4	4490		T5	400		T11	294
auto[0]	auto[InvalidSt]	8346142	1			T4	8758		T5	255		T11	276
auto[1]	auto[ResetSt]	167	1			T52	4		T49	1		T55	3
auto[1]	auto[IdleSt]	108	1			T49	3		T55	1		T57	7
auto[1]	auto[ClkMuxSt]	22	1			T49	1		T50	1		T218	1
auto[1]	auto[CntIncrSt]	38	1			T52	2		T53	1		T56	1
auto[1]	auto[CntProgSt]	791	1			T52	33		T49	16		T55	2
auto[1]	auto[TransCheckSt]	61	1			T55	3		T56	5		T50	7
auto[1]	auto[TokenHashSt]	451	1			T52	5		T49	4		T55	14
auto[1]	auto[FlashRmaSt]	32	1			T54	1		T57	1		T219	2
auto[1]	auto[TokenCheck0St]	37	1			T52	1		T55	1		T53	1
auto[1]	auto[TokenCheck1St]	21	1			T49	1		T55	1		T57	2
auto[1]	auto[TransProgSt]	563	1			T52	10		T49	13		T55	5
auto[1]	auto[PostTransSt]	2092	1			T10	34		T15	6		T16	5
auto[1]	auto[ScrapSt]	45	1			T52	1		T55	1		T54	3
auto[1]	auto[EscalateSt]	1179059	1			T4	2450		T5	98		T11	196
auto[1]	auto[InvalidSt]	5337	1			T4	25		T5	1		T11	2