Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1045017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1230892

1

T1

1326

T2

947

T9

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1990411	1			T1	1693		T2	826		T10	926
values[0x0]	142418	1			T1	248		T2	330		T9	20
values[0x1]	143080	1			T1	272		T2	326		T9	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	828211	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1447698

1

T1

1518

T2

1066

T9

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7499	1			T2	3		T10	7		T11	2
valid_sources[0x01]	12798	1			T2	7		T10	3		T11	10
valid_sources[0x02]	8075	1			T2	4		T10	4		T11	4
valid_sources[0x03]	7647	1			T2	4		T10	3		T11	13
valid_sources[0x04]	7493	1			T2	7		T10	5		T11	3
valid_sources[0x05]	10171	1			T2	3		T10	8		T11	1
valid_sources[0x06]	7244	1			T2	9		T10	3		T11	8
valid_sources[0x07]	7386	1			T2	2		T10	6		T11	4
valid_sources[0x08]	9480	1			T2	1		T10	4		T14	1
valid_sources[0x09]	8194	1			T2	6		T10	4		T11	2
valid_sources[0x0a]	7755	1			T2	3		T10	3		T11	6
valid_sources[0x0b]	7102	1			T2	2		T10	3		T11	6
valid_sources[0x0c]	7977	1			T2	8		T9	2		T10	5
valid_sources[0x0d]	9248	1			T2	5		T10	6		T11	4
valid_sources[0x0e]	7326	1			T2	6		T10	5		T11	9
valid_sources[0x0f]	7426	1			T2	6		T10	5		T11	3
valid_sources[0x10]	11530	1			T2	10		T10	7		T11	4
valid_sources[0x11]	7343	1			T2	11		T10	3		T11	20
valid_sources[0x12]	7937	1			T2	6		T10	6		T11	4
valid_sources[0x13]	7147	1			T2	10		T10	7		T11	1
valid_sources[0x14]	8152	1			T2	6		T10	4		T11	6
valid_sources[0x15]	7241	1			T2	8		T10	7		T11	1
valid_sources[0x16]	8990	1			T2	7		T10	5		T11	5
valid_sources[0x17]	7601	1			T2	5		T10	7		T11	3
valid_sources[0x18]	7778	1			T2	3		T10	9		T11	6
valid_sources[0x19]	7263	1			T2	6		T10	6		T11	7
valid_sources[0x1a]	7630	1			T2	3		T10	7		T11	1
valid_sources[0x1b]	7513	1			T2	3		T10	10		T11	1
valid_sources[0x1c]	10269	1			T2	2		T10	7		T15	4
valid_sources[0x1d]	15078	1			T2	11		T10	4		T11	2
valid_sources[0x1e]	14788	1			T2	6		T10	2		T14	5
valid_sources[0x1f]	7275	1			T2	6		T10	7		T11	5
valid_sources[0x20]	10095	1			T2	2		T10	3		T11	2
valid_sources[0x21]	7316	1			T2	4		T10	5		T13	1
valid_sources[0x22]	7721	1			T2	9		T10	3		T11	6
valid_sources[0x23]	9632	1			T2	4		T10	9		T11	3
valid_sources[0x24]	7452	1			T2	5		T10	9		T11	10
valid_sources[0x25]	10623	1			T2	5		T10	1		T14	12
valid_sources[0x26]	7480	1			T2	6		T10	3		T11	4
valid_sources[0x27]	7385	1			T2	12		T10	3		T11	1
valid_sources[0x28]	7166	1			T2	6		T10	3		T11	5
valid_sources[0x29]	7461	1			T10	4		T11	1		T14	2
valid_sources[0x2a]	7979	1			T2	9		T10	2		T11	2
valid_sources[0x2b]	7487	1			T2	5		T10	5		T11	11
valid_sources[0x2c]	7464	1			T2	13		T10	6		T11	2
valid_sources[0x2d]	7634	1			T2	7		T10	5		T11	4
valid_sources[0x2e]	7379	1			T2	5		T10	6		T11	9
valid_sources[0x2f]	9074	1			T2	4		T9	1		T10	2
valid_sources[0x30]	7627	1			T2	15		T10	3		T14	3
valid_sources[0x31]	7607	1			T2	4		T10	12		T14	12
valid_sources[0x32]	9845	1			T2	6		T10	6		T11	10
valid_sources[0x33]	7426	1			T2	9		T10	8		T11	9
valid_sources[0x34]	10048	1			T2	11		T9	8		T10	8
valid_sources[0x35]	7257	1			T2	6		T9	3		T10	10
valid_sources[0x36]	20314	1			T2	12		T10	11		T11	2
valid_sources[0x37]	9932	1			T2	5		T10	7		T11	6
valid_sources[0x38]	8430	1			T2	7		T10	6		T11	7
valid_sources[0x39]	7627	1			T2	4		T10	10		T11	4
valid_sources[0x3a]	10352	1			T2	3		T9	1		T10	5
valid_sources[0x3b]	7552	1			T2	7		T10	5		T14	8
valid_sources[0x3c]	7274	1			T2	5		T10	6		T11	4
valid_sources[0x3d]	8284	1			T2	8		T10	3		T11	8
valid_sources[0x3e]	7355	1			T2	5		T10	8		T14	7
valid_sources[0x3f]	7717	1			T2	1		T10	5		T11	2
valid_sources[0x40]	9203	1			T2	5		T10	10		T11	2
valid_sources[0x41]	8690	1			T2	4		T10	6		T11	2
valid_sources[0x42]	7382	1			T2	10		T10	8		T11	9
valid_sources[0x43]	7278	1			T2	4		T10	5		T11	6
valid_sources[0x44]	7197	1			T2	7		T10	13		T11	1
valid_sources[0x45]	7727	1			T2	6		T10	5		T11	2
valid_sources[0x46]	8580	1			T2	14		T10	9		T13	2
valid_sources[0x47]	7311	1			T2	5		T10	4		T14	4
valid_sources[0x48]	7598	1			T2	7		T10	8		T11	8
valid_sources[0x49]	11303	1			T2	8		T10	3		T11	17
valid_sources[0x4a]	7040	1			T2	4		T10	6		T11	4
valid_sources[0x4b]	8120	1			T2	6		T10	9		T11	5
valid_sources[0x4c]	7484	1			T2	8		T10	14		T11	2
valid_sources[0x4d]	7318	1			T2	3		T10	3		T11	9
valid_sources[0x4e]	9044	1			T2	3		T10	3		T11	4
valid_sources[0x4f]	18021	1			T2	3		T10	2		T11	5
valid_sources[0x50]	9453	1			T2	4		T10	6		T11	1
valid_sources[0x51]	7572	1			T2	7		T10	13		T11	3
valid_sources[0x52]	8930	1			T2	11		T9	3		T10	6
valid_sources[0x53]	7449	1			T2	4		T10	7		T11	2
valid_sources[0x54]	9450	1			T1	2213		T2	4		T10	5
valid_sources[0x55]	8309	1			T2	4		T10	5		T11	2
valid_sources[0x56]	16724	1			T2	6		T10	7		T11	13
valid_sources[0x57]	8951	1			T2	4		T10	4		T11	1
valid_sources[0x58]	7323	1			T2	7		T10	6		T11	6
valid_sources[0x59]	7801	1			T2	16		T10	7		T11	3
valid_sources[0x5a]	7280	1			T2	9		T9	1		T10	8
valid_sources[0x5b]	7746	1			T2	8		T9	1		T10	11
valid_sources[0x5c]	13428	1			T2	12		T10	4		T11	1
valid_sources[0x5d]	8513	1			T2	4		T10	8		T11	3
valid_sources[0x5e]	7240	1			T2	3		T10	8		T11	2
valid_sources[0x5f]	7316	1			T2	10		T10	9		T11	1
valid_sources[0x60]	9226	1			T2	5		T9	1		T10	7
valid_sources[0x61]	58044	1			T2	10		T10	4		T11	1
valid_sources[0x62]	7407	1			T2	8		T10	3		T11	5
valid_sources[0x63]	7311	1			T2	9		T9	1		T10	3
valid_sources[0x64]	7602	1			T2	5		T9	3		T10	5
valid_sources[0x65]	7702	1			T2	3		T9	1		T10	6
valid_sources[0x66]	7486	1			T2	7		T10	9		T14	7
valid_sources[0x67]	7623	1			T2	5		T10	6		T11	8
valid_sources[0x68]	7385	1			T2	7		T10	5		T11	4
valid_sources[0x69]	7565	1			T2	6		T10	6		T11	10
valid_sources[0x6a]	7435	1			T2	6		T10	7		T11	2
valid_sources[0x6b]	9806	1			T2	5		T10	4		T11	4
valid_sources[0x6c]	9487	1			T2	4		T10	5		T11	4
valid_sources[0x6d]	8278	1			T2	4		T10	3		T11	6
valid_sources[0x6e]	7306	1			T2	9		T10	5		T11	1
valid_sources[0x6f]	7551	1			T2	7		T10	10		T11	5
valid_sources[0x70]	10269	1			T2	6		T10	6		T11	2
valid_sources[0x71]	7614	1			T2	9		T10	7		T11	7
valid_sources[0x72]	7509	1			T2	12		T10	3		T11	1
valid_sources[0x73]	7604	1			T2	3		T10	4		T11	6
valid_sources[0x74]	7406	1			T2	9		T10	10		T11	1
valid_sources[0x75]	11528	1			T2	9		T10	8		T11	1
valid_sources[0x76]	7228	1			T2	4		T10	7		T14	7
valid_sources[0x77]	9474	1			T2	10		T10	9		T13	1
valid_sources[0x78]	7549	1			T2	7		T10	7		T11	1
valid_sources[0x79]	7332	1			T2	3		T10	5		T14	3
valid_sources[0x7a]	7645	1			T2	7		T10	2		T11	5
valid_sources[0x7b]	7482	1			T2	5		T10	5		T11	8
valid_sources[0x7c]	7372	1			T2	9		T10	5		T11	12
valid_sources[0x7d]	7714	1			T2	2		T10	4		T11	5
valid_sources[0x7e]	7676	1			T2	2		T10	4		T11	2
valid_sources[0x7f]	7491	1			T2	2		T10	9		T11	4
valid_sources[0x80]	10412	1			T2	8		T10	5		T11	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

985257

1

T1

873

T2

375

T10

443

values[0x0]

all_enables

biggest_size

123466

1

T1

217

T2

287

T9

10

values[0x1]

all_enables

biggest_size

122169

1

T1

236

T2

285

T9

5