Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	68393490	16140	0	0
claim_transition_if_regwen_rd_A	68393490	1097	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68393490	16140	0	0
T17	154106	2	0	0
T36	1309	0	0	0
T43	30557	0	0	0
T45	41968	0	0	0
T55	28335	0	0	0
T56	27721	0	0	0
T59	21133	0	0	0
T70	2289	0	0	0
T99	1718	0	0	0
T100	0	2	0	0
T101	0	4	0	0
T102	0	8	0	0
T148	0	29	0	0
T149	0	13	0	0
T150	0	12	0	0
T151	0	5	0	0
T152	0	10	0	0
T153	0	4	0	0
T154	36723	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68393490	1097	0	0
T79	6198	0	0	0
T119	0	9	0	0
T123	0	40	0	0
T125	0	19	0	0
T153	147504	1	0	0
T155	0	6	0	0
T156	0	5	0	0
T157	0	2	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	15	0	0
T161	40840	0	0	0
T162	979	0	0	0
T163	23998	0	0	0
T164	1219	0	0	0
T165	28064	0	0	0
T166	4829	0	0	0
T167	47362	0	0	0
T168	696353	0	0	0