Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	737520	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

928437

1

T1

120

T2

14

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1369788	1			T1	116		T2	67		T3	2
values[0x0]	147711	1			T1	36		T2	12		T4	56
values[0x1]	148458	1			T1	32		T2	4		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	582418	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1083539

1

T1

138

T2

42

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4976	1			T4	3		T12	3		T8	4
valid_sources[0x01]	4382	1			T12	2		T13	5		T16	10
valid_sources[0x02]	4571	1			T1	3		T2	1		T12	11
valid_sources[0x03]	7998	1			T5	2		T12	8		T13	8
valid_sources[0x04]	4234	1			T1	1		T12	6		T8	7
valid_sources[0x05]	4222	1			T4	1		T5	2		T12	3
valid_sources[0x06]	4496	1			T1	3		T12	7		T13	1
valid_sources[0x07]	4658	1			T1	2		T12	5		T13	1
valid_sources[0x08]	11148	1			T4	3		T12	4		T8	2
valid_sources[0x09]	4446	1			T1	1		T5	1		T12	6
valid_sources[0x0a]	9582	1			T1	1		T5	1		T12	5
valid_sources[0x0b]	9169	1			T5	1		T12	3		T14	1
valid_sources[0x0c]	4995	1			T1	1		T5	1		T12	3
valid_sources[0x0d]	9409	1			T5	3		T12	2		T8	13
valid_sources[0x0e]	5830	1			T5	2		T12	7		T13	6
valid_sources[0x0f]	4397	1			T4	7		T5	1		T12	3
valid_sources[0x10]	7344	1			T2	1		T4	2		T5	1
valid_sources[0x11]	4855	1			T2	1		T5	1		T12	2
valid_sources[0x12]	17618	1			T2	3		T12	1		T13	5
valid_sources[0x13]	4730	1			T4	1		T5	1		T12	2
valid_sources[0x14]	4542	1			T12	4		T13	5		T14	7
valid_sources[0x15]	10315	1			T2	1		T12	5		T13	4
valid_sources[0x16]	4363	1			T5	4		T12	10		T14	11
valid_sources[0x17]	5464	1			T1	1		T2	1		T12	8
valid_sources[0x18]	4398	1			T4	3		T5	5		T12	9
valid_sources[0x19]	4559	1			T1	1		T2	1		T5	2
valid_sources[0x1a]	6938	1			T1	3		T4	1		T12	6
valid_sources[0x1b]	4522	1			T1	3		T2	1		T4	2
valid_sources[0x1c]	6288	1			T4	1		T12	2		T13	5
valid_sources[0x1d]	5898	1			T1	1		T5	1		T12	7
valid_sources[0x1e]	5728	1			T12	3		T13	3		T14	3
valid_sources[0x1f]	5745	1			T4	1		T5	2		T12	9
valid_sources[0x20]	4167	1			T1	1		T4	4		T12	7
valid_sources[0x21]	4477	1			T1	2		T4	2		T12	7
valid_sources[0x22]	5942	1			T2	3		T4	2		T12	2
valid_sources[0x23]	4421	1			T1	1		T2	2		T4	1
valid_sources[0x24]	5344	1			T12	2		T13	1		T14	7
valid_sources[0x25]	4273	1			T1	1		T4	1		T5	1
valid_sources[0x26]	4275	1			T1	1		T4	2		T5	2
valid_sources[0x27]	6173	1			T1	2		T12	8		T13	1
valid_sources[0x28]	7805	1			T5	2		T12	3		T13	3
valid_sources[0x29]	6700	1			T12	4		T8	4		T13	3
valid_sources[0x2a]	4716	1			T4	3		T5	1		T12	10
valid_sources[0x2b]	4870	1			T1	1		T12	3		T13	5
valid_sources[0x2c]	4586	1			T5	1		T12	4		T13	2
valid_sources[0x2d]	4701	1			T4	3		T5	4		T12	9
valid_sources[0x2e]	4387	1			T1	1		T4	1		T12	4
valid_sources[0x2f]	4503	1			T2	1		T5	1		T12	3
valid_sources[0x30]	5405	1			T1	1		T12	5		T8	11
valid_sources[0x31]	5295	1			T1	2		T5	3		T8	9
valid_sources[0x32]	4597	1			T1	1		T4	2		T12	6
valid_sources[0x33]	7860	1			T4	1		T12	2		T8	8
valid_sources[0x34]	4641	1			T1	1		T4	1		T5	2
valid_sources[0x35]	4808	1			T5	6		T12	8		T14	1
valid_sources[0x36]	4096	1			T1	2		T5	2		T12	3
valid_sources[0x37]	4446	1			T1	1		T4	3		T12	10
valid_sources[0x38]	4200	1			T2	1		T4	2		T5	2
valid_sources[0x39]	9984	1			T4	2		T5	3		T12	11
valid_sources[0x3a]	4430	1			T1	1		T5	4		T12	3
valid_sources[0x3b]	4296	1			T1	2		T2	2		T4	1
valid_sources[0x3c]	4972	1			T2	1		T4	2		T12	2
valid_sources[0x3d]	7486	1			T2	1		T4	1		T5	1
valid_sources[0x3e]	4555	1			T4	1		T12	2		T8	13
valid_sources[0x3f]	4332	1			T1	1		T12	5		T13	6
valid_sources[0x40]	4306	1			T1	1		T5	1		T12	1
valid_sources[0x41]	5223	1			T5	4		T12	4		T8	9
valid_sources[0x42]	4278	1			T1	3		T5	1		T12	1
valid_sources[0x43]	4094	1			T12	4		T13	5		T14	9
valid_sources[0x44]	7906	1			T12	2		T13	6		T14	11
valid_sources[0x45]	6037	1			T1	1		T12	2		T13	4
valid_sources[0x46]	4457	1			T2	1		T4	1		T5	1
valid_sources[0x47]	4191	1			T5	1		T12	3		T8	12
valid_sources[0x48]	5430	1			T1	1		T4	2		T5	4
valid_sources[0x49]	4610	1			T5	3		T12	2		T13	6
valid_sources[0x4a]	4541	1			T1	1		T12	4		T13	1
valid_sources[0x4b]	4524	1			T1	1		T12	8		T13	4
valid_sources[0x4c]	3997	1			T4	4		T5	4		T12	9
valid_sources[0x4d]	4697	1			T2	1		T14	8		T15	1
valid_sources[0x4e]	5133	1			T12	3		T13	2		T16	2
valid_sources[0x4f]	7095	1			T1	2		T12	8		T13	2
valid_sources[0x50]	4532	1			T1	1		T2	1		T5	2
valid_sources[0x51]	4403	1			T12	8		T14	2		T15	2
valid_sources[0x52]	4543	1			T4	1		T5	1		T12	8
valid_sources[0x53]	6830	1			T1	1		T2	4		T4	1
valid_sources[0x54]	11182	1			T4	3		T5	2		T12	4
valid_sources[0x55]	4501	1			T1	2		T4	4		T5	1
valid_sources[0x56]	5071	1			T2	1		T5	1		T12	5
valid_sources[0x57]	4097	1			T1	2		T5	3		T12	2
valid_sources[0x58]	7725	1			T1	1		T12	8		T13	1
valid_sources[0x59]	4357	1			T1	2		T4	1		T12	7
valid_sources[0x5a]	4773	1			T2	1		T4	5		T5	3
valid_sources[0x5b]	4882	1			T1	1		T4	1		T12	7
valid_sources[0x5c]	5001	1			T2	1		T12	1		T13	6
valid_sources[0x5d]	4844	1			T1	1		T12	2		T13	3
valid_sources[0x5e]	4500	1			T12	4		T13	3		T16	9
valid_sources[0x5f]	12553	1			T5	1		T12	4		T13	1
valid_sources[0x60]	5117	1			T12	4		T13	3		T14	1
valid_sources[0x61]	4388	1			T4	1		T12	3		T13	6
valid_sources[0x62]	5346	1			T1	2		T5	3		T12	4
valid_sources[0x63]	4746	1			T4	3		T12	12		T13	2
valid_sources[0x64]	5459	1			T2	3		T5	2		T12	4
valid_sources[0x65]	4644	1			T4	1		T12	3		T13	3
valid_sources[0x66]	4666	1			T5	1		T12	3		T13	1
valid_sources[0x67]	4547	1			T4	4		T12	5		T13	8
valid_sources[0x68]	4354	1			T5	2		T12	5		T13	6
valid_sources[0x69]	8512	1			T4	4		T5	1		T12	10
valid_sources[0x6a]	4446	1			T4	5		T12	4		T13	2
valid_sources[0x6b]	12079	1			T4	4		T12	8		T13	1
valid_sources[0x6c]	4480	1			T1	1		T4	1		T12	4
valid_sources[0x6d]	5755	1			T2	1		T4	2		T5	1
valid_sources[0x6e]	6337	1			T1	1		T4	1		T5	3
valid_sources[0x6f]	4749	1			T1	3		T4	7		T5	2
valid_sources[0x70]	4578	1			T12	7		T13	5		T14	15
valid_sources[0x71]	4252	1			T1	2		T4	1		T5	1
valid_sources[0x72]	4327	1			T5	1		T12	10		T13	5
valid_sources[0x73]	4474	1			T2	1		T4	2		T5	8
valid_sources[0x74]	4444	1			T4	2		T12	9		T13	5
valid_sources[0x75]	4863	1			T1	2		T5	6		T12	6
valid_sources[0x76]	4279	1			T5	2		T12	5		T13	5
valid_sources[0x77]	5928	1			T4	1		T12	6		T13	6
valid_sources[0x78]	4524	1			T1	1		T12	4		T13	1
valid_sources[0x79]	4238	1			T1	1		T2	1		T4	2
valid_sources[0x7a]	4398	1			T2	1		T5	1		T12	6
valid_sources[0x7b]	4619	1			T4	1		T12	6		T8	9
valid_sources[0x7c]	165636	1			T1	1		T4	2		T12	5
valid_sources[0x7d]	4548	1			T1	3		T2	1		T5	4
valid_sources[0x7e]	5589	1			T5	3		T12	3		T8	4
valid_sources[0x7f]	4236	1			T2	2		T4	1		T5	2
valid_sources[0x80]	9607	1			T1	2		T5	4		T12	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

673968

1

T1

62

T2

1

T3

2

values[0x0]

all_enables

biggest_size

127893

1

T1

32

T2

10

T4

46

values[0x1]

all_enables

biggest_size

126576

1

T1

26

T2

3

T4

48