Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61420364

1

T1

972

T2

29841

T3

8763

auto[1]

1093871

1

T3

198

T4

495

T12

2475

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61428922

1

T1

972

T2

29841

T3

8763

auto[1]

1085313

1

T3

198

T4

297

T12

2673

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5139967	1			T1	67		T2	1406		T3	1304
auto[IdleSt]	16447153	1			T1	52		T2	1455		T3	1925
auto[ClkMuxSt]	28559	1			T1	1		T2	16		T3	9
auto[CntIncrSt]	28411	1			T1	1		T2	16		T3	9
auto[CntProgSt]	1258177	1			T1	9		T2	7112		T3	18
auto[TransCheckSt]	22693	1			T1	1		T2	16		T3	9
auto[TokenHashSt]	18507220	1			T1	21		T2	9406		T3	930
auto[FlashRmaSt]	27779	1			T1	1		T2	66		T3	9
auto[TokenCheck0St]	10050	1			T1	1		T2	16		T3	9
auto[TokenCheck1St]	7192	1			T1	1		T2	16		T3	9
auto[TransProgSt]	339868	1			T1	25		T2	9488		T3	18
auto[PostTransSt]	9212038	1			T1	792		T2	828		T3	2865
auto[ScrapSt]	86512	1			T15	8		T5	413		T46	10
auto[EscalateSt]	4586129	1			T3	1093		T4	1135		T12	6554
auto[InvalidSt]	6811236	1			T3	753		T12	3903		T7	9120

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1251	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6811236	1			T3	753		T12	3903		T7	9120
EscalateSt	4586129	1			T3	1093		T4	1135		T12	6554
ScrapSt	86512	1			T15	8		T5	413		T46	10
PostTransSt	9212038	1			T1	792		T2	828		T3	2865
TransProgSt	339868	1			T1	25		T2	9488		T3	18
TokenCheck1St	7192	1			T1	1		T2	16		T3	9
TokenCheck0St	10050	1			T1	1		T2	16		T3	9
FlashRmaSt	27779	1			T1	1		T2	66		T3	9
TokenHashSt	18507220	1			T1	21		T2	9406		T3	930
TransCheckSt	22693	1			T1	1		T2	16		T3	9
CntProgSt	1258177	1			T1	9		T2	7112		T3	18
CntIncrSt	28411	1			T1	1		T2	16		T3	9
ClkMuxSt	28559	1			T1	1		T2	16		T3	9
IdleSt	16447153	1			T1	52		T2	1455		T3	1925
ResetSt	5139967	1			T1	67		T2	1406		T3	1304
arcs[ResetSt=>IdleSt]	41312	1			T1	1		T2	16		T3	16
arcs[IdleSt=>ScrapSt]	248	1			T15	2		T5	1		T46	6
arcs[IdleSt=>ClkMuxSt]	28443	1			T1	1		T2	16		T3	9
arcs[ClkMuxSt=>CntIncrSt]	28411	1			T1	1		T2	16		T3	9
arcs[CntIncrSt=>PostTransSt]	1290	1			T13	9		T19	9		T43	13
arcs[CntIncrSt=>CntProgSt]	27059	1			T1	1		T2	16		T3	9
arcs[CntProgSt=>PostTransSt]	3459	1			T4	8		T13	5		T6	3
arcs[CntProgSt=>TransCheckSt]	22693	1			T1	1		T2	16		T3	9
arcs[TransCheckSt=>PostTransSt]	3174	1			T13	14		T24	30		T19	9
arcs[TransCheckSt=>TokenHashSt]	19379	1			T1	1		T2	16		T3	9
arcs[TokenHashSt=>PostTransSt]	8397	1			T13	19		T23	5		T24	5
arcs[TokenHashSt=>FlashRmaSt]	10093	1			T1	1		T2	16		T3	9
arcs[FlashRmaSt=>TokenCheck0St]	10050	1			T1	1		T2	16		T3	9
arcs[TokenCheck0St=>PostTransSt]	2812	1			T13	8		T23	11		T24	15
arcs[TokenCheck0St=>TokenCheck1St]	7192	1			T1	1		T2	16		T3	9
arcs[TokenCheck1St=>PostTransSt]	620	1			T23	1		T24	6		T47	12
arcs[TransProgSt=>PostTransSt]	5796	1			T1	1		T2	16		T3	9
arcs[IdleSt=>EscalateSt]	126	1			T66	3		T62	7		T63	7
arcs[ClkMuxSt=>EscalateSt]	32	1			T62	1		T63	1		T64	1
arcs[CntIncrSt=>EscalateSt]	62	1			T15	1		T40	3		T65	1
arcs[CntProgSt=>EscalateSt]	907	1			T15	34		T40	6		T65	2
arcs[TransCheckSt=>EscalateSt]	140	1			T40	4		T65	4		T66	8
arcs[TokenHashSt=>EscalateSt]	889	1			T15	5		T40	34		T65	23
arcs[FlashRmaSt=>EscalateSt]	43	1			T15	3		T40	2		T65	1
arcs[TokenCheck0St=>EscalateSt]	46	1			T15	1		T40	2		T65	1
arcs[TokenCheck1St=>EscalateSt]	26	1			T15	1		T40	1		T69	1
arcs[TransProgSt=>EscalateSt]	750	1			T15	33		T40	9		T65	3
arcs[PostTransSt=>EscalateSt]	3840	1			T4	8		T13	5		T6	3
arcs[InvalidSt=>EscalateSt]	9342	1			T3	4		T12	52		T7	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5139786	1			T1	67		T2	1406		T3	1304
auto[0]	auto[IdleSt]	16447072	1			T1	52		T2	1455		T3	1925
auto[0]	auto[ClkMuxSt]	28540	1			T1	1		T2	16		T3	9
auto[0]	auto[CntIncrSt]	28366	1			T1	1		T2	16		T3	9
auto[0]	auto[CntProgSt]	1257548	1			T1	9		T2	7112		T3	18
auto[0]	auto[TransCheckSt]	22601	1			T1	1		T2	16		T3	9
auto[0]	auto[TokenHashSt]	18506630	1			T1	21		T2	9406		T3	930
auto[0]	auto[FlashRmaSt]	27744	1			T1	1		T2	66		T3	9
auto[0]	auto[TokenCheck0St]	10019	1			T1	1		T2	16		T3	9
auto[0]	auto[TokenCheck1St]	7173	1			T1	1		T2	16		T3	9
auto[0]	auto[TransProgSt]	339358	1			T1	25		T2	9488		T3	18
auto[0]	auto[PostTransSt]	9210050	1			T1	792		T2	828		T3	2865
auto[0]	auto[ScrapSt]	86460	1			T15	7		T5	413		T46	10
auto[0]	auto[EscalateSt]	3501178	1			T3	897		T4	645		T12	4104
auto[0]	auto[InvalidSt]	6806588	1			T3	751		T12	3878		T7	9116
auto[1]	auto[ResetSt]	181	1			T15	5		T40	3		T65	4
auto[1]	auto[IdleSt]	81	1			T66	2		T62	4		T63	4
auto[1]	auto[ClkMuxSt]	19	1			T64	1		T217	1		T177	1
auto[1]	auto[CntIncrSt]	45	1			T15	1		T40	2		T66	1
auto[1]	auto[CntProgSt]	629	1			T15	23		T40	5		T65	1
auto[1]	auto[TransCheckSt]	92	1			T40	4		T65	3		T66	5
auto[1]	auto[TokenHashSt]	590	1			T15	4		T40	26		T65	15
auto[1]	auto[FlashRmaSt]	35	1			T15	2		T40	2		T65	1
auto[1]	auto[TokenCheck0St]	31	1			T40	1		T65	1		T218	1
auto[1]	auto[TokenCheck1St]	19	1			T15	1		T40	1		T69	1
auto[1]	auto[TransProgSt]	510	1			T15	25		T40	7		T65	2
auto[1]	auto[PostTransSt]	1988	1			T4	5		T13	2		T23	2
auto[1]	auto[ScrapSt]	52	1			T15	1		T40	1		T65	1
auto[1]	auto[EscalateSt]	1084951	1			T3	196		T4	490		T12	2450
auto[1]	auto[InvalidSt]	4648	1			T3	2		T12	25		T7	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5139793	1			T1	67		T2	1406		T3	1304
auto[0]	auto[IdleSt]	16447073	1			T1	52		T2	1455		T3	1925
auto[0]	auto[ClkMuxSt]	28537	1			T1	1		T2	16		T3	9
auto[0]	auto[CntIncrSt]	28368	1			T1	1		T2	16		T3	9
auto[0]	auto[CntProgSt]	1257583	1			T1	9		T2	7112		T3	18
auto[0]	auto[TransCheckSt]	22596	1			T1	1		T2	16		T3	9
auto[0]	auto[TokenHashSt]	18506636	1			T1	21		T2	9406		T3	930
auto[0]	auto[FlashRmaSt]	27753	1			T1	1		T2	66		T3	9
auto[0]	auto[TokenCheck0St]	10016	1			T1	1		T2	16		T3	9
auto[0]	auto[TokenCheck1St]	7172	1			T1	1		T2	16		T3	9
auto[0]	auto[TransProgSt]	339351	1			T1	25		T2	9488		T3	18
auto[0]	auto[PostTransSt]	9210068	1			T1	792		T2	828		T3	2865
auto[0]	auto[ScrapSt]	86475	1			T15	7		T5	413		T46	10
auto[0]	auto[EscalateSt]	3509708	1			T3	897		T4	841		T12	3908
auto[0]	auto[InvalidSt]	6806542	1			T3	751		T12	3876		T7	9118
auto[1]	auto[ResetSt]	174	1			T15	5		T40	3		T65	3
auto[1]	auto[IdleSt]	80	1			T66	2		T62	5		T63	6
auto[1]	auto[ClkMuxSt]	22	1			T62	1		T63	1		T64	1
auto[1]	auto[CntIncrSt]	43	1			T15	1		T40	3		T65	1
auto[1]	auto[CntProgSt]	594	1			T15	21		T40	4		T65	1
auto[1]	auto[TransCheckSt]	97	1			T40	3		T65	1		T66	4
auto[1]	auto[TokenHashSt]	584	1			T15	3		T40	19		T65	14
auto[1]	auto[FlashRmaSt]	26	1			T15	2		T40	2		T62	2
auto[1]	auto[TokenCheck0St]	34	1			T15	1		T40	1		T65	1
auto[1]	auto[TokenCheck1St]	20	1			T40	1		T219	1		T62	1
auto[1]	auto[TransProgSt]	517	1			T15	21		T40	8		T65	3
auto[1]	auto[PostTransSt]	1970	1			T4	3		T13	3		T6	3
auto[1]	auto[ScrapSt]	37	1			T15	1		T65	1		T218	1
auto[1]	auto[EscalateSt]	1076421	1			T3	196		T4	294		T12	2646
auto[1]	auto[InvalidSt]	4694	1			T3	2		T12	27		T7	2