Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 97.99 95.86 93.40 100.00 98.55 98.76 96.47


Total tests in report: 998
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
66.77 66.77 81.29 81.29 44.82 44.82 55.66 55.66 58.14 58.14 81.74 81.74 92.04 92.04 53.71 53.71 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.414231388
78.10 11.33 88.33 7.04 72.73 27.90 70.93 15.27 72.09 13.95 87.97 6.22 93.53 1.49 61.13 7.42 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.3703621760
82.95 4.85 95.17 6.84 75.07 2.34 73.32 2.39 81.40 9.30 91.29 3.32 94.28 0.75 70.14 9.01 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.99363444
86.19 3.24 95.22 0.05 79.48 4.41 86.38 13.06 81.40 0.00 92.74 1.45 94.28 0.00 73.85 3.71 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2355693193
87.73 1.54 95.93 0.70 80.29 0.81 88.46 2.08 81.40 0.00 93.98 1.24 94.53 0.25 79.51 5.65 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1313348864
89.26 1.53 95.93 0.00 80.29 0.00 88.46 0.00 90.70 9.30 93.98 0.00 94.53 0.00 80.92 1.41 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.1560467028
90.76 1.51 95.93 0.00 81.64 1.35 88.54 0.08 93.02 2.33 94.40 0.41 95.77 1.24 86.04 5.12 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3453279579
91.93 1.17 96.53 0.60 84.70 3.06 88.72 0.17 93.02 0.00 95.23 0.83 96.27 0.50 89.05 3.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3135525744
92.92 0.99 97.03 0.50 87.04 2.34 89.24 0.53 95.35 2.33 96.27 1.04 96.27 0.00 89.22 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2541119592
93.73 0.81 97.13 0.10 87.76 0.72 89.90 0.66 97.67 2.33 96.68 0.41 96.52 0.25 90.46 1.24 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2043995154
94.25 0.52 97.23 0.10 90.01 2.25 89.90 0.00 97.67 0.00 97.10 0.41 96.52 0.00 91.34 0.88 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.452866332
94.70 0.45 97.38 0.15 91.27 1.26 89.90 0.00 97.67 0.00 97.51 0.41 96.77 0.25 92.40 1.06 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.418314710
95.12 0.42 97.48 0.10 91.63 0.36 90.37 0.47 97.67 0.00 97.93 0.41 96.77 0.00 93.99 1.59 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.631210481
95.45 0.33 97.48 0.00 91.63 0.00 90.37 0.00 100.00 2.33 97.93 0.00 96.77 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.1526170344
95.69 0.24 97.48 0.00 91.90 0.27 91.76 1.40 100.00 0.00 97.93 0.00 96.77 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.4264621344
95.90 0.21 97.48 0.00 91.90 0.00 91.76 0.00 100.00 0.00 97.93 0.00 98.26 1.49 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.165521604
96.10 0.20 97.84 0.35 92.80 0.90 91.89 0.13 100.00 0.00 97.93 0.00 98.26 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.661891671
96.23 0.13 97.84 0.00 93.16 0.36 91.89 0.00 100.00 0.00 97.93 0.00 98.26 0.00 94.52 0.53 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.584546652
96.35 0.13 97.89 0.05 93.34 0.18 91.98 0.09 100.00 0.00 98.13 0.21 98.26 0.00 94.88 0.35 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2446419022
96.47 0.11 97.89 0.00 93.34 0.00 92.76 0.78 100.00 0.00 98.13 0.00 98.26 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1453054828
96.55 0.09 97.89 0.00 93.34 0.00 92.77 0.01 100.00 0.00 98.13 0.00 98.51 0.25 95.23 0.35 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2705802539
96.63 0.08 97.89 0.00 93.34 0.00 93.34 0.57 100.00 0.00 98.13 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1084061549
96.70 0.06 97.89 0.00 93.79 0.45 93.34 0.00 100.00 0.00 98.13 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1862030787
96.76 0.06 97.99 0.10 93.88 0.09 93.34 0.00 100.00 0.00 98.34 0.21 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3202333030
96.81 0.05 97.99 0.00 94.24 0.36 93.34 0.00 100.00 0.00 98.34 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2209586386
96.85 0.04 97.99 0.00 94.33 0.09 93.34 0.00 100.00 0.00 98.55 0.21 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1603134533
96.89 0.04 97.99 0.00 94.60 0.27 93.34 0.00 100.00 0.00 98.55 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1110546151
96.93 0.04 97.99 0.00 94.87 0.27 93.34 0.00 100.00 0.00 98.55 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.926571344
96.96 0.04 97.99 0.00 94.87 0.00 93.34 0.00 100.00 0.00 98.55 0.00 98.76 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3324430172
96.99 0.03 97.99 0.00 94.87 0.00 93.38 0.04 100.00 0.00 98.55 0.00 98.76 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.4122505322
97.02 0.03 97.99 0.00 94.87 0.00 93.39 0.01 100.00 0.00 98.55 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.2042182986
97.05 0.03 97.99 0.00 95.05 0.18 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.325546666
97.07 0.03 97.99 0.00 95.23 0.18 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4054067561
97.10 0.03 97.99 0.00 95.41 0.18 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1389269299
97.12 0.03 97.99 0.00 95.41 0.00 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1435246368
97.15 0.03 97.99 0.00 95.41 0.00 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2814636094
97.17 0.03 97.99 0.00 95.41 0.00 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.146749574
97.20 0.03 97.99 0.00 95.41 0.00 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2593526076
97.22 0.03 97.99 0.00 95.41 0.00 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.47 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3507323521
97.24 0.01 97.99 0.00 95.50 0.09 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3933330172
97.25 0.01 97.99 0.00 95.59 0.09 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2468722965
97.26 0.01 97.99 0.00 95.68 0.09 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.345542110
97.27 0.01 97.99 0.00 95.77 0.09 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.214387026
97.29 0.01 97.99 0.00 95.86 0.09 93.39 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2463576262
97.29 0.01 97.99 0.00 95.86 0.00 93.40 0.01 100.00 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.2385972880

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1783251044
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.86156418
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3218382906
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.497439935
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2171956451
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2251551115
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.378545567
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2948976306
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3824479694
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.35322328
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1280758722
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2460522449
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2101987263
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1382461627
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2676879410
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2828209106
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1708607002
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3284721565
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2579485970
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.557965733
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3392050071
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.501656617
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.958478196
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2284930934
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2840688351
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1473758170
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2979928866
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.950226585
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1304625069
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3597748536
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3999499273
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3196988288
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3523262123
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3463475047
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.746928779
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2982870711
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1911634799
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2306543430
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2174743633
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3469681937
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3219065423
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1057546586
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.147895958
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2398051109
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2638043595
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.157479701
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/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2353746187
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3968404381
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3558785334
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/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1109003318
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/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3772234123
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/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.29364392
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/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2781658388
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/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.582269356



Total test records in report: 998
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2030008192 Aug 23 09:40:59 AM UTC 24 Aug 23 09:41:01 AM UTC 24 40608925 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1771632205 Aug 23 09:40:58 AM UTC 24 Aug 23 09:41:07 AM UTC 24 1193648916 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.862781414 Aug 23 09:41:07 AM UTC 24 Aug 23 09:41:16 AM UTC 24 169106838 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1458547395 Aug 23 09:41:16 AM UTC 24 Aug 23 09:41:19 AM UTC 24 95458987 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1453054828 Aug 23 09:41:02 AM UTC 24 Aug 23 09:41:23 AM UTC 24 196485534 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2941581720 Aug 23 09:41:18 AM UTC 24 Aug 23 09:41:27 AM UTC 24 436345417 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.2042182986 Aug 23 09:41:27 AM UTC 24 Aug 23 09:41:28 AM UTC 24 31007944 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.414231388 Aug 23 09:41:19 AM UTC 24 Aug 23 09:41:30 AM UTC 24 579235572 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3033583748 Aug 23 09:41:28 AM UTC 24 Aug 23 09:41:32 AM UTC 24 368524308 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1361882275 Aug 23 09:41:24 AM UTC 24 Aug 23 09:41:37 AM UTC 24 1591334745 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1019783664 Aug 23 09:41:33 AM UTC 24 Aug 23 09:41:38 AM UTC 24 122356507 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3329603054 Aug 23 09:41:31 AM UTC 24 Aug 23 09:41:43 AM UTC 24 970749941 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.2385972880 Aug 23 09:41:42 AM UTC 24 Aug 23 09:41:48 AM UTC 24 2511613324 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1160142598 Aug 23 09:41:38 AM UTC 24 Aug 23 09:41:52 AM UTC 24 2524015808 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.99363444 Aug 23 09:41:48 AM UTC 24 Aug 23 09:41:58 AM UTC 24 1076876375 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3910085600 Aug 23 09:41:43 AM UTC 24 Aug 23 09:42:00 AM UTC 24 823892900 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.631210481 Aug 23 09:41:54 AM UTC 24 Aug 23 09:42:02 AM UTC 24 978519327 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.661891671 Aug 23 09:42:04 AM UTC 24 Aug 23 09:42:06 AM UTC 24 19120505 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.429027828 Aug 23 09:41:54 AM UTC 24 Aug 23 09:42:06 AM UTC 24 6801915855 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2541119592 Aug 23 09:42:07 AM UTC 24 Aug 23 09:42:09 AM UTC 24 37062192 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1254713075 Aug 23 09:42:06 AM UTC 24 Aug 23 09:42:09 AM UTC 24 138091818 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3716800262 Aug 23 09:42:10 AM UTC 24 Aug 23 09:42:14 AM UTC 24 67720787 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.2346449245 Aug 23 09:42:10 AM UTC 24 Aug 23 09:42:15 AM UTC 24 131295983 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.3703621760 Aug 23 09:41:38 AM UTC 24 Aug 23 09:42:20 AM UTC 24 6342332195 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2043995154 Aug 23 09:42:03 AM UTC 24 Aug 23 09:42:24 AM UTC 24 1604591234 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3992705317 Aug 23 09:42:24 AM UTC 24 Aug 23 09:42:26 AM UTC 24 87460455 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1939409128 Aug 23 09:42:14 AM UTC 24 Aug 23 09:42:27 AM UTC 24 409963051 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2446419022 Aug 23 09:42:16 AM UTC 24 Aug 23 09:42:27 AM UTC 24 1036426915 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2705802539 Aug 23 09:42:21 AM UTC 24 Aug 23 09:42:33 AM UTC 24 844201230 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3843342924 Aug 23 09:42:28 AM UTC 24 Aug 23 09:42:33 AM UTC 24 587851878 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2355693193 Aug 23 09:42:09 AM UTC 24 Aug 23 09:42:37 AM UTC 24 355894797 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1698728430 Aug 23 09:42:28 AM UTC 24 Aug 23 09:42:42 AM UTC 24 776063656 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1110526727 Aug 23 09:41:29 AM UTC 24 Aug 23 09:42:43 AM UTC 24 4555482927 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3135525744 Aug 23 09:42:38 AM UTC 24 Aug 23 09:42:44 AM UTC 24 648344442 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.1987442007 Aug 23 09:42:34 AM UTC 24 Aug 23 09:42:48 AM UTC 24 940164431 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.3161279141 Aug 23 09:42:44 AM UTC 24 Aug 23 09:42:54 AM UTC 24 828022410 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.984624393 Aug 23 09:42:28 AM UTC 24 Aug 23 09:42:56 AM UTC 24 1056612046 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.3859818739 Aug 23 09:42:43 AM UTC 24 Aug 23 09:42:57 AM UTC 24 1135785341 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.3255919352 Aug 23 09:42:48 AM UTC 24 Aug 23 09:42:59 AM UTC 24 3467958359 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2525911858 Aug 23 09:42:44 AM UTC 24 Aug 23 09:43:00 AM UTC 24 2313328992 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.971225341 Aug 23 09:43:01 AM UTC 24 Aug 23 09:43:02 AM UTC 24 54359120 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1003445884 Aug 23 09:43:04 AM UTC 24 Aug 23 09:43:06 AM UTC 24 15409566 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.957883050 Aug 23 09:42:55 AM UTC 24 Aug 23 09:43:07 AM UTC 24 1690751839 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1481769026 Aug 23 09:43:07 AM UTC 24 Aug 23 09:43:08 AM UTC 24 12759336 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2111831097 Aug 23 09:43:09 AM UTC 24 Aug 23 09:43:16 AM UTC 24 198584534 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3997195859 Aug 23 09:42:34 AM UTC 24 Aug 23 09:43:16 AM UTC 24 1433547592 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1313348864 Aug 23 09:42:00 AM UTC 24 Aug 23 09:43:20 AM UTC 24 2355690175 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1141306610 Aug 23 09:43:17 AM UTC 24 Aug 23 09:43:20 AM UTC 24 88774122 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.996780408 Aug 23 09:42:59 AM UTC 24 Aug 23 09:43:20 AM UTC 24 555048240 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.566872846 Aug 23 09:43:21 AM UTC 24 Aug 23 09:43:23 AM UTC 24 22261864 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3692400899 Aug 23 09:43:22 AM UTC 24 Aug 23 09:43:25 AM UTC 24 128267603 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3952349650 Aug 23 09:43:20 AM UTC 24 Aug 23 09:43:27 AM UTC 24 618186409 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.931966532 Aug 23 09:43:08 AM UTC 24 Aug 23 09:43:27 AM UTC 24 362902909 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.593743620 Aug 23 09:43:17 AM UTC 24 Aug 23 09:43:29 AM UTC 24 2160208610 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3727771186 Aug 23 09:43:21 AM UTC 24 Aug 23 09:43:31 AM UTC 24 482833325 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2871819267 Aug 23 09:43:28 AM UTC 24 Aug 23 09:43:32 AM UTC 24 183010470 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1403031616 Aug 23 09:43:31 AM UTC 24 Aug 23 09:44:00 AM UTC 24 1161770168 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.2243074404 Aug 23 09:43:26 AM UTC 24 Aug 23 09:43:32 AM UTC 24 601238092 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.258390008 Aug 23 09:43:30 AM UTC 24 Aug 23 09:43:36 AM UTC 24 2086687287 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.531323201 Aug 23 09:43:25 AM UTC 24 Aug 23 09:43:36 AM UTC 24 2782547400 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.715910102 Aug 23 09:43:32 AM UTC 24 Aug 23 09:43:47 AM UTC 24 2164918615 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.4194239369 Aug 23 09:43:36 AM UTC 24 Aug 23 09:43:49 AM UTC 24 1180474693 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.3387052783 Aug 23 09:43:33 AM UTC 24 Aug 23 09:43:51 AM UTC 24 1998148042 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1053951191 Aug 23 09:43:50 AM UTC 24 Aug 23 09:43:52 AM UTC 24 70005598 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1793952905 Aug 23 09:43:52 AM UTC 24 Aug 23 09:43:54 AM UTC 24 17549729 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2396842979 Aug 23 09:43:52 AM UTC 24 Aug 23 09:43:55 AM UTC 24 33047275 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.229929939 Aug 23 09:43:22 AM UTC 24 Aug 23 09:43:55 AM UTC 24 5907470831 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1355176854 Aug 23 09:43:56 AM UTC 24 Aug 23 09:43:59 AM UTC 24 644979654 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.42269936 Aug 23 09:43:28 AM UTC 24 Aug 23 09:44:02 AM UTC 24 3433365819 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1386953579 Aug 23 09:43:55 AM UTC 24 Aug 23 09:44:02 AM UTC 24 192868323 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2814636094 Aug 23 09:44:03 AM UTC 24 Aug 23 09:44:05 AM UTC 24 22008321 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3695675514 Aug 23 09:44:00 AM UTC 24 Aug 23 09:44:09 AM UTC 24 363488308 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.1830042126 Aug 23 09:44:02 AM UTC 24 Aug 23 09:44:11 AM UTC 24 1262266096 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1781670833 Aug 23 09:44:00 AM UTC 24 Aug 23 09:44:12 AM UTC 24 446349119 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2858443430 Aug 23 09:44:05 AM UTC 24 Aug 23 09:44:16 AM UTC 24 3926005389 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2335911484 Aug 23 09:43:54 AM UTC 24 Aug 23 09:44:18 AM UTC 24 503461436 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2282281582 Aug 23 09:43:50 AM UTC 24 Aug 23 09:44:22 AM UTC 24 836258264 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1645720962 Aug 23 09:44:13 AM UTC 24 Aug 23 09:44:24 AM UTC 24 656771053 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.993890266 Aug 23 09:44:12 AM UTC 24 Aug 23 09:44:31 AM UTC 24 1932375457 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3328997878 Aug 23 09:44:46 AM UTC 24 Aug 23 09:44:51 AM UTC 24 111187236 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.3896631286 Aug 23 09:44:19 AM UTC 24 Aug 23 09:44:36 AM UTC 24 6568532237 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3387731069 Aug 23 09:44:28 AM UTC 24 Aug 23 09:44:37 AM UTC 24 246357113 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1819340605 Aug 23 09:44:27 AM UTC 24 Aug 23 09:44:41 AM UTC 24 603707837 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1553982706 Aug 23 09:44:25 AM UTC 24 Aug 23 09:44:41 AM UTC 24 1081881714 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1584380068 Aug 23 09:44:43 AM UTC 24 Aug 23 09:44:45 AM UTC 24 28057989 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1489292372 Aug 23 09:44:32 AM UTC 24 Aug 23 09:44:47 AM UTC 24 424790733 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1740837701 Aug 23 09:44:10 AM UTC 24 Aug 23 09:44:48 AM UTC 24 5714158532 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1449398379 Aug 23 09:44:48 AM UTC 24 Aug 23 09:44:50 AM UTC 24 23869572 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1729079785 Aug 23 09:44:52 AM UTC 24 Aug 23 09:44:55 AM UTC 24 35570428 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1344304360 Aug 23 09:44:50 AM UTC 24 Aug 23 09:44:57 AM UTC 24 168271068 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2169863154 Aug 23 09:44:23 AM UTC 24 Aug 23 09:44:58 AM UTC 24 6550267880 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2043450112 Aug 23 09:43:48 AM UTC 24 Aug 23 09:45:00 AM UTC 24 10379849283 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.146749574 Aug 23 09:44:59 AM UTC 24 Aug 23 09:45:00 AM UTC 24 17480210 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.1159186507 Aug 23 09:44:42 AM UTC 24 Aug 23 09:45:03 AM UTC 24 190741388 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.4225787716 Aug 23 09:44:57 AM UTC 24 Aug 23 09:45:06 AM UTC 24 2593711071 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.1218169768 Aug 23 09:44:56 AM UTC 24 Aug 23 09:45:07 AM UTC 24 828687133 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.763460809 Aug 23 09:44:55 AM UTC 24 Aug 23 09:45:07 AM UTC 24 1023164430 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.1253592151 Aug 23 09:45:01 AM UTC 24 Aug 23 09:45:07 AM UTC 24 818433269 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.3162603206 Aug 23 09:44:17 AM UTC 24 Aug 23 09:45:08 AM UTC 24 4153812123 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.384885378 Aug 23 09:45:08 AM UTC 24 Aug 23 09:45:14 AM UTC 24 1144878414 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.2701055345 Aug 23 09:45:03 AM UTC 24 Aug 23 09:45:16 AM UTC 24 1764069829 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.183762449 Aug 23 09:44:49 AM UTC 24 Aug 23 09:45:16 AM UTC 24 371232075 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.483854447 Aug 23 09:45:08 AM UTC 24 Aug 23 09:45:17 AM UTC 24 755819609 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.2826421230 Aug 23 09:45:10 AM UTC 24 Aug 23 09:45:19 AM UTC 24 933473201 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1222069695 Aug 23 09:45:19 AM UTC 24 Aug 23 09:45:21 AM UTC 24 44337849 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.3735938587 Aug 23 09:45:04 AM UTC 24 Aug 23 09:45:22 AM UTC 24 1343853895 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.134180700 Aug 23 09:45:22 AM UTC 24 Aug 23 09:45:24 AM UTC 24 15177944 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3454138735 Aug 23 09:45:08 AM UTC 24 Aug 23 09:45:24 AM UTC 24 1053454806 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.3156618189 Aug 23 09:45:16 AM UTC 24 Aug 23 09:45:24 AM UTC 24 1309499193 ps
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T252 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.1157451519 Aug 23 09:45:25 AM UTC 24 Aug 23 09:45:29 AM UTC 24 205056487 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2475053312 Aug 23 09:45:01 AM UTC 24 Aug 23 09:45:30 AM UTC 24 934061348 ps
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T53 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.3588370745 Aug 23 09:45:25 AM UTC 24 Aug 23 09:45:33 AM UTC 24 542975177 ps
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T256 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.1500842934 Aug 23 09:45:33 AM UTC 24 Aug 23 09:45:34 AM UTC 24 11921140 ps
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T258 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2167355379 Aug 23 09:45:38 AM UTC 24 Aug 23 09:45:42 AM UTC 24 231638073 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.417376359 Aug 23 09:45:38 AM UTC 24 Aug 23 09:45:43 AM UTC 24 826461713 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1272398819 Aug 23 09:45:24 AM UTC 24 Aug 23 09:45:43 AM UTC 24 842788589 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.3430250241 Aug 23 09:45:35 AM UTC 24 Aug 23 09:45:48 AM UTC 24 452363206 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.4122505322 Aug 23 09:44:39 AM UTC 24 Aug 23 09:45:49 AM UTC 24 4105965814 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.2744839874 Aug 23 09:45:43 AM UTC 24 Aug 23 09:45:52 AM UTC 24 266287717 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1546707289 Aug 23 09:45:37 AM UTC 24 Aug 23 09:45:53 AM UTC 24 952391675 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3111780142 Aug 23 09:45:54 AM UTC 24 Aug 23 09:45:55 AM UTC 24 42348457 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2068567502 Aug 23 09:45:44 AM UTC 24 Aug 23 09:45:58 AM UTC 24 1657155705 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1105103840 Aug 23 09:46:33 AM UTC 24 Aug 23 09:46:48 AM UTC 24 7426030335 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.500989267 Aug 23 09:45:59 AM UTC 24 Aug 23 09:46:00 AM UTC 24 11453845 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1347219183 Aug 23 09:45:56 AM UTC 24 Aug 23 09:46:02 AM UTC 24 189711556 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.460395857 Aug 23 09:45:42 AM UTC 24 Aug 23 09:46:05 AM UTC 24 931930900 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.572868716 Aug 23 09:46:01 AM UTC 24 Aug 23 09:46:05 AM UTC 24 92038371 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.2157152233 Aug 23 09:46:02 AM UTC 24 Aug 23 09:46:05 AM UTC 24 59518006 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.4084932315 Aug 23 09:46:06 AM UTC 24 Aug 23 09:46:08 AM UTC 24 21466807 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3151461979 Aug 23 09:45:48 AM UTC 24 Aug 23 09:46:10 AM UTC 24 5137376406 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1358963300 Aug 23 09:46:37 AM UTC 24 Aug 23 09:46:39 AM UTC 24 20627156 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.822446383 Aug 23 09:46:08 AM UTC 24 Aug 23 09:46:15 AM UTC 24 686312650 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2043091431 Aug 23 09:45:35 AM UTC 24 Aug 23 09:46:15 AM UTC 24 913701206 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.286104098 Aug 23 09:46:05 AM UTC 24 Aug 23 09:46:16 AM UTC 24 996513851 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.3250574131 Aug 23 09:46:06 AM UTC 24 Aug 23 09:46:16 AM UTC 24 425581898 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3046521454 Aug 23 09:46:03 AM UTC 24 Aug 23 09:46:17 AM UTC 24 319288663 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.263645401 Aug 23 09:46:17 AM UTC 24 Aug 23 09:46:20 AM UTC 24 210757981 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1012747408 Aug 23 09:46:16 AM UTC 24 Aug 23 09:46:21 AM UTC 24 590967784 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.98078744 Aug 23 09:46:01 AM UTC 24 Aug 23 09:46:23 AM UTC 24 550558939 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.2202391310 Aug 23 09:46:13 AM UTC 24 Aug 23 09:46:26 AM UTC 24 1618795427 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2156025750 Aug 23 09:46:15 AM UTC 24 Aug 23 09:46:27 AM UTC 24 1702460927 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.702739538 Aug 23 09:46:18 AM UTC 24 Aug 23 09:46:27 AM UTC 24 638776075 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1026069992 Aug 23 09:45:54 AM UTC 24 Aug 23 09:46:27 AM UTC 24 6239114298 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1390262388 Aug 23 09:45:37 AM UTC 24 Aug 23 09:46:29 AM UTC 24 2025524458 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.3509412902 Aug 23 09:46:27 AM UTC 24 Aug 23 09:46:29 AM UTC 24 54342825 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.258776027 Aug 23 09:46:29 AM UTC 24 Aug 23 09:46:30 AM UTC 24 34664026 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.2932156352 Aug 23 09:46:29 AM UTC 24 Aug 23 09:46:32 AM UTC 24 162402249 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.31317981 Aug 23 09:46:21 AM UTC 24 Aug 23 09:46:34 AM UTC 24 810758941 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2974082950 Aug 23 09:46:31 AM UTC 24 Aug 23 09:46:34 AM UTC 24 359244153 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3043626787 Aug 23 09:46:30 AM UTC 24 Aug 23 09:46:37 AM UTC 24 118966738 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3725555030 Aug 23 09:46:21 AM UTC 24 Aug 23 09:46:39 AM UTC 24 853883951 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.3988463282 Aug 23 09:46:39 AM UTC 24 Aug 23 09:46:45 AM UTC 24 636245901 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.3535705723 Aug 23 09:46:35 AM UTC 24 Aug 23 09:46:44 AM UTC 24 242028925 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1670794026 Aug 23 09:46:35 AM UTC 24 Aug 23 09:46:45 AM UTC 24 407129443 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2528965967 Aug 23 09:46:17 AM UTC 24 Aug 23 09:46:48 AM UTC 24 3168662005 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.2444029624 Aug 23 09:46:47 AM UTC 24 Aug 23 09:46:51 AM UTC 24 246117434 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.2284870527 Aug 23 09:46:45 AM UTC 24 Aug 23 09:46:52 AM UTC 24 1050441428 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3745186106 Aug 23 09:46:49 AM UTC 24 Aug 23 09:46:53 AM UTC 24 480282596 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3796858006 Aug 23 09:46:30 AM UTC 24 Aug 23 09:46:56 AM UTC 24 738158459 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.3971316096 Aug 23 09:46:45 AM UTC 24 Aug 23 09:46:59 AM UTC 24 668478783 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2852602806 Aug 23 09:46:51 AM UTC 24 Aug 23 09:46:59 AM UTC 24 480347115 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3551153469 Aug 23 09:46:11 AM UTC 24 Aug 23 09:46:59 AM UTC 24 8850025798 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.936671940 Aug 23 09:47:00 AM UTC 24 Aug 23 09:47:02 AM UTC 24 41288763 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4281093012 Aug 23 09:47:00 AM UTC 24 Aug 23 09:47:03 AM UTC 24 36745219 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.680486817 Aug 23 09:46:53 AM UTC 24 Aug 23 09:47:04 AM UTC 24 1121071782 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2257694002 Aug 23 09:47:02 AM UTC 24 Aug 23 09:47:04 AM UTC 24 13819635 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3837961664 Aug 23 09:46:54 AM UTC 24 Aug 23 09:47:05 AM UTC 24 1002964540 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3412826198 Aug 23 09:47:05 AM UTC 24 Aug 23 09:47:08 AM UTC 24 63296062 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.1573747631 Aug 23 09:48:25 AM UTC 24 Aug 23 09:48:35 AM UTC 24 1457863532 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.1669009059 Aug 23 09:46:24 AM UTC 24 Aug 23 09:47:10 AM UTC 24 4552523429 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.55824468 Aug 23 09:47:05 AM UTC 24 Aug 23 09:47:12 AM UTC 24 72535640 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2593526076 Aug 23 09:47:11 AM UTC 24 Aug 23 09:47:13 AM UTC 24 12845990 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1536462368 Aug 23 09:46:49 AM UTC 24 Aug 23 09:47:13 AM UTC 24 1023186615 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1631345888 Aug 23 09:47:12 AM UTC 24 Aug 23 09:47:15 AM UTC 24 164391126 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.10699935 Aug 23 09:46:39 AM UTC 24 Aug 23 09:47:18 AM UTC 24 1263669369 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.394670401 Aug 23 09:47:06 AM UTC 24 Aug 23 09:47:19 AM UTC 24 1033845779 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1336071861 Aug 23 09:47:09 AM UTC 24 Aug 23 09:47:19 AM UTC 24 2456919068 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2848463448 Aug 23 09:47:15 AM UTC 24 Aug 23 09:47:22 AM UTC 24 1555371277 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2353746187 Aug 23 09:47:11 AM UTC 24 Aug 23 09:47:22 AM UTC 24 431500223 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3009147407 Aug 23 09:47:20 AM UTC 24 Aug 23 09:47:23 AM UTC 24 384466859 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3185087464 Aug 23 09:46:46 AM UTC 24 Aug 23 09:47:23 AM UTC 24 1343179303 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3079073973 Aug 23 09:47:05 AM UTC 24 Aug 23 09:47:26 AM UTC 24 1510228181 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.270198230 Aug 23 09:45:49 AM UTC 24 Aug 23 09:47:29 AM UTC 24 13558257825 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.2342193680 Aug 23 09:47:14 AM UTC 24 Aug 23 09:47:31 AM UTC 24 680033269 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1195955240 Aug 23 09:47:24 AM UTC 24 Aug 23 09:47:31 AM UTC 24 3638866584 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3968404381 Aug 23 09:47:24 AM UTC 24 Aug 23 09:47:33 AM UTC 24 1474746488 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1736677190 Aug 23 09:47:20 AM UTC 24 Aug 23 09:47:33 AM UTC 24 587313596 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.64277313 Aug 23 09:47:31 AM UTC 24 Aug 23 09:47:33 AM UTC 24 186919533 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.582269356 Aug 23 09:47:34 AM UTC 24 Aug 23 09:47:35 AM UTC 24 44260153 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.29364392 Aug 23 09:47:32 AM UTC 24 Aug 23 09:47:36 AM UTC 24 1499377834 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3558785334 Aug 23 09:47:24 AM UTC 24 Aug 23 09:47:37 AM UTC 24 1182347747 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.3540593939 Aug 23 09:47:36 AM UTC 24 Aug 23 09:47:38 AM UTC 24 29115225 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2463576262 Aug 23 09:46:16 AM UTC 24 Aug 23 09:47:43 AM UTC 24 3586248848 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3737153070 Aug 23 09:47:23 AM UTC 24 Aug 23 09:47:43 AM UTC 24 3423169527 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3603109900 Aug 23 09:47:34 AM UTC 24 Aug 23 09:47:43 AM UTC 24 65375461 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3507323521 Aug 23 09:47:43 AM UTC 24 Aug 23 09:47:45 AM UTC 24 35232885 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.281459137 Aug 23 09:47:38 AM UTC 24 Aug 23 09:47:47 AM UTC 24 393568821 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1065394328 Aug 23 09:47:39 AM UTC 24 Aug 23 09:47:48 AM UTC 24 363259054 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3669795516 Aug 23 09:47:30 AM UTC 24 Aug 23 09:47:49 AM UTC 24 885648780 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1757000116 Aug 23 09:47:37 AM UTC 24 Aug 23 09:47:49 AM UTC 24 1159251910 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.538303791 Aug 23 09:47:34 AM UTC 24 Aug 23 09:47:49 AM UTC 24 166435635 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1109003318 Aug 23 09:47:45 AM UTC 24 Aug 23 09:47:51 AM UTC 24 292591054 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2289367916 Aug 23 09:47:44 AM UTC 24 Aug 23 09:47:54 AM UTC 24 388016578 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2052803335 Aug 23 09:47:47 AM UTC 24 Aug 23 09:47:58 AM UTC 24 2570932192 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.1728277839 Aug 23 09:47:49 AM UTC 24 Aug 23 09:47:58 AM UTC 24 673600833 ps
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T329 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.4158581601 Aug 23 09:47:49 AM UTC 24 Aug 23 09:47:58 AM UTC 24 10027506320 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.1663889356 Aug 23 09:47:59 AM UTC 24 Aug 23 09:48:01 AM UTC 24 23265707 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.1789128597 Aug 23 09:48:02 AM UTC 24 Aug 23 09:48:07 AM UTC 24 628900194 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3772234123 Aug 23 09:47:53 AM UTC 24 Aug 23 09:48:09 AM UTC 24 721209142 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3626946521 Aug 23 09:47:20 AM UTC 24 Aug 23 09:48:10 AM UTC 24 11577524098 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3533261408 Aug 23 09:48:07 AM UTC 24 Aug 23 09:48:10 AM UTC 24 82386011 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2212540985 Aug 23 09:47:55 AM UTC 24 Aug 23 09:48:11 AM UTC 24 534983987 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1206855772 Aug 23 09:47:51 AM UTC 24 Aug 23 09:48:12 AM UTC 24 3390685526 ps
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T337 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.660453917 Aug 23 09:48:11 AM UTC 24 Aug 23 09:48:14 AM UTC 24 103772269 ps
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T338 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2825563619 Aug 23 09:47:58 AM UTC 24 Aug 23 09:48:19 AM UTC 24 789832003 ps
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T340 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2567458574 Aug 23 09:48:12 AM UTC 24 Aug 23 09:48:24 AM UTC 24 284755063 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1435246368 Aug 23 09:48:13 AM UTC 24 Aug 23 09:48:24 AM UTC 24 284109333 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.3726082701 Aug 23 09:48:21 AM UTC 24 Aug 23 09:48:26 AM UTC 24 1194365595 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2798122357 Aug 23 09:44:37 AM UTC 24 Aug 23 09:48:27 AM UTC 24 6811250383 ps
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T344 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.756927902 Aug 23 09:48:20 AM UTC 24 Aug 23 09:48:29 AM UTC 24 519253663 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2404942927 Aug 23 09:48:29 AM UTC 24 Aug 23 09:48:31 AM UTC 24 18301765 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1815797373 Aug 23 09:48:18 AM UTC 24 Aug 23 09:48:33 AM UTC 24 582638744 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1338989895 Aug 23 09:48:25 AM UTC 24 Aug 23 09:48:33 AM UTC 24 425216829 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.2816643594 Aug 23 09:48:09 AM UTC 24 Aug 23 09:48:35 AM UTC 24 851696320 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1115393393 Aug 23 09:48:32 AM UTC 24 Aug 23 09:48:36 AM UTC 24 160171168 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4126256465 Aug 23 09:48:34 AM UTC 24 Aug 23 09:48:36 AM UTC 24 31568939 ps
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T352 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.680330904 Aug 23 09:48:36 AM UTC 24 Aug 23 09:48:43 AM UTC 24 152642138 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1637945009 Aug 23 09:48:37 AM UTC 24 Aug 23 09:48:45 AM UTC 24 588018257 ps
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T354 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.874161664 Aug 23 09:48:44 AM UTC 24 Aug 23 09:48:49 AM UTC 24 747542149 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.3652333966 Aug 23 09:48:37 AM UTC 24 Aug 23 09:48:49 AM UTC 24 340934185 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.4048919128 Aug 23 09:48:48 AM UTC 24 Aug 23 09:48:53 AM UTC 24 937674430 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.3777037908 Aug 23 09:48:21 AM UTC 24 Aug 23 09:48:56 AM UTC 24 11067991535 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2111992387 Aug 23 09:48:40 AM UTC 24 Aug 23 09:48:57 AM UTC 24 2043162494 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2631513627 Aug 23 09:48:50 AM UTC 24 Aug 23 09:49:00 AM UTC 24 2551609529 ps