Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55585843

1

T1

1578

T2

905

T3

3817

auto[1]

1137457

1

T4

891

T10

490

T13

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55594957

1

T1

1578

T2

905

T3

3817

auto[1]

1128343

1

T4

297

T10

882

T13

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5379731	1			T1	108		T2	93		T3	1509
auto[IdleSt]	15159689	1			T1	188		T2	812		T3	1241
auto[ClkMuxSt]	29633	1			T1	1		T3	14		T4	12
auto[CntIncrSt]	29472	1			T1	1		T3	14		T4	12
auto[CntProgSt]	1161424	1			T1	44		T3	63		T4	783
auto[TransCheckSt]	23166	1			T1	1		T3	14		T5	2
auto[TokenHashSt]	14374962	1			T1	239		T3	150		T5	450
auto[FlashRmaSt]	29279	1			T1	1		T3	14		T5	24
auto[TokenCheck0St]	10420	1			T1	1		T3	14		T5	2
auto[TokenCheck1St]	7538	1			T1	1		T3	14		T5	2
auto[TransProgSt]	300367	1			T1	47		T3	53		T5	94
auto[PostTransSt]	8402429	1			T1	946		T3	717		T4	731
auto[ScrapSt]	124154	1			T44	4		T45	1563		T46	4
auto[EscalateSt]	4662705	1			T4	1501		T10	4905		T13	1217
auto[InvalidSt]	7026918	1			T13	694		T15	5115		T17	944

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1413	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7026918	1			T13	694		T15	5115		T17	944
EscalateSt	4662705	1			T4	1501		T10	4905		T13	1217
ScrapSt	124154	1			T44	4		T45	1563		T46	4
PostTransSt	8402429	1			T1	946		T3	717		T4	731
TransProgSt	300367	1			T1	47		T3	53		T5	94
TokenCheck1St	7538	1			T1	1		T3	14		T5	2
TokenCheck0St	10420	1			T1	1		T3	14		T5	2
FlashRmaSt	29279	1			T1	1		T3	14		T5	24
TokenHashSt	14374962	1			T1	239		T3	150		T5	450
TransCheckSt	23166	1			T1	1		T3	14		T5	2
CntProgSt	1161424	1			T1	44		T3	63		T4	783
CntIncrSt	29472	1			T1	1		T3	14		T4	12
ClkMuxSt	29633	1			T1	1		T3	14		T4	12
IdleSt	15159689	1			T1	188		T2	812		T3	1241
ResetSt	5379731	1			T1	108		T2	93		T3	1509
arcs[ResetSt=>IdleSt]	42905	1			T1	1		T2	1		T3	14
arcs[IdleSt=>ScrapSt]	231	1			T44	1		T45	1		T46	3
arcs[IdleSt=>ClkMuxSt]	29507	1			T1	1		T3	14		T4	12
arcs[ClkMuxSt=>CntIncrSt]	29472	1			T1	1		T3	14		T4	12
arcs[CntIncrSt=>PostTransSt]	1367	1			T38	12		T39	5		T42	12
arcs[CntIncrSt=>CntProgSt]	28036	1			T1	1		T3	14		T4	12
arcs[CntProgSt=>PostTransSt]	3809	1			T4	12		T10	14		T16	5
arcs[CntProgSt=>TransCheckSt]	23166	1			T1	1		T3	14		T5	2
arcs[TransCheckSt=>PostTransSt]	3378	1			T35	51		T38	15		T39	7
arcs[TransCheckSt=>TokenHashSt]	19667	1			T1	1		T3	14		T5	2
arcs[TokenHashSt=>PostTransSt]	8440	1			T17	5		T37	60		T35	8
arcs[TokenHashSt=>FlashRmaSt]	10466	1			T1	1		T3	14		T5	2
arcs[FlashRmaSt=>TokenCheck0St]	10420	1			T1	1		T3	14		T5	2
arcs[TokenCheck0St=>PostTransSt]	2829	1			T17	10		T35	27		T38	12
arcs[TokenCheck0St=>TokenCheck1St]	7538	1			T1	1		T3	14		T5	2
arcs[TokenCheck1St=>PostTransSt]	620	1			T17	1		T35	13		T39	1
arcs[TransProgSt=>PostTransSt]	6058	1			T1	1		T3	14		T5	2
arcs[IdleSt=>EscalateSt]	144	1			T14	5		T44	7		T62	6
arcs[ClkMuxSt=>EscalateSt]	35	1			T14	1		T44	2		T62	3
arcs[CntIncrSt=>EscalateSt]	69	1			T14	1		T44	1		T62	1
arcs[CntProgSt=>EscalateSt]	1061	1			T14	15		T44	2		T62	33
arcs[TransCheckSt=>EscalateSt]	121	1			T14	2		T44	4		T64	1
arcs[TokenHashSt=>EscalateSt]	761	1			T14	13		T44	23		T62	9
arcs[FlashRmaSt=>EscalateSt]	46	1			T14	1		T44	1		T62	1
arcs[TokenCheck0St=>EscalateSt]	53	1			T44	1		T65	1		T66	1
arcs[TokenCheck1St=>EscalateSt]	28	1			T62	1		T63	2		T64	1
arcs[TransProgSt=>EscalateSt]	832	1			T14	15		T44	11		T62	24
arcs[PostTransSt=>EscalateSt]	4157	1			T4	12		T10	14		T14	2
arcs[InvalidSt=>EscalateSt]	9682	1			T13	5		T15	4		T17	12

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5379546	1			T1	108		T2	93		T3	1509
auto[0]	auto[IdleSt]	15159594	1			T1	188		T2	812		T3	1241
auto[0]	auto[ClkMuxSt]	29613	1			T1	1		T3	14		T4	12
auto[0]	auto[CntIncrSt]	29427	1			T1	1		T3	14		T4	12
auto[0]	auto[CntProgSt]	1160715	1			T1	44		T3	63		T4	783
auto[0]	auto[TransCheckSt]	23080	1			T1	1		T3	14		T5	2
auto[0]	auto[TokenHashSt]	14374458	1			T1	239		T3	150		T5	450
auto[0]	auto[FlashRmaSt]	29250	1			T1	1		T3	14		T5	24
auto[0]	auto[TokenCheck0St]	10384	1			T1	1		T3	14		T5	2
auto[0]	auto[TokenCheck1St]	7519	1			T1	1		T3	14		T5	2
auto[0]	auto[TransProgSt]	299819	1			T1	47		T3	53		T5	94
auto[0]	auto[PostTransSt]	8400320	1			T1	946		T3	717		T4	722
auto[0]	auto[ScrapSt]	124113	1			T44	4		T45	1563		T46	4
auto[0]	auto[EscalateSt]	3534550	1			T4	619		T10	4420		T13	923
auto[0]	auto[InvalidSt]	7022042	1			T13	691		T15	5114		T17	942
auto[1]	auto[ResetSt]	185	1			T14	3		T44	5		T62	3
auto[1]	auto[IdleSt]	95	1			T14	4		T44	6		T62	4
auto[1]	auto[ClkMuxSt]	20	1			T44	1		T62	3		T64	1
auto[1]	auto[CntIncrSt]	45	1			T14	1		T62	1		T63	1
auto[1]	auto[CntProgSt]	709	1			T14	11		T62	22		T63	18
auto[1]	auto[TransCheckSt]	86	1			T14	2		T44	4		T215	6
auto[1]	auto[TokenHashSt]	504	1			T14	6		T44	15		T62	8
auto[1]	auto[FlashRmaSt]	29	1			T14	1		T62	1		T65	1
auto[1]	auto[TokenCheck0St]	36	1			T44	1		T216	1		T215	1
auto[1]	auto[TokenCheck1St]	19	1			T62	1		T63	1		T66	1
auto[1]	auto[TransProgSt]	548	1			T14	12		T44	7		T62	15
auto[1]	auto[PostTransSt]	2109	1			T4	9		T10	5		T14	2
auto[1]	auto[ScrapSt]	41	1			T63	2		T64	1		T65	1
auto[1]	auto[EscalateSt]	1128155	1			T4	882		T10	485		T13	294
auto[1]	auto[InvalidSt]	4876	1			T13	3		T15	1		T17	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5379530	1			T1	108		T2	93		T3	1509
auto[0]	auto[IdleSt]	15159595	1			T1	188		T2	812		T3	1241
auto[0]	auto[ClkMuxSt]	29609	1			T1	1		T3	14		T4	12
auto[0]	auto[CntIncrSt]	29428	1			T1	1		T3	14		T4	12
auto[0]	auto[CntProgSt]	1160746	1			T1	44		T3	63		T4	783
auto[0]	auto[TransCheckSt]	23084	1			T1	1		T3	14		T5	2
auto[0]	auto[TokenHashSt]	14374462	1			T1	239		T3	150		T5	450
auto[0]	auto[FlashRmaSt]	29249	1			T1	1		T3	14		T5	24
auto[0]	auto[TokenCheck0St]	10391	1			T1	1		T3	14		T5	2
auto[0]	auto[TokenCheck1St]	7519	1			T1	1		T3	14		T5	2
auto[0]	auto[TransProgSt]	299819	1			T1	47		T3	53		T5	94
auto[0]	auto[PostTransSt]	8400288	1			T1	946		T3	717		T4	728
auto[0]	auto[ScrapSt]	124111	1			T44	3		T45	1563		T46	4
auto[0]	auto[EscalateSt]	3543601	1			T4	1207		T10	4032		T13	1021
auto[0]	auto[InvalidSt]	7022112	1			T13	692		T15	5112		T17	934
auto[1]	auto[ResetSt]	201	1			T14	3		T44	4		T62	6
auto[1]	auto[IdleSt]	94	1			T14	5		T44	2		T62	5
auto[1]	auto[ClkMuxSt]	24	1			T14	1		T44	1		T62	1
auto[1]	auto[CntIncrSt]	44	1			T44	1		T63	1		T64	1
auto[1]	auto[CntProgSt]	678	1			T14	8		T44	2		T62	23
auto[1]	auto[TransCheckSt]	82	1			T64	1		T217	1		T215	6
auto[1]	auto[TokenHashSt]	500	1			T14	9		T44	17		T62	6
auto[1]	auto[FlashRmaSt]	30	1			T44	1		T65	2		T66	2
auto[1]	auto[TokenCheck0St]	29	1			T65	1		T66	1		T215	2
auto[1]	auto[TokenCheck1St]	19	1			T62	1		T63	2		T64	1
auto[1]	auto[TransProgSt]	548	1			T14	8		T44	9		T62	17
auto[1]	auto[PostTransSt]	2141	1			T4	3		T10	9		T16	1
auto[1]	auto[ScrapSt]	43	1			T44	1		T63	2		T64	1
auto[1]	auto[EscalateSt]	1119104	1			T4	294		T10	873		T13	196
auto[1]	auto[InvalidSt]	4806	1			T13	2		T15	3		T17	10