| Name |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3835704565 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4135867868 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3364201388 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3676617488 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3334165460 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3639190849 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.78581340 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3760008273 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1044135331 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1893110045 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2710565190 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2522925074 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.973605538 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3628318333 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.241716134 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2505788999 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1317068949 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3870389525 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.89125111 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2022262857 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1768320526 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1341142226 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1733088973 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1299602636 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.287181197 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1535057267 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2642388553 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.583188239 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2852776801 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1388199545 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1469792382 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3858555415 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.980874639 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3140359223 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1725247395 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2152361629 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3562443512 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3289847756 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3876671908 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3975321821 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.147197135 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2194174149 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.4079265356 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2593070939 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1962438341 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.169888838 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3214453491 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2464403941 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1868600367 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3027722634 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.306015289 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.221386550 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1229671883 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1848532019 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.420478940 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1779625878 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1882890635 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2832152822 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3843706286 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1034585212 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1733158883 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2564918108 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1216126030 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2125667910 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2652819851 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2868458878 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4149858428 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3399733737 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3451376044 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2260291523 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1719823753 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3360586608 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.765819179 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4262166298 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1991986080 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.972085116 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1310817827 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4047755466 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2363743934 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2794536157 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3864974151 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2231283636 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4281308937 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4258538510 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1918370339 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3197389367 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2336895842 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2943085359 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3316053174 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4277526361 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1915098901 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4180457372 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2737267346 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.580558284 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.399561182 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1869891770 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1402347619 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.967779691 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1542821502 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3212599770 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2824261964 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3363011714 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3747136451 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2327446298 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2832501308 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3436779249 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3068010572 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1594386909 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.4000596816 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1268363542 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3710938654 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1387742088 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.798298929 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.383717413 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3176449413 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.496150183 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.619141539 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.895796157 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3537785308 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3924588536 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4031541526 |
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| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3520055017 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.232377018 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2416457972 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3620566083 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.2373692507 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3728494780 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.902726669 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1118995812 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1765855647 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3883370144 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1583272893 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1033298882 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.153250904 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1816762585 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3209979892 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.120467535 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1336873503 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2988125716 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1571269340 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.275405087 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.4218330144 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1854032587 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.4190194567 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1817873334 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.2250064299 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1431866926 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1218532623 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.3431856569 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1991206871 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.628440584 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2859470054 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3429201568 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1652133482 |
| /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2265922193 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.4257119214 |
|
|
Aug 25 10:28:34 AM UTC 24 |
Aug 25 10:28:37 AM UTC 24 |
32225781 ps |
| T2 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.2551844765 |
|
|
Aug 25 10:28:35 AM UTC 24 |
Aug 25 10:28:38 AM UTC 24 |
37822192 ps |
| T3 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.3599806645 |
|
|
Aug 25 10:28:33 AM UTC 24 |
Aug 25 10:28:38 AM UTC 24 |
545392786 ps |
| T4 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3479018825 |
|
|
Aug 25 10:28:35 AM UTC 24 |
Aug 25 10:28:40 AM UTC 24 |
204172487 ps |
| T5 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.995590242 |
|
|
Aug 25 10:28:36 AM UTC 24 |
Aug 25 10:28:40 AM UTC 24 |
69996048 ps |
| T6 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3663544186 |
|
|
Aug 25 10:28:37 AM UTC 24 |
Aug 25 10:28:42 AM UTC 24 |
480952627 ps |
| T11 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.361418932 |
|
|
Aug 25 10:28:35 AM UTC 24 |
Aug 25 10:28:44 AM UTC 24 |
421068113 ps |
| T7 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3300439642 |
|
|
Aug 25 10:28:38 AM UTC 24 |
Aug 25 10:28:45 AM UTC 24 |
122030472 ps |
| T10 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.471865310 |
|
|
Aug 25 10:28:36 AM UTC 24 |
Aug 25 10:28:47 AM UTC 24 |
261148573 ps |
| T12 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.3037829341 |
|
|
Aug 25 10:28:45 AM UTC 24 |
Aug 25 10:28:48 AM UTC 24 |
39325262 ps |
| T22 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.2215436261 |
|
|
Aug 25 10:28:45 AM UTC 24 |
Aug 25 10:28:48 AM UTC 24 |
33947201 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3204974140 |
|
|
Aug 25 10:28:35 AM UTC 24 |
Aug 25 10:28:49 AM UTC 24 |
610797390 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.538409046 |
|
|
Aug 25 10:28:47 AM UTC 24 |
Aug 25 10:28:50 AM UTC 24 |
31081367 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1856956077 |
|
|
Aug 25 10:28:35 AM UTC 24 |
Aug 25 10:28:50 AM UTC 24 |
466453099 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.4199610256 |
|
|
Aug 25 10:28:36 AM UTC 24 |
Aug 25 10:28:52 AM UTC 24 |
830245079 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1606961219 |
|
|
Aug 25 10:28:50 AM UTC 24 |
Aug 25 10:28:53 AM UTC 24 |
150089324 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.300385715 |
|
|
Aug 25 10:28:39 AM UTC 24 |
Aug 25 10:28:54 AM UTC 24 |
377334156 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.632140370 |
|
|
Aug 25 10:28:53 AM UTC 24 |
Aug 25 10:28:56 AM UTC 24 |
14776393 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2648592189 |
|
|
Aug 25 10:28:41 AM UTC 24 |
Aug 25 10:28:56 AM UTC 24 |
1070932074 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.2780581356 |
|
|
Aug 25 10:28:39 AM UTC 24 |
Aug 25 10:28:59 AM UTC 24 |
1239191673 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2842107913 |
|
|
Aug 25 10:28:35 AM UTC 24 |
Aug 25 10:29:02 AM UTC 24 |
2360143455 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2761827767 |
|
|
Aug 25 10:28:51 AM UTC 24 |
Aug 25 10:29:04 AM UTC 24 |
368701946 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1650640832 |
|
|
Aug 25 10:28:51 AM UTC 24 |
Aug 25 10:29:05 AM UTC 24 |
194300806 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.2875864290 |
|
|
Aug 25 10:28:48 AM UTC 24 |
Aug 25 10:29:08 AM UTC 24 |
59185201 ps |
| T8 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.1460047937 |
|
|
Aug 25 10:29:03 AM UTC 24 |
Aug 25 10:29:09 AM UTC 24 |
174923029 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1869991387 |
|
|
Aug 25 10:28:51 AM UTC 24 |
Aug 25 10:29:09 AM UTC 24 |
288303816 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.2741386071 |
|
|
Aug 25 10:28:54 AM UTC 24 |
Aug 25 10:29:11 AM UTC 24 |
1771241666 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1307969060 |
|
|
Aug 25 10:28:38 AM UTC 24 |
Aug 25 10:29:12 AM UTC 24 |
1069459106 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.3026403853 |
|
|
Aug 25 10:28:34 AM UTC 24 |
Aug 25 10:29:12 AM UTC 24 |
406427033 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.68968477 |
|
|
Aug 25 10:29:13 AM UTC 24 |
Aug 25 10:29:15 AM UTC 24 |
68901816 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.9029597 |
|
|
Aug 25 10:28:57 AM UTC 24 |
Aug 25 10:29:16 AM UTC 24 |
1575689317 ps |
| T31 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3435800060 |
|
|
Aug 25 10:29:16 AM UTC 24 |
Aug 25 10:29:19 AM UTC 24 |
14115209 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.302247202 |
|
|
Aug 25 10:29:08 AM UTC 24 |
Aug 25 10:29:23 AM UTC 24 |
441864501 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.3735175343 |
|
|
Aug 25 10:29:13 AM UTC 24 |
Aug 25 10:29:24 AM UTC 24 |
239663986 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3453501167 |
|
|
Aug 25 10:28:56 AM UTC 24 |
Aug 25 10:29:27 AM UTC 24 |
871139395 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1053838822 |
|
|
Aug 25 10:28:48 AM UTC 24 |
Aug 25 10:29:29 AM UTC 24 |
1745692063 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.1063887359 |
|
|
Aug 25 10:29:09 AM UTC 24 |
Aug 25 10:29:29 AM UTC 24 |
287050754 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.1316018966 |
|
|
Aug 25 10:28:37 AM UTC 24 |
Aug 25 10:29:30 AM UTC 24 |
1890866679 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.2294774200 |
|
|
Aug 25 10:29:24 AM UTC 24 |
Aug 25 10:29:30 AM UTC 24 |
113360209 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1787862384 |
|
|
Aug 25 10:29:30 AM UTC 24 |
Aug 25 10:29:32 AM UTC 24 |
10457804 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3480937294 |
|
|
Aug 25 10:29:19 AM UTC 24 |
Aug 25 10:29:32 AM UTC 24 |
146962073 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.2999874354 |
|
|
Aug 25 10:29:09 AM UTC 24 |
Aug 25 10:29:34 AM UTC 24 |
10465690765 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2477524077 |
|
|
Aug 25 10:29:30 AM UTC 24 |
Aug 25 10:29:34 AM UTC 24 |
85922376 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.1427931880 |
|
|
Aug 25 10:29:05 AM UTC 24 |
Aug 25 10:29:35 AM UTC 24 |
1758559847 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.316177954 |
|
|
Aug 25 10:29:06 AM UTC 24 |
Aug 25 10:29:38 AM UTC 24 |
5129705617 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.4241091626 |
|
|
Aug 25 10:29:24 AM UTC 24 |
Aug 25 10:29:40 AM UTC 24 |
4145909251 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2924031310 |
|
|
Aug 25 10:29:29 AM UTC 24 |
Aug 25 10:29:40 AM UTC 24 |
508781994 ps |
| T9 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.429107904 |
|
|
Aug 25 10:29:34 AM UTC 24 |
Aug 25 10:29:43 AM UTC 24 |
371631479 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3583942178 |
|
|
Aug 25 10:28:44 AM UTC 24 |
Aug 25 10:30:10 AM UTC 24 |
216579283 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.172990728 |
|
|
Aug 25 10:29:33 AM UTC 24 |
Aug 25 10:29:46 AM UTC 24 |
625289893 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1102709111 |
|
|
Aug 25 10:29:26 AM UTC 24 |
Aug 25 10:29:47 AM UTC 24 |
554715517 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1326577313 |
|
|
Aug 25 10:29:46 AM UTC 24 |
Aug 25 10:29:49 AM UTC 24 |
121311106 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1328689475 |
|
|
Aug 25 10:29:49 AM UTC 24 |
Aug 25 10:29:52 AM UTC 24 |
37354384 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.1167049844 |
|
|
Aug 25 10:29:48 AM UTC 24 |
Aug 25 10:29:53 AM UTC 24 |
89710775 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3852009250 |
|
|
Aug 25 10:29:01 AM UTC 24 |
Aug 25 10:29:53 AM UTC 24 |
1827008861 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.920683297 |
|
|
Aug 25 10:29:40 AM UTC 24 |
Aug 25 10:29:53 AM UTC 24 |
2328255947 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.935555202 |
|
|
Aug 25 10:29:37 AM UTC 24 |
Aug 25 10:29:57 AM UTC 24 |
4125838268 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3004220628 |
|
|
Aug 25 10:29:31 AM UTC 24 |
Aug 25 10:29:58 AM UTC 24 |
902960811 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2204482363 |
|
|
Aug 25 10:29:41 AM UTC 24 |
Aug 25 10:29:59 AM UTC 24 |
777943092 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1281843835 |
|
|
Aug 25 10:29:54 AM UTC 24 |
Aug 25 10:29:59 AM UTC 24 |
64037808 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.2593693020 |
|
|
Aug 25 10:29:41 AM UTC 24 |
Aug 25 10:30:00 AM UTC 24 |
904317831 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.4010801340 |
|
|
Aug 25 10:29:54 AM UTC 24 |
Aug 25 10:30:00 AM UTC 24 |
62129195 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.1743487463 |
|
|
Aug 25 10:29:59 AM UTC 24 |
Aug 25 10:30:02 AM UTC 24 |
37795122 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1064577621 |
|
|
Aug 25 10:29:35 AM UTC 24 |
Aug 25 10:30:04 AM UTC 24 |
742769030 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3505036788 |
|
|
Aug 25 10:29:33 AM UTC 24 |
Aug 25 10:30:07 AM UTC 24 |
1060598255 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1405310934 |
|
|
Aug 25 10:29:54 AM UTC 24 |
Aug 25 10:30:08 AM UTC 24 |
563726079 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.31930687 |
|
|
Aug 25 10:29:17 AM UTC 24 |
Aug 25 10:30:09 AM UTC 24 |
250051867 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.563851860 |
|
|
Aug 25 10:29:59 AM UTC 24 |
Aug 25 10:30:11 AM UTC 24 |
220926464 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.1359309849 |
|
|
Aug 25 10:29:58 AM UTC 24 |
Aug 25 10:30:14 AM UTC 24 |
2048932341 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.13561420 |
|
|
Aug 25 10:30:04 AM UTC 24 |
Aug 25 10:30:15 AM UTC 24 |
235850115 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.2207911176 |
|
|
Aug 25 10:29:54 AM UTC 24 |
Aug 25 10:30:16 AM UTC 24 |
653684920 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.1130253290 |
|
|
Aug 25 10:30:01 AM UTC 24 |
Aug 25 10:30:17 AM UTC 24 |
1966730588 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2692816463 |
|
|
Aug 25 10:30:18 AM UTC 24 |
Aug 25 10:30:21 AM UTC 24 |
19991691 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.836778590 |
|
|
Aug 25 10:30:01 AM UTC 24 |
Aug 25 10:30:21 AM UTC 24 |
426845749 ps |
| T33 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.660514631 |
|
|
Aug 25 10:30:21 AM UTC 24 |
Aug 25 10:30:24 AM UTC 24 |
21248933 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2799527649 |
|
|
Aug 25 10:30:12 AM UTC 24 |
Aug 25 10:30:26 AM UTC 24 |
977588063 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.1632015128 |
|
|
Aug 25 10:30:21 AM UTC 24 |
Aug 25 10:30:26 AM UTC 24 |
35672951 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.266160973 |
|
|
Aug 25 10:30:12 AM UTC 24 |
Aug 25 10:30:31 AM UTC 24 |
1381495338 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.2223015040 |
|
|
Aug 25 10:30:27 AM UTC 24 |
Aug 25 10:30:32 AM UTC 24 |
88350414 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.1234392482 |
|
|
Aug 25 10:29:11 AM UTC 24 |
Aug 25 10:30:32 AM UTC 24 |
11914760841 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.73753720 |
|
|
Aug 25 10:28:55 AM UTC 24 |
Aug 25 10:30:33 AM UTC 24 |
2743459694 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.4157959145 |
|
|
Aug 25 10:30:31 AM UTC 24 |
Aug 25 10:30:33 AM UTC 24 |
34119325 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.2736450956 |
|
|
Aug 25 10:30:10 AM UTC 24 |
Aug 25 10:30:38 AM UTC 24 |
1755580376 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2658556011 |
|
|
Aug 25 10:30:08 AM UTC 24 |
Aug 25 10:30:39 AM UTC 24 |
3852773902 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3608264008 |
|
|
Aug 25 10:29:46 AM UTC 24 |
Aug 25 10:30:40 AM UTC 24 |
117843352 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.4078098988 |
|
|
Aug 25 10:30:30 AM UTC 24 |
Aug 25 10:30:41 AM UTC 24 |
470735448 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.4090515656 |
|
|
Aug 25 10:30:35 AM UTC 24 |
Aug 25 10:30:41 AM UTC 24 |
228598416 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.3687350675 |
|
|
Aug 25 10:30:24 AM UTC 24 |
Aug 25 10:30:42 AM UTC 24 |
60843512 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.3464206073 |
|
|
Aug 25 10:29:12 AM UTC 24 |
Aug 25 10:30:42 AM UTC 24 |
424525259 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.4085238039 |
|
|
Aug 25 10:29:53 AM UTC 24 |
Aug 25 10:30:45 AM UTC 24 |
232455197 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.2013325456 |
|
|
Aug 25 10:30:28 AM UTC 24 |
Aug 25 10:30:45 AM UTC 24 |
1121808874 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.495040663 |
|
|
Aug 25 10:30:09 AM UTC 24 |
Aug 25 10:30:48 AM UTC 24 |
4320394805 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2161573934 |
|
|
Aug 25 10:30:40 AM UTC 24 |
Aug 25 10:30:49 AM UTC 24 |
544660081 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.3887523396 |
|
|
Aug 25 10:30:32 AM UTC 24 |
Aug 25 10:30:50 AM UTC 24 |
2055531248 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.488927496 |
|
|
Aug 25 10:30:03 AM UTC 24 |
Aug 25 10:30:52 AM UTC 24 |
1960845557 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1695804429 |
|
|
Aug 25 10:30:49 AM UTC 24 |
Aug 25 10:30:52 AM UTC 24 |
30169287 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1488058306 |
|
|
Aug 25 10:30:50 AM UTC 24 |
Aug 25 10:30:53 AM UTC 24 |
21899882 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.1419096682 |
|
|
Aug 25 10:30:50 AM UTC 24 |
Aug 25 10:30:54 AM UTC 24 |
27762018 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.2302156290 |
|
|
Aug 25 10:30:28 AM UTC 24 |
Aug 25 10:30:55 AM UTC 24 |
2122517938 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2293737613 |
|
|
Aug 25 10:30:41 AM UTC 24 |
Aug 25 10:30:55 AM UTC 24 |
389274495 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3413521426 |
|
|
Aug 25 10:30:43 AM UTC 24 |
Aug 25 10:30:56 AM UTC 24 |
1152546564 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.1626837388 |
|
|
Aug 25 10:30:57 AM UTC 24 |
Aug 25 10:30:59 AM UTC 24 |
18151595 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.520762936 |
|
|
Aug 25 10:30:54 AM UTC 24 |
Aug 25 10:31:00 AM UTC 24 |
128202111 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.907802000 |
|
|
Aug 25 10:30:41 AM UTC 24 |
Aug 25 10:31:02 AM UTC 24 |
855654495 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3422840934 |
|
|
Aug 25 10:30:41 AM UTC 24 |
Aug 25 10:31:04 AM UTC 24 |
1651684502 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.4099639097 |
|
|
Aug 25 10:30:43 AM UTC 24 |
Aug 25 10:31:05 AM UTC 24 |
1347945332 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.1671260422 |
|
|
Aug 25 10:31:00 AM UTC 24 |
Aug 25 10:31:06 AM UTC 24 |
262060021 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.2255082229 |
|
|
Aug 25 10:30:35 AM UTC 24 |
Aug 25 10:31:07 AM UTC 24 |
724706585 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.119940516 |
|
|
Aug 25 10:30:23 AM UTC 24 |
Aug 25 10:31:07 AM UTC 24 |
498727238 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.462588225 |
|
|
Aug 25 10:30:52 AM UTC 24 |
Aug 25 10:31:08 AM UTC 24 |
147742699 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.3073388457 |
|
|
Aug 25 10:31:06 AM UTC 24 |
Aug 25 10:31:09 AM UTC 24 |
188833242 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.100321316 |
|
|
Aug 25 10:31:02 AM UTC 24 |
Aug 25 10:31:12 AM UTC 24 |
541785893 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.513549342 |
|
|
Aug 25 10:30:56 AM UTC 24 |
Aug 25 10:31:12 AM UTC 24 |
337648791 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2162778177 |
|
|
Aug 25 10:31:07 AM UTC 24 |
Aug 25 10:31:15 AM UTC 24 |
1231733313 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.1768481767 |
|
|
Aug 25 10:30:56 AM UTC 24 |
Aug 25 10:31:16 AM UTC 24 |
941847761 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.853006122 |
|
|
Aug 25 10:30:55 AM UTC 24 |
Aug 25 10:31:18 AM UTC 24 |
1417991057 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.3642085322 |
|
|
Aug 25 10:29:31 AM UTC 24 |
Aug 25 10:31:18 AM UTC 24 |
6833537841 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.508501344 |
|
|
Aug 25 10:30:34 AM UTC 24 |
Aug 25 10:31:19 AM UTC 24 |
2613172451 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3594918377 |
|
|
Aug 25 10:31:16 AM UTC 24 |
Aug 25 10:31:19 AM UTC 24 |
27524690 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1246752889 |
|
|
Aug 25 10:31:17 AM UTC 24 |
Aug 25 10:31:19 AM UTC 24 |
26054670 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.4288562503 |
|
|
Aug 25 10:30:17 AM UTC 24 |
Aug 25 10:31:20 AM UTC 24 |
756651654 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.802691905 |
|
|
Aug 25 10:31:16 AM UTC 24 |
Aug 25 10:31:20 AM UTC 24 |
27992744 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.1106432364 |
|
|
Aug 25 10:31:10 AM UTC 24 |
Aug 25 10:31:21 AM UTC 24 |
262142418 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.437887786 |
|
|
Aug 25 10:31:08 AM UTC 24 |
Aug 25 10:31:23 AM UTC 24 |
1379732868 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.2828519157 |
|
|
Aug 25 10:31:19 AM UTC 24 |
Aug 25 10:31:23 AM UTC 24 |
116075214 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.4217823835 |
|
|
Aug 25 10:31:22 AM UTC 24 |
Aug 25 10:31:24 AM UTC 24 |
37356638 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3933183405 |
|
|
Aug 25 10:28:36 AM UTC 24 |
Aug 25 10:31:25 AM UTC 24 |
29421486082 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1093586232 |
|
|
Aug 25 10:31:01 AM UTC 24 |
Aug 25 10:31:29 AM UTC 24 |
627566733 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3318949931 |
|
|
Aug 25 10:30:39 AM UTC 24 |
Aug 25 10:31:29 AM UTC 24 |
2511270120 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.2451185037 |
|
|
Aug 25 10:31:19 AM UTC 24 |
Aug 25 10:31:33 AM UTC 24 |
44571060 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1054023487 |
|
|
Aug 25 10:31:22 AM UTC 24 |
Aug 25 10:31:34 AM UTC 24 |
437023818 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.462906435 |
|
|
Aug 25 10:31:08 AM UTC 24 |
Aug 25 10:31:36 AM UTC 24 |
2300359040 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.2338045812 |
|
|
Aug 25 10:31:20 AM UTC 24 |
Aug 25 10:31:37 AM UTC 24 |
649586161 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3000762978 |
|
|
Aug 25 10:31:31 AM UTC 24 |
Aug 25 10:31:38 AM UTC 24 |
645356091 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3927896465 |
|
|
Aug 25 10:31:08 AM UTC 24 |
Aug 25 10:31:40 AM UTC 24 |
2901861443 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2585966014 |
|
|
Aug 25 10:31:25 AM UTC 24 |
Aug 25 10:31:42 AM UTC 24 |
2265171843 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1044234053 |
|
|
Aug 25 10:31:21 AM UTC 24 |
Aug 25 10:31:44 AM UTC 24 |
895233150 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.1918193558 |
|
|
Aug 25 10:30:46 AM UTC 24 |
Aug 25 10:31:44 AM UTC 24 |
769588919 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1088407547 |
|
|
Aug 25 10:31:30 AM UTC 24 |
Aug 25 10:31:45 AM UTC 24 |
395105603 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1754867303 |
|
|
Aug 25 10:31:43 AM UTC 24 |
Aug 25 10:31:45 AM UTC 24 |
52490064 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.36791996 |
|
|
Aug 25 10:31:45 AM UTC 24 |
Aug 25 10:31:47 AM UTC 24 |
33181286 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1777068017 |
|
|
Aug 25 10:31:49 AM UTC 24 |
Aug 25 10:32:07 AM UTC 24 |
330111924 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.1253860279 |
|
|
Aug 25 10:31:24 AM UTC 24 |
Aug 25 10:31:48 AM UTC 24 |
3520168218 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.413066301 |
|
|
Aug 25 10:31:22 AM UTC 24 |
Aug 25 10:31:48 AM UTC 24 |
783990267 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1707562002 |
|
|
Aug 25 10:31:46 AM UTC 24 |
Aug 25 10:31:49 AM UTC 24 |
15375069 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.4140062275 |
|
|
Aug 25 10:31:45 AM UTC 24 |
Aug 25 10:31:50 AM UTC 24 |
41238435 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.4266393023 |
|
|
Aug 25 10:31:35 AM UTC 24 |
Aug 25 10:31:50 AM UTC 24 |
605164939 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.2608333321 |
|
|
Aug 25 10:30:52 AM UTC 24 |
Aug 25 10:31:51 AM UTC 24 |
2150102785 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3540836183 |
|
|
Aug 25 10:31:46 AM UTC 24 |
Aug 25 10:31:51 AM UTC 24 |
234348649 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.744765520 |
|
|
Aug 25 10:31:49 AM UTC 24 |
Aug 25 10:31:52 AM UTC 24 |
20407672 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.373481694 |
|
|
Aug 25 10:31:37 AM UTC 24 |
Aug 25 10:31:52 AM UTC 24 |
527832874 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2317579081 |
|
|
Aug 25 10:31:38 AM UTC 24 |
Aug 25 10:31:54 AM UTC 24 |
212823870 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.394386645 |
|
|
Aug 25 10:31:34 AM UTC 24 |
Aug 25 10:31:59 AM UTC 24 |
3209629901 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1190756319 |
|
|
Aug 25 10:31:49 AM UTC 24 |
Aug 25 10:32:02 AM UTC 24 |
806441718 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.3412347857 |
|
|
Aug 25 10:31:53 AM UTC 24 |
Aug 25 10:32:02 AM UTC 24 |
199999399 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.855322004 |
|
|
Aug 25 10:31:19 AM UTC 24 |
Aug 25 10:32:03 AM UTC 24 |
477491874 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.2835374858 |
|
|
Aug 25 10:31:53 AM UTC 24 |
Aug 25 10:32:04 AM UTC 24 |
1803157917 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.442174807 |
|
|
Aug 25 10:31:50 AM UTC 24 |
Aug 25 10:32:05 AM UTC 24 |
2159302442 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.157928588 |
|
|
Aug 25 10:31:48 AM UTC 24 |
Aug 25 10:32:09 AM UTC 24 |
1336694664 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.2131956536 |
|
|
Aug 25 10:32:06 AM UTC 24 |
Aug 25 10:32:09 AM UTC 24 |
84655060 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.1840698671 |
|
|
Aug 25 10:31:51 AM UTC 24 |
Aug 25 10:32:09 AM UTC 24 |
791752793 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.1093635437 |
|
|
Aug 25 10:31:53 AM UTC 24 |
Aug 25 10:32:12 AM UTC 24 |
437513097 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1033298882 |
|
|
Aug 25 10:32:09 AM UTC 24 |
Aug 25 10:32:12 AM UTC 24 |
34461040 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1118995812 |
|
|
Aug 25 10:32:08 AM UTC 24 |
Aug 25 10:32:13 AM UTC 24 |
119546592 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.3486269575 |
|
|
Aug 25 10:31:59 AM UTC 24 |
Aug 25 10:32:15 AM UTC 24 |
1548873801 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1544365384 |
|
|
Aug 25 10:32:02 AM UTC 24 |
Aug 25 10:32:15 AM UTC 24 |
833030832 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.232377018 |
|
|
Aug 25 10:32:10 AM UTC 24 |
Aug 25 10:32:17 AM UTC 24 |
264642050 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.4239771193 |
|
|
Aug 25 10:32:02 AM UTC 24 |
Aug 25 10:32:18 AM UTC 24 |
548073731 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.109469137 |
|
|
Aug 25 10:32:16 AM UTC 24 |
Aug 25 10:32:18 AM UTC 24 |
14138355 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.431936587 |
|
|
Aug 25 10:32:17 AM UTC 24 |
Aug 25 10:32:24 AM UTC 24 |
611742407 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1846799374 |
|
|
Aug 25 10:30:01 AM UTC 24 |
Aug 25 10:32:24 AM UTC 24 |
7282877417 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.902726669 |
|
|
Aug 25 10:32:12 AM UTC 24 |
Aug 25 10:32:26 AM UTC 24 |
287368237 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.1809532472 |
|
|
Aug 25 10:32:12 AM UTC 24 |
Aug 25 10:32:26 AM UTC 24 |
926478084 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.2874245985 |
|
|
Aug 25 10:31:46 AM UTC 24 |
Aug 25 10:32:27 AM UTC 24 |
296388773 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.9652013 |
|
|
Aug 25 10:31:55 AM UTC 24 |
Aug 25 10:32:27 AM UTC 24 |
1102172693 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3883370144 |
|
|
Aug 25 10:32:10 AM UTC 24 |
Aug 25 10:32:28 AM UTC 24 |
419176543 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.434366388 |
|
|
Aug 25 10:31:53 AM UTC 24 |
Aug 25 10:32:30 AM UTC 24 |
1235125448 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2416457972 |
|
|
Aug 25 10:32:15 AM UTC 24 |
Aug 25 10:32:30 AM UTC 24 |
629551990 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.304147940 |
|
|
Aug 25 10:32:31 AM UTC 24 |
Aug 25 10:32:34 AM UTC 24 |
90422722 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.4162411164 |
|
|
Aug 25 10:32:24 AM UTC 24 |
Aug 25 10:32:35 AM UTC 24 |
1085021852 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1151485756 |
|
|
Aug 25 10:32:19 AM UTC 24 |
Aug 25 10:32:36 AM UTC 24 |
934441091 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.379393316 |
|
|
Aug 25 10:32:26 AM UTC 24 |
Aug 25 10:32:38 AM UTC 24 |
819537903 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2265922193 |
|
|
Aug 25 10:32:36 AM UTC 24 |
Aug 25 10:32:38 AM UTC 24 |
16856734 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3520055017 |
|
|
Aug 25 10:32:19 AM UTC 24 |
Aug 25 10:32:41 AM UTC 24 |
582185210 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1991206871 |
|
|
Aug 25 10:32:35 AM UTC 24 |
Aug 25 10:32:42 AM UTC 24 |
84114158 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3728494780 |
|
|
Aug 25 10:32:28 AM UTC 24 |
Aug 25 10:32:43 AM UTC 24 |
320752133 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.334777700 |
|
|
Aug 25 10:33:14 AM UTC 24 |
Aug 25 10:33:44 AM UTC 24 |
2640982681 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.4190194567 |
|
|
Aug 25 10:32:39 AM UTC 24 |
Aug 25 10:32:45 AM UTC 24 |
849810785 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3637158114 |
|
|
Aug 25 10:32:44 AM UTC 24 |
Aug 25 10:32:47 AM UTC 24 |
110533414 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2177876660 |
|
|
Aug 25 10:33:38 AM UTC 24 |
Aug 25 10:33:40 AM UTC 24 |
23602407 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3626817584 |
|
|
Aug 25 10:33:16 AM UTC 24 |
Aug 25 10:33:41 AM UTC 24 |
391496078 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.2931927421 |
|
|
Aug 25 10:31:05 AM UTC 24 |
Aug 25 10:32:48 AM UTC 24 |
5120885812 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.2373692507 |
|
|
Aug 25 10:32:28 AM UTC 24 |
Aug 25 10:32:48 AM UTC 24 |
1932756189 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.1034927189 |
|
|
Aug 25 10:31:26 AM UTC 24 |
Aug 25 10:32:49 AM UTC 24 |
1940370220 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3620566083 |
|
|
Aug 25 10:32:28 AM UTC 24 |
Aug 25 10:32:50 AM UTC 24 |
1171919470 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1765855647 |
|
|
Aug 25 10:32:09 AM UTC 24 |
Aug 25 10:32:51 AM UTC 24 |
214763556 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2859470054 |
|
|
Aug 25 10:32:39 AM UTC 24 |
Aug 25 10:32:54 AM UTC 24 |
103314678 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1817873334 |
|
|
Aug 25 10:32:43 AM UTC 24 |
Aug 25 10:32:54 AM UTC 24 |
625773238 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2970276447 |
|
|
Aug 25 10:31:00 AM UTC 24 |
Aug 25 10:32:58 AM UTC 24 |
7068925177 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1816762585 |
|
|
Aug 25 10:32:40 AM UTC 24 |
Aug 25 10:32:58 AM UTC 24 |
996313312 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.3431856569 |
|
|
Aug 25 10:32:42 AM UTC 24 |
Aug 25 10:33:00 AM UTC 24 |
437366886 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.275405087 |
|
|
Aug 25 10:32:46 AM UTC 24 |
Aug 25 10:33:01 AM UTC 24 |
1209809869 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.885782658 |
|
|
Aug 25 10:29:44 AM UTC 24 |
Aug 25 10:33:02 AM UTC 24 |
51178498994 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1336873503 |
|
|
Aug 25 10:32:50 AM UTC 24 |
Aug 25 10:33:03 AM UTC 24 |
1034465618 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.153250904 |
|
|
Aug 25 10:33:01 AM UTC 24 |
Aug 25 10:33:04 AM UTC 24 |
247004586 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3209979892 |
|
|
Aug 25 10:32:50 AM UTC 24 |
Aug 25 10:33:05 AM UTC 24 |
602976711 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.806534508 |
|
|
Aug 25 10:32:05 AM UTC 24 |
Aug 25 10:33:05 AM UTC 24 |
1825806217 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3481774043 |
|
|
Aug 25 10:33:04 AM UTC 24 |
Aug 25 10:33:06 AM UTC 24 |
45466549 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.1512017968 |
|
|
Aug 25 10:33:14 AM UTC 24 |
Aug 25 10:33:37 AM UTC 24 |
6222702060 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1841939157 |
|
|
Aug 25 10:33:38 AM UTC 24 |
Aug 25 10:33:41 AM UTC 24 |
51033684 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.3225979100 |
|
|
Aug 25 10:33:23 AM UTC 24 |
Aug 25 10:33:50 AM UTC 24 |
2562298060 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.37658375 |
|
|
Aug 25 10:33:03 AM UTC 24 |
Aug 25 10:33:09 AM UTC 24 |
87592757 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1218532623 |
|
|
Aug 25 10:32:55 AM UTC 24 |
Aug 25 10:33:09 AM UTC 24 |
1753285649 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1785972691 |
|
|
Aug 25 10:33:05 AM UTC 24 |
Aug 25 10:33:11 AM UTC 24 |
322031351 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1701347599 |
|
|
Aug 25 10:32:27 AM UTC 24 |
Aug 25 10:33:12 AM UTC 24 |
1097805210 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2988125716 |
|
|
Aug 25 10:32:49 AM UTC 24 |
Aug 25 10:33:13 AM UTC 24 |
1199603651 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1431866926 |
|
|
Aug 25 10:32:59 AM UTC 24 |
Aug 25 10:33:13 AM UTC 24 |
223629628 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.2250064299 |
|
|
Aug 25 10:32:55 AM UTC 24 |
Aug 25 10:33:15 AM UTC 24 |
381057110 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3738753849 |
|
|
Aug 25 10:33:09 AM UTC 24 |
Aug 25 10:33:17 AM UTC 24 |
610302567 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.497229360 |
|
|
Aug 25 10:33:05 AM UTC 24 |
Aug 25 10:33:17 AM UTC 24 |
173311071 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1854032587 |
|
|
Aug 25 10:32:48 AM UTC 24 |
Aug 25 10:33:19 AM UTC 24 |
1440331368 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1571269340 |
|
|
Aug 25 10:32:52 AM UTC 24 |
Aug 25 10:33:20 AM UTC 24 |
1973085294 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2657146115 |
|
|
Aug 25 10:33:10 AM UTC 24 |
Aug 25 10:33:21 AM UTC 24 |
1036429652 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.1416836975 |
|
|
Aug 25 10:33:19 AM UTC 24 |
Aug 25 10:33:21 AM UTC 24 |
70977621 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1867271639 |
|
|
Aug 25 10:33:14 AM UTC 24 |
Aug 25 10:33:21 AM UTC 24 |
1100216192 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.1616575961 |
|
|
Aug 25 10:32:20 AM UTC 24 |
Aug 25 10:33:22 AM UTC 24 |
37268345963 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.2095250442 |
|
|
Aug 25 10:33:07 AM UTC 24 |
Aug 25 10:33:22 AM UTC 24 |
312949324 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.346876702 |
|
|
Aug 25 10:33:20 AM UTC 24 |
Aug 25 10:33:23 AM UTC 24 |
72409733 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1934357518 |
|
|
Aug 25 10:33:20 AM UTC 24 |
Aug 25 10:33:24 AM UTC 24 |
248633876 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.568509737 |
|
|
Aug 25 10:33:23 AM UTC 24 |
Aug 25 10:33:27 AM UTC 24 |
39442826 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.4181915684 |
|
|
Aug 25 10:33:06 AM UTC 24 |
Aug 25 10:33:29 AM UTC 24 |
1258847986 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.598187608 |
|
|
Aug 25 10:33:23 AM UTC 24 |
Aug 25 10:33:29 AM UTC 24 |
93516177 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.628440584 |
|
|
Aug 25 10:32:37 AM UTC 24 |
Aug 25 10:33:30 AM UTC 24 |
1473406496 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.4204916293 |
|
|
Aug 25 10:32:04 AM UTC 24 |
Aug 25 10:33:30 AM UTC 24 |
1870291448 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1305781153 |
|
|
Aug 25 10:33:10 AM UTC 24 |
Aug 25 10:33:32 AM UTC 24 |
920740568 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1236701574 |
|
|
Aug 25 10:33:24 AM UTC 24 |
Aug 25 10:33:32 AM UTC 24 |
1032000345 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.1963825456 |
|
|
Aug 25 10:33:27 AM UTC 24 |
Aug 25 10:33:36 AM UTC 24 |
268691778 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2119836956 |
|
|
Aug 25 10:33:23 AM UTC 24 |
Aug 25 10:33:38 AM UTC 24 |
1297997886 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.677377253 |
|
|
Aug 25 10:33:39 AM UTC 24 |
Aug 25 10:33:41 AM UTC 24 |
36603994 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.3768145972 |
|
|
Aug 25 10:33:41 AM UTC 24 |
Aug 25 10:33:46 AM UTC 24 |
69184224 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.3965206243 |
|
|
Aug 25 10:33:24 AM UTC 24 |
Aug 25 10:33:46 AM UTC 24 |
2039525847 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1726409682 |
|
|
Aug 25 10:33:31 AM UTC 24 |
Aug 25 10:33:47 AM UTC 24 |
817081469 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1491390429 |
|
|
Aug 25 10:33:41 AM UTC 24 |
Aug 25 10:33:47 AM UTC 24 |
138051411 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1660267346 |
|
|
Aug 25 10:31:23 AM UTC 24 |
Aug 25 10:33:47 AM UTC 24 |
2690007948 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.2315777688 |
|
|
Aug 25 10:33:04 AM UTC 24 |
Aug 25 10:33:50 AM UTC 24 |
464810987 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.3778254183 |
|
|
Aug 25 10:33:31 AM UTC 24 |
Aug 25 10:33:53 AM UTC 24 |
681730144 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.2320783261 |
|
|
Aug 25 10:33:32 AM UTC 24 |
Aug 25 10:33:53 AM UTC 24 |
280426004 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.2689163448 |
|
|
Aug 25 10:32:18 AM UTC 24 |
Aug 25 10:33:54 AM UTC 24 |
1255186809 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.556443659 |
|
|
Aug 25 10:33:45 AM UTC 24 |
Aug 25 10:33:54 AM UTC 24 |
311314591 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2346659645 |
|
|
Aug 25 10:30:43 AM UTC 24 |
Aug 25 10:33:57 AM UTC 24 |
8306667886 ps |