Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57488697

1

T1

1326

T2

2747

T3

929

auto[1]

1127904

1

T4

891

T16

693

T18

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57476376

1

T1

1326

T2

2747

T3

929

auto[1]

1140225

1

T4

396

T16

594

T18

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5317327	1			T1	99		T2	475		T3	113
auto[IdleSt]	15654368	1			T1	150		T2	656		T3	816
auto[ClkMuxSt]	28250	1			T2	5		T4	13		T5	10
auto[CntIncrSt]	28072	1			T2	5		T4	13		T5	10
auto[CntProgSt]	1113647	1			T2	10		T4	292		T5	175
auto[TransCheckSt]	22466	1			T2	5		T5	10		T7	10
auto[TokenHashSt]	16040367	1			T2	259		T5	108		T7	2946
auto[FlashRmaSt]	28283	1			T2	5		T5	53		T7	34
auto[TokenCheck0St]	10012	1			T2	5		T5	10		T7	10
auto[TokenCheck1St]	7166	1			T2	5		T5	10		T7	10
auto[TransProgSt]	280089	1			T2	10		T5	135		T7	309
auto[PostTransSt]	8386798	1			T1	1077		T2	1307		T4	802
auto[ScrapSt]	75242	1			T5	24		T7	1052		T12	376
auto[EscalateSt]	4637464	1			T4	1625		T16	1737		T18	1347
auto[InvalidSt]	6985700	1			T18	786		T32	547		T43	2162

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1350	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6985700	1			T18	786		T32	547		T43	2162
EscalateSt	4637464	1			T4	1625		T16	1737		T18	1347
ScrapSt	75242	1			T5	24		T7	1052		T12	376
PostTransSt	8386798	1			T1	1077		T2	1307		T4	802
TransProgSt	280089	1			T2	10		T5	135		T7	309
TokenCheck1St	7166	1			T2	5		T5	10		T7	10
TokenCheck0St	10012	1			T2	5		T5	10		T7	10
FlashRmaSt	28283	1			T2	5		T5	53		T7	34
TokenHashSt	16040367	1			T2	259		T5	108		T7	2946
TransCheckSt	22466	1			T2	5		T5	10		T7	10
CntProgSt	1113647	1			T2	10		T4	292		T5	175
CntIncrSt	28072	1			T2	5		T4	13		T5	10
ClkMuxSt	28250	1			T2	5		T4	13		T5	10
IdleSt	15654368	1			T1	150		T2	656		T3	816
ResetSt	5317327	1			T1	99		T2	475		T3	113
arcs[ResetSt=>IdleSt]	41680	1			T1	1		T2	5		T3	1
arcs[IdleSt=>ScrapSt]	213	1			T5	1		T7	2		T12	1
arcs[IdleSt=>ClkMuxSt]	28111	1			T2	5		T4	13		T5	10
arcs[ClkMuxSt=>CntIncrSt]	28072	1			T2	5		T4	13		T5	10
arcs[CntIncrSt=>PostTransSt]	1139	1			T31	5		T37	12		T46	8
arcs[CntIncrSt=>CntProgSt]	26868	1			T2	5		T4	13		T5	10
arcs[CntProgSt=>PostTransSt]	3489	1			T4	13		T16	13		T11	4
arcs[CntProgSt=>TransCheckSt]	22466	1			T2	5		T5	10		T7	10
arcs[TransCheckSt=>PostTransSt]	3126	1			T17	27		T31	9		T37	13
arcs[TransCheckSt=>TokenHashSt]	19225	1			T2	5		T5	10		T7	10
arcs[TokenHashSt=>PostTransSt]	8346	1			T17	10		T31	20		T37	28
arcs[TokenHashSt=>FlashRmaSt]	10050	1			T2	5		T5	10		T7	10
arcs[FlashRmaSt=>TokenCheck0St]	10012	1			T2	5		T5	10		T7	10
arcs[TokenCheck0St=>PostTransSt]	2777	1			T17	12		T31	6		T37	9
arcs[TokenCheck0St=>TokenCheck1St]	7166	1			T2	5		T5	10		T7	10
arcs[TokenCheck1St=>PostTransSt]	602	1			T17	6		T44	7		T46	1
arcs[TransProgSt=>PostTransSt]	5821	1			T2	5		T5	10		T7	10
arcs[IdleSt=>EscalateSt]	174	1			T20	4		T60	6		T34	5
arcs[ClkMuxSt=>EscalateSt]	39	1			T20	1		T60	1		T34	1
arcs[CntIncrSt=>EscalateSt]	65	1			T20	1		T34	1		T61	1
arcs[CntProgSt=>EscalateSt]	913	1			T20	30		T60	6		T34	30
arcs[TransCheckSt=>EscalateSt]	115	1			T20	3		T60	8		T34	1
arcs[TokenHashSt=>EscalateSt]	829	1			T20	14		T60	26		T34	13
arcs[FlashRmaSt=>EscalateSt]	38	1			T34	1		T61	1		T62	2
arcs[TokenCheck0St=>EscalateSt]	69	1			T20	1		T60	4		T34	2
arcs[TokenCheck1St=>EscalateSt]	26	1			T20	1		T60	1		T61	2
arcs[TransProgSt=>EscalateSt]	717	1			T20	16		T60	10		T34	20
arcs[PostTransSt=>EscalateSt]	3905	1			T4	13		T16	13		T11	4
arcs[InvalidSt=>EscalateSt]	9905	1			T18	5		T32	3		T43	11

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5317154	1			T1	99		T2	475		T3	113
auto[0]	auto[IdleSt]	15654244	1			T1	150		T2	656		T3	816
auto[0]	auto[ClkMuxSt]	28224	1			T2	5		T4	13		T5	10
auto[0]	auto[CntIncrSt]	28027	1			T2	5		T4	13		T5	10
auto[0]	auto[CntProgSt]	1113052	1			T2	10		T4	292		T5	175
auto[0]	auto[TransCheckSt]	22389	1			T2	5		T5	10		T7	10
auto[0]	auto[TokenHashSt]	16039820	1			T2	259		T5	108		T7	2946
auto[0]	auto[FlashRmaSt]	28255	1			T2	5		T5	53		T7	34
auto[0]	auto[TokenCheck0St]	9967	1			T2	5		T5	10		T7	10
auto[0]	auto[TokenCheck1St]	7148	1			T2	5		T5	10		T7	10
auto[0]	auto[TransProgSt]	279623	1			T2	10		T5	135		T7	309
auto[0]	auto[PostTransSt]	8384819	1			T1	1077		T2	1307		T4	793
auto[0]	auto[ScrapSt]	75198	1			T5	24		T7	1052		T12	376
auto[0]	auto[EscalateSt]	3518694	1			T4	743		T16	1051		T18	1053
auto[0]	auto[InvalidSt]	6980733	1			T18	783		T32	545		T43	2152
auto[1]	auto[ResetSt]	173	1			T20	4		T60	4		T34	5
auto[1]	auto[IdleSt]	124	1			T20	1		T60	3		T34	2
auto[1]	auto[ClkMuxSt]	26	1			T20	1		T60	1		T228	1
auto[1]	auto[CntIncrSt]	45	1			T20	1		T34	1		T61	1
auto[1]	auto[CntProgSt]	595	1			T20	16		T60	5		T34	19
auto[1]	auto[TransCheckSt]	77	1			T20	3		T60	4		T34	1
auto[1]	auto[TokenHashSt]	547	1			T20	10		T60	15		T34	10
auto[1]	auto[FlashRmaSt]	28	1			T34	1		T61	1		T62	2
auto[1]	auto[TokenCheck0St]	45	1			T60	4		T63	1		T228	2
auto[1]	auto[TokenCheck1St]	18	1			T60	1		T61	1		T63	2
auto[1]	auto[TransProgSt]	466	1			T20	11		T60	5		T34	9
auto[1]	auto[PostTransSt]	1979	1			T4	9		T16	7		T20	4
auto[1]	auto[ScrapSt]	44	1			T34	2		T63	1		T229	3
auto[1]	auto[EscalateSt]	1118770	1			T4	882		T16	686		T18	294
auto[1]	auto[InvalidSt]	4967	1			T18	3		T32	2		T43	10

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5317150	1			T1	99		T2	475		T3	113
auto[0]	auto[IdleSt]	15654257	1			T1	150		T2	656		T3	816
auto[0]	auto[ClkMuxSt]	28222	1			T2	5		T4	13		T5	10
auto[0]	auto[CntIncrSt]	28030	1			T2	5		T4	13		T5	10
auto[0]	auto[CntProgSt]	1113033	1			T2	10		T4	292		T5	175
auto[0]	auto[TransCheckSt]	22388	1			T2	5		T5	10		T7	10
auto[0]	auto[TokenHashSt]	16039816	1			T2	259		T5	108		T7	2946
auto[0]	auto[FlashRmaSt]	28257	1			T2	5		T5	53		T7	34
auto[0]	auto[TokenCheck0St]	9963	1			T2	5		T5	10		T7	10
auto[0]	auto[TokenCheck1St]	7147	1			T2	5		T5	10		T7	10
auto[0]	auto[TransProgSt]	279598	1			T2	10		T5	135		T7	309
auto[0]	auto[PostTransSt]	8384740	1			T1	1077		T2	1307		T4	798
auto[0]	auto[ScrapSt]	75201	1			T5	24		T7	1052		T12	376
auto[0]	auto[EscalateSt]	3506462	1			T4	1233		T16	1149		T18	1151
auto[0]	auto[InvalidSt]	6980762	1			T18	784		T32	546		T43	2161
auto[1]	auto[ResetSt]	177	1			T20	4		T60	6		T34	3
auto[1]	auto[IdleSt]	111	1			T20	4		T60	5		T34	5
auto[1]	auto[ClkMuxSt]	28	1			T20	1		T60	1		T34	1
auto[1]	auto[CntIncrSt]	42	1			T20	1		T34	1		T61	1
auto[1]	auto[CntProgSt]	614	1			T20	23		T60	3		T34	20
auto[1]	auto[TransCheckSt]	78	1			T20	1		T60	6		T34	1
auto[1]	auto[TokenHashSt]	551	1			T20	9		T60	16		T34	6
auto[1]	auto[FlashRmaSt]	26	1			T62	2		T230	1		T162	1
auto[1]	auto[TokenCheck0St]	49	1			T20	1		T34	2		T63	1
auto[1]	auto[TokenCheck1St]	19	1			T20	1		T60	1		T61	2
auto[1]	auto[TransProgSt]	491	1			T20	7		T60	7		T34	17
auto[1]	auto[PostTransSt]	2058	1			T4	4		T16	6		T11	4
auto[1]	auto[ScrapSt]	41	1			T60	1		T229	3		T231	1
auto[1]	auto[EscalateSt]	1131002	1			T4	392		T16	588		T18	196
auto[1]	auto[InvalidSt]	4938	1			T18	2		T32	1		T43	1