Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.56 97.99 95.59 93.40 95.35 98.55 98.76 96.29


Total tests in report: 1006
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
58.99 58.99 80.53 80.53 44.64 44.64 49.08 49.08 37.21 37.21 71.99 71.99 92.54 92.54 36.93 36.93 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.3922221020
70.24 11.25 81.94 1.41 51.67 7.02 60.82 11.74 65.12 27.91 82.99 11.00 92.79 0.25 56.36 19.43 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1915273897
80.08 9.84 88.63 6.69 78.76 27.09 75.59 14.77 69.77 4.65 88.59 5.60 94.53 1.74 64.66 8.30 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.917431563
83.72 3.64 95.32 6.69 79.66 0.90 76.87 1.29 76.74 6.98 91.70 3.11 94.53 0.00 71.20 6.54 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2184887846
86.02 2.31 95.62 0.30 80.74 1.08 82.70 5.83 81.40 4.65 93.15 1.45 94.53 0.00 74.03 2.83 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1758204512
87.53 1.50 95.67 0.05 82.27 1.53 85.11 2.41 81.40 0.00 93.15 0.00 95.77 1.24 79.33 5.30 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.410934979
88.82 1.29 96.33 0.65 85.69 3.42 85.23 0.12 81.40 0.00 93.98 0.83 96.27 0.50 82.86 3.53 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.2570134222
89.74 0.91 96.83 0.50 87.31 1.62 85.96 0.73 83.72 2.33 95.02 1.04 96.27 0.00 83.04 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.159804982
90.58 0.84 96.93 0.10 88.12 0.81 86.51 0.55 86.05 2.33 95.64 0.62 96.52 0.25 84.28 1.24 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1669468290
91.42 0.84 96.93 0.00 88.12 0.00 86.51 0.00 90.70 4.65 95.64 0.00 96.52 0.00 85.51 1.24 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3092010960
92.17 0.75 97.03 0.10 88.21 0.09 87.10 0.59 93.02 2.33 96.06 0.41 96.52 0.00 87.28 1.77 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1867962398
92.85 0.67 97.03 0.00 88.21 0.00 89.16 2.06 93.02 0.00 96.06 0.00 96.52 0.00 89.93 2.65 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1552108074
93.38 0.54 97.18 0.15 89.74 1.53 89.16 0.00 93.02 0.00 96.47 0.41 96.77 0.25 91.34 1.41 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1559936031
93.77 0.39 97.23 0.05 90.73 0.99 89.16 0.00 93.02 0.00 97.10 0.62 96.77 0.00 92.40 1.06 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1843173373
94.11 0.33 97.23 0.00 90.73 0.00 89.16 0.00 95.35 2.33 97.10 0.00 96.77 0.00 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2178991364
94.36 0.26 97.23 0.00 90.73 0.00 90.96 1.80 95.35 0.00 97.10 0.00 96.77 0.00 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3754193884
94.58 0.21 97.23 0.00 90.73 0.00 90.96 0.00 95.35 0.00 97.10 0.00 98.26 1.49 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3692719352
94.79 0.21 97.59 0.35 91.63 0.90 91.19 0.22 95.35 0.00 97.10 0.00 98.26 0.00 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2223000670
94.98 0.20 97.69 0.10 91.90 0.27 91.99 0.81 95.35 0.00 97.30 0.21 98.26 0.00 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3290262698
95.15 0.17 97.79 0.10 91.90 0.00 92.34 0.34 95.35 0.00 97.51 0.21 98.26 0.00 92.93 0.53 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2597733277
95.32 0.17 97.79 0.00 92.71 0.81 92.34 0.00 95.35 0.00 97.51 0.00 98.26 0.00 93.29 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2003352598
95.45 0.13 97.79 0.00 93.07 0.36 92.34 0.00 95.35 0.00 97.51 0.00 98.26 0.00 93.82 0.53 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2571336621
95.57 0.13 97.84 0.05 93.34 0.27 92.34 0.00 95.35 0.00 97.72 0.21 98.26 0.00 94.17 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.2873613325
95.69 0.11 97.84 0.00 93.34 0.00 92.78 0.45 95.35 0.00 97.72 0.00 98.26 0.00 94.52 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.175108953
95.78 0.10 97.89 0.05 93.34 0.00 92.78 0.00 95.35 0.00 97.93 0.21 98.51 0.25 94.70 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2519520203
95.88 0.09 97.89 0.00 93.34 0.00 93.07 0.28 95.35 0.00 97.93 0.00 98.51 0.00 95.05 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1223400126
95.96 0.09 97.99 0.10 93.43 0.09 93.07 0.00 95.35 0.00 98.34 0.41 98.51 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.208450486
96.02 0.05 97.99 0.00 93.43 0.00 93.09 0.02 95.35 0.00 98.34 0.00 98.51 0.00 95.41 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.572078753
96.07 0.05 97.99 0.00 93.79 0.36 93.09 0.00 95.35 0.00 98.34 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3418137070
96.12 0.05 97.99 0.00 94.15 0.36 93.09 0.00 95.35 0.00 98.34 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2604394292
96.16 0.04 97.99 0.00 94.42 0.27 93.09 0.00 95.35 0.00 98.34 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3846908217
96.20 0.04 97.99 0.00 94.69 0.27 93.09 0.00 95.35 0.00 98.34 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2449059832
96.23 0.04 97.99 0.00 94.69 0.00 93.09 0.00 95.35 0.00 98.34 0.00 98.76 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1946866630
96.27 0.04 97.99 0.00 94.69 0.00 93.16 0.07 95.35 0.00 98.34 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.515820106
96.30 0.03 97.99 0.00 94.69 0.00 93.20 0.04 95.35 0.00 98.34 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2495416769
96.33 0.03 97.99 0.00 94.69 0.00 93.20 0.00 95.35 0.00 98.55 0.21 98.76 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.204182798
96.35 0.03 97.99 0.00 94.87 0.18 93.20 0.00 95.35 0.00 98.55 0.00 98.76 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.63339340
96.38 0.03 97.99 0.00 95.05 0.18 93.20 0.00 95.35 0.00 98.55 0.00 98.76 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4001323513
96.40 0.03 97.99 0.00 95.05 0.00 93.20 0.00 95.35 0.00 98.55 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.739555341
96.43 0.03 97.99 0.00 95.05 0.00 93.20 0.00 95.35 0.00 98.55 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.3792249341
96.45 0.03 97.99 0.00 95.05 0.00 93.20 0.00 95.35 0.00 98.55 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.43822216
96.47 0.02 97.99 0.00 95.05 0.00 93.34 0.14 95.35 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3713648788
96.49 0.01 97.99 0.00 95.14 0.09 93.34 0.00 95.35 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1486847233
96.50 0.01 97.99 0.00 95.23 0.09 93.34 0.00 95.35 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2957656438
96.51 0.01 97.99 0.00 95.32 0.09 93.34 0.00 95.35 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.355457924
96.53 0.01 97.99 0.00 95.41 0.09 93.34 0.00 95.35 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1780779732
96.54 0.01 97.99 0.00 95.50 0.09 93.34 0.00 95.35 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2275131054
96.55 0.01 97.99 0.00 95.59 0.09 93.34 0.00 95.35 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3236282576
96.56 0.01 97.99 0.00 95.59 0.00 93.40 0.06 95.35 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.583956951

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3339478654
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1487577994
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1205842442
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3327113561
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3845247023
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1480881639
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.80927603
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2442979750
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2703942790
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3840759663
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3396076383
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4007512221
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2883582799
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.728984948
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.635944386
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1229609315
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1895425223
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2966914732
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1459939384
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3737577727
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2097241793
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3805907184
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1575519074
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2083840093
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3292251096
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2576198234
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1129758274
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1318020933
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3872252898
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1071270391
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3571444062
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2305769747
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3033093843
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2073793190
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2676000418
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3131065612
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3622676143
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1086748052
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1117168872
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/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3420270604
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/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3208198240



Total test records in report: 1006
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.901149823 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:17 PM UTC 24 13417610 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.229231164 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:19 PM UTC 24 28046976 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.739555341 Aug 27 08:00:16 PM UTC 24 Aug 27 08:00:19 PM UTC 24 33225821 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3683869955 Aug 27 08:00:16 PM UTC 24 Aug 27 08:00:20 PM UTC 24 55538511 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2223000670 Aug 27 08:00:19 PM UTC 24 Aug 27 08:00:21 PM UTC 24 21387094 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.159804982 Aug 27 08:00:19 PM UTC 24 Aug 27 08:00:22 PM UTC 24 21147169 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.2367587261 Aug 27 08:00:18 PM UTC 24 Aug 27 08:00:22 PM UTC 24 146865987 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.3922221020 Aug 27 08:00:19 PM UTC 24 Aug 27 08:00:22 PM UTC 24 146993198 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.4033204837 Aug 27 08:00:16 PM UTC 24 Aug 27 08:00:23 PM UTC 24 1392783621 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2495416769 Aug 27 08:00:20 PM UTC 24 Aug 27 08:00:23 PM UTC 24 14625358 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.515820106 Aug 27 08:00:19 PM UTC 24 Aug 27 08:00:24 PM UTC 24 247314840 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.2570134222 Aug 27 08:00:18 PM UTC 24 Aug 27 08:00:24 PM UTC 24 323934559 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1867962398 Aug 27 08:00:18 PM UTC 24 Aug 27 08:00:25 PM UTC 24 185987677 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.4011380106 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:26 PM UTC 24 826371454 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2597733277 Aug 27 08:00:18 PM UTC 24 Aug 27 08:00:27 PM UTC 24 428516557 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.1746473204 Aug 27 08:00:23 PM UTC 24 Aug 27 08:00:28 PM UTC 24 325668579 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.206177308 Aug 27 08:00:24 PM UTC 24 Aug 27 08:00:29 PM UTC 24 212044548 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1929041394 Aug 27 08:00:20 PM UTC 24 Aug 27 08:00:29 PM UTC 24 223459710 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1915273897 Aug 27 08:00:16 PM UTC 24 Aug 27 08:00:29 PM UTC 24 1397967439 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.583956951 Aug 27 08:00:19 PM UTC 24 Aug 27 08:00:30 PM UTC 24 172381390 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.2133948299 Aug 27 08:00:19 PM UTC 24 Aug 27 08:00:30 PM UTC 24 918586243 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.56279599 Aug 27 08:00:19 PM UTC 24 Aug 27 08:00:30 PM UTC 24 1560860438 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.4230994219 Aug 27 08:00:28 PM UTC 24 Aug 27 08:00:30 PM UTC 24 19917848 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1117840460 Aug 27 08:00:16 PM UTC 24 Aug 27 08:00:31 PM UTC 24 626065022 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1833270030 Aug 27 08:00:29 PM UTC 24 Aug 27 08:00:31 PM UTC 24 37251035 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1265820874 Aug 27 08:00:29 PM UTC 24 Aug 27 08:00:31 PM UTC 24 16367587 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2233545347 Aug 27 08:00:18 PM UTC 24 Aug 27 08:00:31 PM UTC 24 1523765528 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2184887846 Aug 27 08:00:18 PM UTC 24 Aug 27 08:00:32 PM UTC 24 2561170681 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1163359543 Aug 27 08:00:16 PM UTC 24 Aug 27 08:00:32 PM UTC 24 304864375 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.2960753638 Aug 27 08:00:22 PM UTC 24 Aug 27 08:00:33 PM UTC 24 1130864185 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1003453871 Aug 27 08:00:30 PM UTC 24 Aug 27 08:00:33 PM UTC 24 10954877 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3342243563 Aug 27 08:00:18 PM UTC 24 Aug 27 08:00:33 PM UTC 24 3950400085 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.330685558 Aug 27 08:00:29 PM UTC 24 Aug 27 08:00:33 PM UTC 24 43269726 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2600061120 Aug 27 08:00:24 PM UTC 24 Aug 27 08:00:34 PM UTC 24 378665335 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2790830416 Aug 27 08:00:19 PM UTC 24 Aug 27 08:00:35 PM UTC 24 638321380 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1781621604 Aug 27 08:00:30 PM UTC 24 Aug 27 08:00:36 PM UTC 24 175851532 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.917431563 Aug 27 08:00:21 PM UTC 24 Aug 27 08:00:36 PM UTC 24 2522317178 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.1924856073 Aug 27 08:00:30 PM UTC 24 Aug 27 08:00:37 PM UTC 24 178667250 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.815438027 Aug 27 08:00:33 PM UTC 24 Aug 27 08:00:39 PM UTC 24 627824581 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1528175738 Aug 27 08:00:36 PM UTC 24 Aug 27 08:00:39 PM UTC 24 12512937 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.70981331 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:39 PM UTC 24 174022427 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.2181872964 Aug 27 08:00:24 PM UTC 24 Aug 27 08:00:39 PM UTC 24 1652120358 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.103813316 Aug 27 08:00:36 PM UTC 24 Aug 27 08:00:39 PM UTC 24 72981891 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1826144183 Aug 27 08:00:37 PM UTC 24 Aug 27 08:00:40 PM UTC 24 13802548 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1786815338 Aug 27 08:00:30 PM UTC 24 Aug 27 08:00:40 PM UTC 24 1434581773 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.4107030757 Aug 27 08:00:30 PM UTC 24 Aug 27 08:00:40 PM UTC 24 3442854210 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.116872219 Aug 27 08:00:16 PM UTC 24 Aug 27 08:00:41 PM UTC 24 2835936710 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.3590355756 Aug 27 08:00:18 PM UTC 24 Aug 27 08:00:41 PM UTC 24 1850582311 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.3570833876 Aug 27 08:00:35 PM UTC 24 Aug 27 08:00:42 PM UTC 24 170883834 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.406301390 Aug 27 08:00:33 PM UTC 24 Aug 27 08:00:43 PM UTC 24 645389390 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.208450486 Aug 27 08:00:30 PM UTC 24 Aug 27 08:00:43 PM UTC 24 292405188 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.4286314875 Aug 27 08:00:41 PM UTC 24 Aug 27 08:00:43 PM UTC 24 42746245 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.3690889349 Aug 27 08:00:40 PM UTC 24 Aug 27 08:00:44 PM UTC 24 242349863 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.763346652 Aug 27 08:00:35 PM UTC 24 Aug 27 08:00:44 PM UTC 24 946029999 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1781540945 Aug 27 08:00:24 PM UTC 24 Aug 27 08:00:45 PM UTC 24 1951309639 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3994913272 Aug 27 08:00:32 PM UTC 24 Aug 27 08:00:46 PM UTC 24 12604978125 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.874825360 Aug 27 08:00:41 PM UTC 24 Aug 27 08:00:46 PM UTC 24 199554588 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1133759275 Aug 27 08:00:33 PM UTC 24 Aug 27 08:00:48 PM UTC 24 452014876 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.1104413331 Aug 27 08:00:45 PM UTC 24 Aug 27 08:00:50 PM UTC 24 2243645510 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.3425796683 Aug 27 08:00:32 PM UTC 24 Aug 27 08:00:50 PM UTC 24 662686106 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.669469897 Aug 27 08:00:24 PM UTC 24 Aug 27 08:00:50 PM UTC 24 2400913287 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1915925613 Aug 27 08:00:41 PM UTC 24 Aug 27 08:00:52 PM UTC 24 570787548 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.647751636 Aug 27 08:00:40 PM UTC 24 Aug 27 08:00:53 PM UTC 24 114954179 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4062838040 Aug 27 08:00:51 PM UTC 24 Aug 27 08:00:53 PM UTC 24 40625188 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1184508011 Aug 27 08:00:51 PM UTC 24 Aug 27 08:00:53 PM UTC 24 53489364 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1782887328 Aug 27 08:00:33 PM UTC 24 Aug 27 08:00:54 PM UTC 24 1869424991 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1574999753 Aug 27 08:00:25 PM UTC 24 Aug 27 08:00:55 PM UTC 24 570878645 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2174424487 Aug 27 08:00:44 PM UTC 24 Aug 27 08:00:55 PM UTC 24 340570038 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1363240523 Aug 27 08:00:45 PM UTC 24 Aug 27 08:00:55 PM UTC 24 294307429 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.4250265551 Aug 27 08:00:51 PM UTC 24 Aug 27 08:00:55 PM UTC 24 1352184392 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3787321978 Aug 27 08:00:29 PM UTC 24 Aug 27 08:00:56 PM UTC 24 768684536 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.413921193 Aug 27 08:00:54 PM UTC 24 Aug 27 08:00:57 PM UTC 24 37796326 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.3246946337 Aug 27 08:00:53 PM UTC 24 Aug 27 08:00:57 PM UTC 24 350366930 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1758204512 Aug 27 08:00:40 PM UTC 24 Aug 27 08:00:58 PM UTC 24 1215165962 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.2954131882 Aug 27 08:00:42 PM UTC 24 Aug 27 08:00:58 PM UTC 24 1805239622 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1153504899 Aug 27 08:00:46 PM UTC 24 Aug 27 08:00:59 PM UTC 24 1322810956 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.4019460465 Aug 27 08:00:42 PM UTC 24 Aug 27 08:01:00 PM UTC 24 393440238 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.882545293 Aug 27 08:00:32 PM UTC 24 Aug 27 08:01:04 PM UTC 24 9061916434 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1223400126 Aug 27 08:00:52 PM UTC 24 Aug 27 08:01:01 PM UTC 24 80944685 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1187120570 Aug 27 08:01:02 PM UTC 24 Aug 27 08:01:04 PM UTC 24 32117342 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1595734585 Aug 27 08:00:45 PM UTC 24 Aug 27 08:01:04 PM UTC 24 964772443 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.1715319970 Aug 27 08:01:02 PM UTC 24 Aug 27 08:01:04 PM UTC 24 51342829 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.3378510481 Aug 27 08:00:58 PM UTC 24 Aug 27 08:01:05 PM UTC 24 186662104 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1552108074 Aug 27 08:00:19 PM UTC 24 Aug 27 08:01:05 PM UTC 24 961284385 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1669468290 Aug 27 08:00:19 PM UTC 24 Aug 27 08:01:07 PM UTC 24 910413665 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1227396510 Aug 27 08:01:05 PM UTC 24 Aug 27 08:01:07 PM UTC 24 16631576 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3334190698 Aug 27 08:00:59 PM UTC 24 Aug 27 08:01:08 PM UTC 24 287185319 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2300868402 Aug 27 08:00:35 PM UTC 24 Aug 27 08:01:08 PM UTC 24 125194637 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2618606847 Aug 27 08:00:56 PM UTC 24 Aug 27 08:01:09 PM UTC 24 406887407 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3849648645 Aug 27 08:00:54 PM UTC 24 Aug 27 08:01:09 PM UTC 24 959167713 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2729690204 Aug 27 08:01:33 PM UTC 24 Aug 27 08:01:44 PM UTC 24 1145267045 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3671896595 Aug 27 08:00:45 PM UTC 24 Aug 27 08:01:09 PM UTC 24 4692621216 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.54838422 Aug 27 08:01:05 PM UTC 24 Aug 27 08:01:09 PM UTC 24 159348373 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.4137960152 Aug 27 08:01:08 PM UTC 24 Aug 27 08:01:10 PM UTC 24 10986092 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1410734651 Aug 27 08:00:59 PM UTC 24 Aug 27 08:01:10 PM UTC 24 372888253 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2503056690 Aug 27 08:00:41 PM UTC 24 Aug 27 08:01:10 PM UTC 24 752438387 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.825596210 Aug 27 08:00:54 PM UTC 24 Aug 27 08:01:11 PM UTC 24 288875690 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.1343502078 Aug 27 08:00:56 PM UTC 24 Aug 27 08:01:11 PM UTC 24 611188319 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2519520203 Aug 27 08:00:54 PM UTC 24 Aug 27 08:01:11 PM UTC 24 202778402 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.751050734 Aug 27 08:00:58 PM UTC 24 Aug 27 08:01:13 PM UTC 24 1145182365 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.4042409458 Aug 27 08:00:47 PM UTC 24 Aug 27 08:01:13 PM UTC 24 1884647888 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.928500423 Aug 27 08:01:05 PM UTC 24 Aug 27 08:01:14 PM UTC 24 1053285585 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3880374140 Aug 27 08:01:10 PM UTC 24 Aug 27 08:01:14 PM UTC 24 278804249 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.1485525162 Aug 27 08:01:12 PM UTC 24 Aug 27 08:01:15 PM UTC 24 21292466 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.206786831 Aug 27 08:01:13 PM UTC 24 Aug 27 08:01:15 PM UTC 24 24164152 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3047109280 Aug 27 08:01:14 PM UTC 24 Aug 27 08:01:16 PM UTC 24 23466452 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.750400111 Aug 27 08:00:56 PM UTC 24 Aug 27 08:01:17 PM UTC 24 1024958071 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.85862711 Aug 27 08:01:05 PM UTC 24 Aug 27 08:01:17 PM UTC 24 362514630 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.666523937 Aug 27 08:01:06 PM UTC 24 Aug 27 08:01:17 PM UTC 24 1187114870 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.84219285 Aug 27 08:01:09 PM UTC 24 Aug 27 08:01:18 PM UTC 24 293969694 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.1096256668 Aug 27 08:01:08 PM UTC 24 Aug 27 08:01:18 PM UTC 24 986594633 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.390430813 Aug 27 08:00:38 PM UTC 24 Aug 27 08:01:19 PM UTC 24 319726501 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1128163961 Aug 27 08:00:58 PM UTC 24 Aug 27 08:01:19 PM UTC 24 1112011428 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3627249182 Aug 27 08:01:15 PM UTC 24 Aug 27 08:01:20 PM UTC 24 99615597 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2284299460 Aug 27 08:01:17 PM UTC 24 Aug 27 08:01:20 PM UTC 24 42164926 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.1221408915 Aug 27 08:01:10 PM UTC 24 Aug 27 08:01:20 PM UTC 24 4503670695 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.1937500311 Aug 27 08:01:11 PM UTC 24 Aug 27 08:01:21 PM UTC 24 385679494 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2836798159 Aug 27 08:00:52 PM UTC 24 Aug 27 08:01:23 PM UTC 24 228920413 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.552783910 Aug 27 08:01:18 PM UTC 24 Aug 27 08:01:23 PM UTC 24 343005194 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1945616809 Aug 27 08:00:32 PM UTC 24 Aug 27 08:01:23 PM UTC 24 1746939878 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3864640359 Aug 27 08:01:11 PM UTC 24 Aug 27 08:01:24 PM UTC 24 320596776 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2255037117 Aug 27 08:01:33 PM UTC 24 Aug 27 08:01:42 PM UTC 24 1001024101 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.937634027 Aug 27 08:01:15 PM UTC 24 Aug 27 08:01:25 PM UTC 24 212871286 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.643170866 Aug 27 08:01:19 PM UTC 24 Aug 27 08:01:25 PM UTC 24 407620594 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.43822216 Aug 27 08:01:39 PM UTC 24 Aug 27 08:01:42 PM UTC 24 10051254 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1716280022 Aug 27 08:01:11 PM UTC 24 Aug 27 08:01:26 PM UTC 24 1169437498 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1631064917 Aug 27 08:01:20 PM UTC 24 Aug 27 08:01:26 PM UTC 24 267557974 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.4157547981 Aug 27 08:01:09 PM UTC 24 Aug 27 08:01:27 PM UTC 24 735725668 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1417631281 Aug 27 08:01:17 PM UTC 24 Aug 27 08:01:27 PM UTC 24 1447432603 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.2735950049 Aug 27 08:01:25 PM UTC 24 Aug 27 08:01:28 PM UTC 24 15496235 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2698915793 Aug 27 08:01:25 PM UTC 24 Aug 27 08:01:28 PM UTC 24 14330908 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.789279659 Aug 27 08:01:16 PM UTC 24 Aug 27 08:01:29 PM UTC 24 2193449847 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.175108953 Aug 27 08:00:16 PM UTC 24 Aug 27 08:01:43 PM UTC 24 2124062054 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.3792249341 Aug 27 08:01:28 PM UTC 24 Aug 27 08:01:30 PM UTC 24 13829421 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3601585701 Aug 27 08:01:25 PM UTC 24 Aug 27 08:01:30 PM UTC 24 109298068 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.138977307 Aug 27 08:00:44 PM UTC 24 Aug 27 08:01:31 PM UTC 24 1278290584 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2857236824 Aug 27 08:01:21 PM UTC 24 Aug 27 08:01:31 PM UTC 24 1017158261 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3945767850 Aug 27 08:00:23 PM UTC 24 Aug 27 08:01:31 PM UTC 24 2394264806 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.463250657 Aug 27 08:00:58 PM UTC 24 Aug 27 08:01:31 PM UTC 24 2248245010 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.531232031 Aug 27 08:01:26 PM UTC 24 Aug 27 08:01:32 PM UTC 24 327442545 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.1313438201 Aug 27 08:00:50 PM UTC 24 Aug 27 08:01:32 PM UTC 24 139598412 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.752889188 Aug 27 08:01:26 PM UTC 24 Aug 27 08:01:32 PM UTC 24 1533019238 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.2569685524 Aug 27 08:01:16 PM UTC 24 Aug 27 08:01:34 PM UTC 24 722334802 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.3118539715 Aug 27 08:01:31 PM UTC 24 Aug 27 08:01:35 PM UTC 24 697722587 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.2484470436 Aug 27 08:01:30 PM UTC 24 Aug 27 08:01:35 PM UTC 24 528074003 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.1298451628 Aug 27 08:01:21 PM UTC 24 Aug 27 08:01:35 PM UTC 24 346719660 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.127757304 Aug 27 08:01:09 PM UTC 24 Aug 27 08:01:36 PM UTC 24 4055970144 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2002638808 Aug 27 08:01:29 PM UTC 24 Aug 27 08:01:36 PM UTC 24 326216318 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.1571163839 Aug 27 08:01:33 PM UTC 24 Aug 27 08:01:37 PM UTC 24 25622478 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.3044513996 Aug 27 08:01:28 PM UTC 24 Aug 27 08:01:38 PM UTC 24 191765424 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1222695012 Aug 27 08:01:36 PM UTC 24 Aug 27 08:01:38 PM UTC 24 38887561 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2377755760 Aug 27 08:01:34 PM UTC 24 Aug 27 08:01:38 PM UTC 24 169206891 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1786947123 Aug 27 08:01:26 PM UTC 24 Aug 27 08:01:39 PM UTC 24 1070537798 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2766710114 Aug 27 08:00:58 PM UTC 24 Aug 27 08:01:39 PM UTC 24 9964644570 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.973815026 Aug 27 08:00:56 PM UTC 24 Aug 27 08:01:40 PM UTC 24 2196076202 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.926004279 Aug 27 08:01:01 PM UTC 24 Aug 27 08:01:40 PM UTC 24 2056099124 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.7943790 Aug 27 08:01:36 PM UTC 24 Aug 27 08:01:41 PM UTC 24 55957022 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2589205093 Aug 27 08:00:35 PM UTC 24 Aug 27 08:01:41 PM UTC 24 14722987845 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.1370763692 Aug 27 08:01:29 PM UTC 24 Aug 27 08:01:42 PM UTC 24 2085757470 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.1001760958 Aug 27 08:01:24 PM UTC 24 Aug 27 08:01:44 PM UTC 24 354053605 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.41193554 Aug 27 08:01:36 PM UTC 24 Aug 27 08:01:44 PM UTC 24 278878648 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3999663608 Aug 27 08:01:10 PM UTC 24 Aug 27 08:01:44 PM UTC 24 1039487433 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3145189310 Aug 27 08:01:19 PM UTC 24 Aug 27 08:01:45 PM UTC 24 4004296916 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1038291592 Aug 27 08:01:28 PM UTC 24 Aug 27 08:01:46 PM UTC 24 1910303905 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.1510885288 Aug 27 08:01:20 PM UTC 24 Aug 27 08:01:46 PM UTC 24 4215159656 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1508615001 Aug 27 08:01:21 PM UTC 24 Aug 27 08:01:46 PM UTC 24 3591694529 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.2311672092 Aug 27 08:01:37 PM UTC 24 Aug 27 08:01:47 PM UTC 24 496899303 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3043455229 Aug 27 08:01:41 PM UTC 24 Aug 27 08:01:47 PM UTC 24 157726425 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.654533619 Aug 27 08:01:38 PM UTC 24 Aug 27 08:01:47 PM UTC 24 819837661 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3208198240 Aug 27 08:01:45 PM UTC 24 Aug 27 08:01:48 PM UTC 24 20448057 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.303762460 Aug 27 08:01:42 PM UTC 24 Aug 27 08:01:48 PM UTC 24 226616098 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.155472048 Aug 27 08:01:45 PM UTC 24 Aug 27 08:01:48 PM UTC 24 103049176 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.2409955740 Aug 27 08:01:45 PM UTC 24 Aug 27 08:01:50 PM UTC 24 92496027 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.227347571 Aug 27 08:01:33 PM UTC 24 Aug 27 08:01:50 PM UTC 24 813619428 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.479397267 Aug 27 08:01:48 PM UTC 24 Aug 27 08:01:50 PM UTC 24 13552651 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1051047526 Aug 27 08:01:05 PM UTC 24 Aug 27 08:01:51 PM UTC 24 688997518 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.3406669865 Aug 27 08:01:46 PM UTC 24 Aug 27 08:01:51 PM UTC 24 72549702 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.632150998 Aug 27 08:01:42 PM UTC 24 Aug 27 08:01:52 PM UTC 24 333521465 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.3334506271 Aug 27 08:01:39 PM UTC 24 Aug 27 08:01:52 PM UTC 24 1595057278 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1116815284 Aug 27 08:01:15 PM UTC 24 Aug 27 08:01:52 PM UTC 24 261439540 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1219732364 Aug 27 08:01:09 PM UTC 24 Aug 27 08:01:53 PM UTC 24 4729628029 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.534927046 Aug 27 08:01:49 PM UTC 24 Aug 27 08:01:53 PM UTC 24 149922449 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.4186877083 Aug 27 08:01:40 PM UTC 24 Aug 27 08:01:54 PM UTC 24 283918641 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1261117 Aug 27 08:01:43 PM UTC 24 Aug 27 08:01:54 PM UTC 24 881026631 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2738885576 Aug 27 08:01:46 PM UTC 24 Aug 27 08:01:55 PM UTC 24 74597201 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1029972282 Aug 27 08:01:48 PM UTC 24 Aug 27 08:01:55 PM UTC 24 780483615 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3634552831 Aug 27 08:01:32 PM UTC 24 Aug 27 08:01:55 PM UTC 24 7575719991 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3420270604 Aug 27 08:01:43 PM UTC 24 Aug 27 08:01:56 PM UTC 24 1524315428 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1131170140 Aug 27 08:01:46 PM UTC 24 Aug 27 08:01:56 PM UTC 24 295346311 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.557125879 Aug 27 08:01:54 PM UTC 24 Aug 27 08:01:56 PM UTC 24 43640864 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3238553368 Aug 27 08:01:20 PM UTC 24 Aug 27 08:01:57 PM UTC 24 10225487293 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1227052426 Aug 27 08:01:55 PM UTC 24 Aug 27 08:01:57 PM UTC 24 10196195 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.4089091246 Aug 27 08:01:48 PM UTC 24 Aug 27 08:01:58 PM UTC 24 574496667 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.354483220 Aug 27 08:01:37 PM UTC 24 Aug 27 08:01:58 PM UTC 24 892392894 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2483412604 Aug 27 08:01:55 PM UTC 24 Aug 27 08:01:59 PM UTC 24 121262915 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1584659549 Aug 27 08:01:57 PM UTC 24 Aug 27 08:02:00 PM UTC 24 121228854 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1897302362 Aug 27 08:01:43 PM UTC 24 Aug 27 08:02:01 PM UTC 24 1307358807 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3297605510 Aug 27 08:01:51 PM UTC 24 Aug 27 08:02:02 PM UTC 24 3566035628 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.2071252905 Aug 27 08:01:57 PM UTC 24 Aug 27 08:02:02 PM UTC 24 233050268 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.1315108912 Aug 27 08:01:26 PM UTC 24 Aug 27 08:02:02 PM UTC 24 331668128 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3070245713 Aug 27 08:01:51 PM UTC 24 Aug 27 08:02:02 PM UTC 24 454015113 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.3590060039 Aug 27 08:00:21 PM UTC 24 Aug 27 08:02:03 PM UTC 24 2596885923 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1018096006 Aug 27 08:02:09 PM UTC 24 Aug 27 08:02:20 PM UTC 24 700431090 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.24357261 Aug 27 08:01:49 PM UTC 24 Aug 27 08:02:04 PM UTC 24 412462132 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3713648788 Aug 27 08:00:41 PM UTC 24 Aug 27 08:02:04 PM UTC 24 11083587398 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2774436132 Aug 27 08:00:47 PM UTC 24 Aug 27 08:02:04 PM UTC 24 12327730516 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1243849292 Aug 27 08:02:00 PM UTC 24 Aug 27 08:02:05 PM UTC 24 524870247 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2633129355 Aug 27 08:02:03 PM UTC 24 Aug 27 08:02:06 PM UTC 24 18129116 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.3977289188 Aug 27 08:01:56 PM UTC 24 Aug 27 08:02:06 PM UTC 24 74365735 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3092010960 Aug 27 08:02:06 PM UTC 24 Aug 27 08:02:20 PM UTC 24 375575926 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.4240037231 Aug 27 08:01:53 PM UTC 24 Aug 27 08:02:06 PM UTC 24 973016409 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3742185641 Aug 27 08:01:53 PM UTC 24 Aug 27 08:02:07 PM UTC 24 299179495 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.204182798 Aug 27 08:02:05 PM UTC 24 Aug 27 08:02:07 PM UTC 24 13895241 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3535754760 Aug 27 08:02:05 PM UTC 24 Aug 27 08:02:07 PM UTC 24 190349972 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.3151360956 Aug 27 08:02:00 PM UTC 24 Aug 27 08:02:07 PM UTC 24 577628041 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.2873613325 Aug 27 08:01:53 PM UTC 24 Aug 27 08:02:08 PM UTC 24 297109321 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.572078753 Aug 27 08:01:58 PM UTC 24 Aug 27 08:02:20 PM UTC 24 2109522485 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.3334503791 Aug 27 08:01:57 PM UTC 24 Aug 27 08:02:08 PM UTC 24 535869415 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1928210491 Aug 27 08:02:06 PM UTC 24 Aug 27 08:02:11 PM UTC 24 50994975 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3524402826 Aug 27 08:02:03 PM UTC 24 Aug 27 08:02:12 PM UTC 24 483076971 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3802461248 Aug 27 08:02:02 PM UTC 24 Aug 27 08:02:12 PM UTC 24 196722059 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2048141925 Aug 27 08:01:32 PM UTC 24 Aug 27 08:02:12 PM UTC 24 6068412526 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3629064700 Aug 27 08:01:19 PM UTC 24 Aug 27 08:02:12 PM UTC 24 1277901429 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.10821994 Aug 27 08:02:02 PM UTC 24 Aug 27 08:02:12 PM UTC 24 1605656838 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3840155754 Aug 27 08:01:31 PM UTC 24 Aug 27 08:02:13 PM UTC 24 7083338013 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2558034695 Aug 27 08:01:53 PM UTC 24 Aug 27 08:02:13 PM UTC 24 2194910232 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3926158177 Aug 27 08:01:46 PM UTC 24 Aug 27 08:02:14 PM UTC 24 4071618034 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.1078917001 Aug 27 08:02:09 PM UTC 24 Aug 27 08:02:14 PM UTC 24 98851398 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2994913413 Aug 27 08:01:50 PM UTC 24 Aug 27 08:02:15 PM UTC 24 925028446 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3754193884 Aug 27 08:01:36 PM UTC 24 Aug 27 08:02:15 PM UTC 24 1602408586 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.478038217 Aug 27 08:02:07 PM UTC 24 Aug 27 08:02:15 PM UTC 24 318782753 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.3273216904 Aug 27 08:01:57 PM UTC 24 Aug 27 08:02:16 PM UTC 24 836764873 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2625932230 Aug 27 08:02:14 PM UTC 24 Aug 27 08:02:16 PM UTC 24 12692466 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.640684297 Aug 27 08:02:14 PM UTC 24 Aug 27 08:02:16 PM UTC 24 12942631 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.529474149 Aug 27 08:02:08 PM UTC 24 Aug 27 08:02:17 PM UTC 24 398704071 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.2022315552 Aug 27 08:02:14 PM UTC 24 Aug 27 08:02:17 PM UTC 24 62989357 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.3545328903 Aug 27 08:02:14 PM UTC 24 Aug 27 08:02:18 PM UTC 24 19401941 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.2289479472 Aug 27 08:01:51 PM UTC 24 Aug 27 08:02:20 PM UTC 24 1439561371 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1771668964 Aug 27 08:01:45 PM UTC 24 Aug 27 08:02:21 PM UTC 24 22692470743 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1763070888 Aug 27 08:01:42 PM UTC 24 Aug 27 08:02:21 PM UTC 24 1356351098 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3202872681 Aug 27 08:02:05 PM UTC 24 Aug 27 08:02:21 PM UTC 24 364589177 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.1523036010 Aug 27 08:01:41 PM UTC 24 Aug 27 08:02:22 PM UTC 24 6175505361 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.3525891965 Aug 27 08:02:09 PM UTC 24 Aug 27 08:02:23 PM UTC 24 493990447 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.739122009 Aug 27 08:02:21 PM UTC 24 Aug 27 08:02:23 PM UTC 24 126015445 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.105356667 Aug 27 08:02:14 PM UTC 24 Aug 27 08:02:24 PM UTC 24 103345744 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1287012923 Aug 27 08:02:22 PM UTC 24 Aug 27 08:02:25 PM UTC 24 48300273 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.4289757581 Aug 27 08:02:06 PM UTC 24 Aug 27 08:02:25 PM UTC 24 804197784 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.3058525577 Aug 27 08:02:17 PM UTC 24 Aug 27 08:02:25 PM UTC 24 1204688629 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.3803305015 Aug 27 08:02:21 PM UTC 24 Aug 27 08:02:26 PM UTC 24 427413081 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1734724907 Aug 27 08:02:12 PM UTC 24 Aug 27 08:02:27 PM UTC 24 674995740 ps