Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56078137

1

T1

1788

T2

8851

T3

1060

auto[1]

1186909

1

T4

693

T5

396

T7

196

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56094211

1

T1

1788

T2

8851

T3

1060

auto[1]

1170835

1

T4

1188

T5

495

T14

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5630646	1			T1	110		T2	1707		T3	86
auto[IdleSt]	16028844	1			T1	215		T2	467		T3	974
auto[ClkMuxSt]	29358	1			T1	1		T2	31		T4	19
auto[CntIncrSt]	29143	1			T1	1		T2	18		T4	19
auto[CntProgSt]	1512970	1			T1	110		T2	36		T4	394
auto[TransCheckSt]	23031	1			T1	1		T2	18		T5	6
auto[TokenHashSt]	11233058	1			T1	43		T2	5212		T5	318
auto[FlashRmaSt]	28886	1			T1	20		T2	115		T5	6
auto[TokenCheck0St]	10427	1			T1	1		T2	18		T5	6
auto[TokenCheck1St]	7444	1			T1	1		T2	18		T5	6
auto[TransProgSt]	337521	1			T1	281		T2	36		T5	33
auto[PostTransSt]	9317250	1			T1	1004		T2	1167		T4	1126
auto[ScrapSt]	190611	1			T2	8		T18	20		T44	4
auto[EscalateSt]	4983947	1			T4	2484		T5	1538		T7	851
auto[InvalidSt]	7900427	1			T5	678		T16	2987		T48	3573

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1483	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7900427	1			T5	678		T16	2987		T48	3573
EscalateSt	4983947	1			T4	2484		T5	1538		T7	851
ScrapSt	190611	1			T2	8		T18	20		T44	4
PostTransSt	9317250	1			T1	1004		T2	1167		T4	1126
TransProgSt	337521	1			T1	281		T2	36		T5	33
TokenCheck1St	7444	1			T1	1		T2	18		T5	6
TokenCheck0St	10427	1			T1	1		T2	18		T5	6
FlashRmaSt	28886	1			T1	20		T2	115		T5	6
TokenHashSt	11233058	1			T1	43		T2	5212		T5	318
TransCheckSt	23031	1			T1	1		T2	18		T5	6
CntProgSt	1512970	1			T1	110		T2	36		T4	394
CntIncrSt	29143	1			T1	1		T2	18		T4	19
ClkMuxSt	29358	1			T1	1		T2	31		T4	19
IdleSt	16028844	1			T1	215		T2	467		T3	974
ResetSt	5630646	1			T1	110		T2	1707		T3	86
arcs[ResetSt=>IdleSt]	43746	1			T1	1		T2	19		T3	1
arcs[IdleSt=>ScrapSt]	218	1			T2	1		T18	2		T44	1
arcs[IdleSt=>ClkMuxSt]	29172	1			T1	1		T2	18		T4	19
arcs[ClkMuxSt=>CntIncrSt]	29143	1			T1	1		T2	18		T4	19
arcs[CntIncrSt=>PostTransSt]	1286	1			T14	12		T49	13		T50	9
arcs[CntIncrSt=>CntProgSt]	27797	1			T1	1		T2	18		T4	19
arcs[CntProgSt=>PostTransSt]	3785	1			T4	19		T7	2		T14	16
arcs[CntProgSt=>TransCheckSt]	23031	1			T1	1		T2	18		T5	6
arcs[TransCheckSt=>PostTransSt]	3167	1			T14	8		T17	45		T49	16
arcs[TransCheckSt=>TokenHashSt]	19757	1			T1	1		T2	18		T5	6
arcs[TokenHashSt=>PostTransSt]	8445	1			T14	28		T17	9		T47	75
arcs[TokenHashSt=>FlashRmaSt]	10461	1			T1	1		T2	18		T5	6
arcs[FlashRmaSt=>TokenCheck0St]	10427	1			T1	1		T2	18		T5	6
arcs[TokenCheck0St=>PostTransSt]	2914	1			T14	6		T17	17		T48	8
arcs[TokenCheck0St=>TokenCheck1St]	7444	1			T1	1		T2	18		T5	6
arcs[TokenCheck1St=>PostTransSt]	593	1			T17	4		T35	8		T38	14
arcs[TransProgSt=>PostTransSt]	6044	1			T1	1		T2	18		T5	6
arcs[IdleSt=>EscalateSt]	177	1			T44	3		T45	3		T68	2
arcs[ClkMuxSt=>EscalateSt]	29	1			T45	1		T63	1		T64	1
arcs[CntIncrSt=>EscalateSt]	60	1			T44	3		T65	3		T45	1
arcs[CntProgSt=>EscalateSt]	981	1			T44	35		T65	32		T45	2
arcs[TransCheckSt=>EscalateSt]	107	1			T45	4		T68	7		T67	1
arcs[TokenHashSt=>EscalateSt]	851	1			T44	8		T65	15		T45	23
arcs[FlashRmaSt=>EscalateSt]	34	1			T44	2		T66	2		T67	1
arcs[TokenCheck0St=>EscalateSt]	69	1			T44	3		T65	4		T45	1
arcs[TokenCheck1St=>EscalateSt]	28	1			T65	2		T45	3		T68	1
arcs[TransProgSt=>EscalateSt]	779	1			T44	29		T65	28		T45	7
arcs[PostTransSt=>EscalateSt]	4124	1			T4	19		T7	2		T14	17
arcs[InvalidSt=>EscalateSt]	10649	1			T5	9		T16	2		T48	18

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5630467	1			T1	110		T2	1707		T3	86
auto[0]	auto[IdleSt]	16028732	1			T1	215		T2	467		T3	974
auto[0]	auto[ClkMuxSt]	29343	1			T1	1		T2	31		T4	19
auto[0]	auto[CntIncrSt]	29101	1			T1	1		T2	18		T4	19
auto[0]	auto[CntProgSt]	1512331	1			T1	110		T2	36		T4	394
auto[0]	auto[TransCheckSt]	22961	1			T1	1		T2	18		T5	6
auto[0]	auto[TokenHashSt]	11232478	1			T1	43		T2	5212		T5	318
auto[0]	auto[FlashRmaSt]	28865	1			T1	20		T2	115		T5	6
auto[0]	auto[TokenCheck0St]	10375	1			T1	1		T2	18		T5	6
auto[0]	auto[TokenCheck1St]	7428	1			T1	1		T2	18		T5	6
auto[0]	auto[TransProgSt]	337003	1			T1	281		T2	36		T5	33
auto[0]	auto[PostTransSt]	9315127	1			T1	1004		T2	1167		T4	1119
auto[0]	auto[ScrapSt]	190566	1			T2	8		T18	20		T44	3
auto[0]	auto[EscalateSt]	3806859	1			T4	1798		T5	1146		T7	657
auto[0]	auto[InvalidSt]	7895018	1			T5	674		T16	2986		T48	3564
auto[1]	auto[ResetSt]	179	1			T44	4		T65	3		T68	1
auto[1]	auto[IdleSt]	112	1			T45	2		T68	2		T67	3
auto[1]	auto[ClkMuxSt]	15	1			T63	1		T239	1		T240	2
auto[1]	auto[CntIncrSt]	42	1			T44	3		T65	3		T45	1
auto[1]	auto[CntProgSt]	639	1			T44	16		T65	24		T45	1
auto[1]	auto[TransCheckSt]	70	1			T45	2		T68	4		T241	2
auto[1]	auto[TokenHashSt]	580	1			T44	6		T65	11		T45	17
auto[1]	auto[FlashRmaSt]	21	1			T44	2		T66	1		T241	1
auto[1]	auto[TokenCheck0St]	52	1			T44	3		T65	3		T45	1
auto[1]	auto[TokenCheck1St]	16	1			T65	2		T45	2		T242	1
auto[1]	auto[TransProgSt]	518	1			T44	17		T65	22		T45	6
auto[1]	auto[PostTransSt]	2123	1			T4	7		T7	2		T14	11
auto[1]	auto[ScrapSt]	45	1			T44	1		T65	3		T67	1
auto[1]	auto[EscalateSt]	1177088	1			T4	686		T5	392		T7	194
auto[1]	auto[InvalidSt]	5409	1			T5	4		T16	1		T48	9

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5630470	1			T1	110		T2	1707		T3	86
auto[0]	auto[IdleSt]	16028721	1			T1	215		T2	467		T3	974
auto[0]	auto[ClkMuxSt]	29335	1			T1	1		T2	31		T4	19
auto[0]	auto[CntIncrSt]	29101	1			T1	1		T2	18		T4	19
auto[0]	auto[CntProgSt]	1512308	1			T1	110		T2	36		T4	394
auto[0]	auto[TransCheckSt]	22958	1			T1	1		T2	18		T5	6
auto[0]	auto[TokenHashSt]	11232509	1			T1	43		T2	5212		T5	318
auto[0]	auto[FlashRmaSt]	28866	1			T1	20		T2	115		T5	6
auto[0]	auto[TokenCheck0St]	10385	1			T1	1		T2	18		T5	6
auto[0]	auto[TokenCheck1St]	7427	1			T1	1		T2	18		T5	6
auto[0]	auto[TransProgSt]	336998	1			T1	281		T2	36		T5	33
auto[0]	auto[PostTransSt]	9315146	1			T1	1004		T2	1167		T4	1114
auto[0]	auto[ScrapSt]	190575	1			T2	8		T18	20		T44	4
auto[0]	auto[EscalateSt]	3822742	1			T4	1308		T5	1048		T7	851
auto[0]	auto[InvalidSt]	7895187	1			T5	673		T16	2986		T48	3564
auto[1]	auto[ResetSt]	176	1			T44	5		T65	5		T45	1
auto[1]	auto[IdleSt]	123	1			T44	3		T45	1		T68	2
auto[1]	auto[ClkMuxSt]	23	1			T45	1		T63	1		T64	1
auto[1]	auto[CntIncrSt]	42	1			T44	1		T65	2		T68	2
auto[1]	auto[CntProgSt]	662	1			T44	30		T65	19		T45	1
auto[1]	auto[TransCheckSt]	73	1			T45	3		T68	3		T67	1
auto[1]	auto[TokenHashSt]	549	1			T44	5		T65	11		T45	15
auto[1]	auto[FlashRmaSt]	20	1			T44	1		T66	2		T67	1
auto[1]	auto[TokenCheck0St]	42	1			T44	2		T65	3		T45	1
auto[1]	auto[TokenCheck1St]	17	1			T65	1		T45	2		T68	1
auto[1]	auto[TransProgSt]	523	1			T44	19		T65	19		T45	5
auto[1]	auto[PostTransSt]	2104	1			T4	12		T14	6		T44	1
auto[1]	auto[ScrapSt]	36	1			T65	2		T67	1		T241	1
auto[1]	auto[EscalateSt]	1161205	1			T4	1176		T5	490		T14	588
auto[1]	auto[InvalidSt]	5240	1			T5	5		T16	1		T48	9