Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.99 95.77 93.40 100.00 98.55 98.76 96.29


Total tests in report: 999
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.03 64.03 81.89 81.89 51.94 51.94 58.03 58.03 48.84 48.84 82.78 82.78 92.04 92.04 32.69 32.69 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2220557944
74.03 10.00 88.63 6.74 79.03 27.09 74.73 16.70 53.49 4.65 88.17 5.39 94.03 1.99 40.11 7.42 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3812606868
80.01 5.98 88.93 0.30 80.29 1.26 82.89 8.16 76.74 23.26 90.46 2.28 94.28 0.25 46.47 6.36 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2402971729
85.13 5.12 95.27 6.34 81.10 0.81 83.77 0.88 76.74 0.00 92.32 1.87 94.28 0.00 72.44 25.97 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.633888105
86.50 1.36 96.28 1.01 84.25 3.15 83.96 0.19 76.74 0.00 93.78 1.45 95.02 0.75 75.44 3.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.470218680
87.76 1.27 96.28 0.00 84.25 0.00 86.87 2.91 79.07 2.33 94.40 0.62 95.02 0.00 78.45 3.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1097247036
89.02 1.26 96.33 0.05 84.25 0.00 86.87 0.00 86.05 6.98 94.61 0.21 95.02 0.00 80.04 1.59 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1752057021
90.22 1.20 96.58 0.25 86.32 2.07 86.98 0.10 86.05 0.00 95.23 0.62 95.77 0.75 84.63 4.59 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1275760454
91.03 0.81 97.08 0.50 87.94 1.62 86.99 0.01 88.37 2.33 96.27 1.04 95.77 0.00 84.81 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3331450374
91.76 0.73 97.13 0.05 88.57 0.63 87.39 0.40 90.70 2.33 96.47 0.21 96.02 0.25 86.04 1.24 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2790678206
92.46 0.70 97.18 0.05 88.57 0.00 87.96 0.57 93.02 2.33 96.68 0.21 96.02 0.00 87.81 1.77 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.4263599896
92.98 0.51 97.23 0.05 89.65 1.08 87.96 0.00 93.02 0.00 97.30 0.62 96.27 0.25 89.40 1.59 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1305118968
93.41 0.44 97.23 0.00 90.73 1.08 88.28 0.32 93.02 0.00 97.30 0.00 96.52 0.25 90.81 1.41 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.954886385
93.82 0.40 97.23 0.00 90.73 0.00 91.09 2.81 93.02 0.00 97.30 0.00 96.52 0.00 90.81 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1819851324
94.19 0.37 97.23 0.00 91.00 0.27 91.09 0.00 95.35 2.33 97.30 0.00 96.52 0.00 90.81 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.1334802503
94.55 0.36 97.23 0.00 91.00 0.00 91.09 0.00 97.67 2.33 97.51 0.21 96.52 0.00 90.81 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2196979198
94.88 0.33 97.23 0.00 91.00 0.00 91.09 0.00 100.00 2.33 97.51 0.00 96.52 0.00 90.81 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.908192382
95.20 0.31 97.23 0.00 91.00 0.00 92.41 1.32 100.00 0.00 97.51 0.00 96.52 0.00 91.70 0.88 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.45354228
95.45 0.26 97.33 0.10 91.45 0.45 92.41 0.00 100.00 0.00 97.72 0.21 96.52 0.00 92.76 1.06 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.229301751
95.67 0.21 97.33 0.00 91.45 0.00 92.41 0.00 100.00 0.00 97.72 0.00 98.01 1.49 92.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3865450496
95.88 0.21 97.69 0.35 92.35 0.90 92.61 0.20 100.00 0.00 97.72 0.00 98.01 0.00 92.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.732204405
96.05 0.17 97.84 0.15 92.44 0.09 92.77 0.16 100.00 0.00 97.93 0.21 98.26 0.25 93.11 0.35 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.918064355
96.20 0.15 97.89 0.05 92.44 0.00 93.06 0.28 100.00 0.00 98.13 0.21 98.26 0.00 93.64 0.53 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1062806958
96.31 0.10 97.99 0.10 92.44 0.00 93.12 0.06 100.00 0.00 98.34 0.21 98.26 0.00 93.99 0.35 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1903860202
96.41 0.10 97.99 0.00 93.16 0.72 93.12 0.00 100.00 0.00 98.34 0.00 98.26 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.285020632
96.49 0.08 97.99 0.00 93.70 0.54 93.12 0.00 100.00 0.00 98.34 0.00 98.26 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2910363721
96.56 0.08 97.99 0.00 93.70 0.00 93.12 0.00 100.00 0.00 98.34 0.00 98.26 0.00 94.52 0.53 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1797721703
96.64 0.08 97.99 0.00 93.70 0.00 93.12 0.00 100.00 0.00 98.34 0.00 98.26 0.00 95.05 0.53 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2273659603
96.71 0.07 97.99 0.00 93.70 0.00 93.12 0.00 100.00 0.00 98.34 0.00 98.76 0.50 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1886598585
96.77 0.06 97.99 0.00 94.15 0.45 93.12 0.00 100.00 0.00 98.34 0.00 98.76 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3914335090
96.84 0.06 97.99 0.00 94.42 0.27 93.12 0.00 100.00 0.00 98.34 0.00 98.76 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.214448129
96.89 0.05 97.99 0.00 94.42 0.00 93.12 0.00 100.00 0.00 98.34 0.00 98.76 0.00 95.58 0.35 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.1159025723
96.93 0.04 97.99 0.00 94.51 0.09 93.12 0.00 100.00 0.00 98.55 0.21 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.619779854
96.97 0.04 97.99 0.00 94.78 0.27 93.12 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2206451285
97.00 0.03 97.99 0.00 94.78 0.00 93.36 0.24 100.00 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1109579989
97.03 0.03 97.99 0.00 94.96 0.18 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1929610341
97.05 0.03 97.99 0.00 95.14 0.18 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.589266198
97.08 0.03 97.99 0.00 95.14 0.00 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.4030545678
97.10 0.03 97.99 0.00 95.14 0.00 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.195865702
97.13 0.03 97.99 0.00 95.14 0.00 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.530811211
97.15 0.03 97.99 0.00 95.14 0.00 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.3606084993
97.17 0.01 97.99 0.00 95.23 0.09 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1550836605
97.18 0.01 97.99 0.00 95.32 0.09 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1477428641
97.19 0.01 97.99 0.00 95.41 0.09 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2081223187
97.21 0.01 97.99 0.00 95.50 0.09 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.629153264
97.22 0.01 97.99 0.00 95.59 0.09 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1552128827
97.23 0.01 97.99 0.00 95.68 0.09 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.606478925
97.24 0.01 97.99 0.00 95.77 0.09 93.36 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2146446969
97.25 0.01 97.99 0.00 95.77 0.00 93.38 0.02 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3473608441
97.25 0.01 97.99 0.00 95.77 0.00 93.40 0.02 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1593901290

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1746676835
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2904595945
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2839866451
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.82030301
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4138789060
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2496783088
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.292724566
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2858810192
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2044592238
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2474419125
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1349515824
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3433324691
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.297484801
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.36123508
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.938638257
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2005579757
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1281587634
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4149970068
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3106049724
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2787663977
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1323102915
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1473577265
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1974636502
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.858539394
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2179623658
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.248062938
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2150081567
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3808857251
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.282492066
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.304851394
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1309369065
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2079348377
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3307035327
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1097225632
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3561601470
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1198743316
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3671307546
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/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.152422602
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.842342060
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.2631284858
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/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.825954001



Total test records in report: 999
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.4178202674 Aug 29 12:51:20 PM UTC 24 Aug 29 12:51:23 PM UTC 24 17903384 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.4195278551 Aug 29 12:51:19 PM UTC 24 Aug 29 12:51:27 PM UTC 24 92227203 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3693028237 Aug 29 12:51:27 PM UTC 24 Aug 29 12:51:29 PM UTC 24 10619699 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3162821219 Aug 29 12:51:23 PM UTC 24 Aug 29 12:51:30 PM UTC 24 290257023 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1022470860 Aug 29 12:51:31 PM UTC 24 Aug 29 12:51:34 PM UTC 24 153171566 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.1192923704 Aug 29 12:51:23 PM UTC 24 Aug 29 12:51:35 PM UTC 24 66564479 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1903860202 Aug 29 12:51:31 PM UTC 24 Aug 29 12:51:35 PM UTC 24 162655048 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3473608441 Aug 29 12:51:28 PM UTC 24 Aug 29 12:51:37 PM UTC 24 172092653 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2220557944 Aug 29 12:51:24 PM UTC 24 Aug 29 12:51:37 PM UTC 24 348882824 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.1822035019 Aug 29 12:51:32 PM UTC 24 Aug 29 12:51:39 PM UTC 24 302889665 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3303842201 Aug 29 12:51:27 PM UTC 24 Aug 29 12:51:42 PM UTC 24 1457172999 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.732204405 Aug 29 12:51:40 PM UTC 24 Aug 29 12:51:43 PM UTC 24 94480933 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3812606868 Aug 29 12:51:29 PM UTC 24 Aug 29 12:51:44 PM UTC 24 367969465 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.4263599896 Aug 29 12:51:36 PM UTC 24 Aug 29 12:51:45 PM UTC 24 996100287 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.3431470236 Aug 29 12:51:40 PM UTC 24 Aug 29 12:51:45 PM UTC 24 39685407 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2447343211 Aug 29 12:51:43 PM UTC 24 Aug 29 12:51:46 PM UTC 24 23329647 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2402971729 Aug 29 12:51:27 PM UTC 24 Aug 29 12:51:49 PM UTC 24 1658997144 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.4030545678 Aug 29 12:51:47 PM UTC 24 Aug 29 12:51:50 PM UTC 24 21631049 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3026806678 Aug 29 12:51:46 PM UTC 24 Aug 29 12:51:51 PM UTC 24 45856696 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.1970611472 Aug 29 12:51:36 PM UTC 24 Aug 29 12:51:51 PM UTC 24 278116201 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.633888105 Aug 29 12:51:36 PM UTC 24 Aug 29 12:51:51 PM UTC 24 312992011 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.918064355 Aug 29 12:51:47 PM UTC 24 Aug 29 12:51:58 PM UTC 24 424412622 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3538279398 Aug 29 12:51:52 PM UTC 24 Aug 29 12:51:58 PM UTC 24 718259169 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.2231918758 Aug 29 12:51:50 PM UTC 24 Aug 29 12:51:58 PM UTC 24 2544466055 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1837944533 Aug 29 12:51:46 PM UTC 24 Aug 29 12:51:58 PM UTC 24 55816665 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4282153404 Aug 29 12:51:33 PM UTC 24 Aug 29 12:51:59 PM UTC 24 793822020 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.2462398686 Aug 29 12:51:21 PM UTC 24 Aug 29 12:52:00 PM UTC 24 1148784023 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.2079178837 Aug 29 12:52:42 PM UTC 24 Aug 29 12:52:48 PM UTC 24 153665153 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3950980854 Aug 29 12:51:47 PM UTC 24 Aug 29 12:52:01 PM UTC 24 1921339140 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.406916052 Aug 29 12:51:54 PM UTC 24 Aug 29 12:52:03 PM UTC 24 1051676299 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1512582153 Aug 29 12:52:02 PM UTC 24 Aug 29 12:52:04 PM UTC 24 29731993 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.524552543 Aug 29 12:51:46 PM UTC 24 Aug 29 12:52:05 PM UTC 24 410868236 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2258557281 Aug 29 12:52:04 PM UTC 24 Aug 29 12:52:06 PM UTC 24 176183635 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.470218680 Aug 29 12:51:52 PM UTC 24 Aug 29 12:52:07 PM UTC 24 4803715749 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.2346050267 Aug 29 12:52:02 PM UTC 24 Aug 29 12:52:08 PM UTC 24 241247849 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1193871274 Aug 29 12:51:39 PM UTC 24 Aug 29 12:52:09 PM UTC 24 637565486 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.195865702 Aug 29 12:52:09 PM UTC 24 Aug 29 12:52:11 PM UTC 24 31867632 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1558776820 Aug 29 12:52:07 PM UTC 24 Aug 29 12:52:13 PM UTC 24 191675113 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.1080541021 Aug 29 12:52:07 PM UTC 24 Aug 29 12:52:16 PM UTC 24 74114907 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2339706444 Aug 29 12:51:59 PM UTC 24 Aug 29 12:52:16 PM UTC 24 886735237 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.854503567 Aug 29 12:51:59 PM UTC 24 Aug 29 12:52:16 PM UTC 24 272365171 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3191572017 Aug 29 12:51:59 PM UTC 24 Aug 29 12:52:17 PM UTC 24 1773614647 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.197919928 Aug 29 12:52:37 PM UTC 24 Aug 29 12:52:48 PM UTC 24 4161139230 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1797721703 Aug 29 12:51:51 PM UTC 24 Aug 29 12:52:17 PM UTC 24 549290610 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2273659603 Aug 29 12:51:59 PM UTC 24 Aug 29 12:52:18 PM UTC 24 1232506059 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3873041828 Aug 29 12:52:10 PM UTC 24 Aug 29 12:52:18 PM UTC 24 167859982 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.1760128770 Aug 29 12:52:08 PM UTC 24 Aug 29 12:52:20 PM UTC 24 294532876 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2418451295 Aug 29 12:52:07 PM UTC 24 Aug 29 12:52:20 PM UTC 24 441709428 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1752057021 Aug 29 12:52:08 PM UTC 24 Aug 29 12:52:21 PM UTC 24 249926934 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2933181033 Aug 29 12:52:17 PM UTC 24 Aug 29 12:52:22 PM UTC 24 69578527 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3987155824 Aug 29 12:52:21 PM UTC 24 Aug 29 12:52:23 PM UTC 24 112139954 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1593901290 Aug 29 12:51:28 PM UTC 24 Aug 29 12:52:24 PM UTC 24 1866744406 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1097247036 Aug 29 12:51:43 PM UTC 24 Aug 29 12:52:24 PM UTC 24 1256179045 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.3861247720 Aug 29 12:52:17 PM UTC 24 Aug 29 12:52:24 PM UTC 24 281673637 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3331450374 Aug 29 12:52:22 PM UTC 24 Aug 29 12:52:25 PM UTC 24 38054765 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1556935242 Aug 29 12:52:19 PM UTC 24 Aug 29 12:52:27 PM UTC 24 657846085 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3928946833 Aug 29 12:52:12 PM UTC 24 Aug 29 12:52:28 PM UTC 24 413204745 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.2721590222 Aug 29 12:52:25 PM UTC 24 Aug 29 12:52:28 PM UTC 24 192216139 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.530811211 Aug 29 12:52:28 PM UTC 24 Aug 29 12:52:30 PM UTC 24 19618022 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1633794632 Aug 29 12:52:19 PM UTC 24 Aug 29 12:52:33 PM UTC 24 518567954 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.4077870064 Aug 29 12:52:17 PM UTC 24 Aug 29 12:52:33 PM UTC 24 1546806033 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.3663215612 Aug 29 12:52:29 PM UTC 24 Aug 29 12:52:35 PM UTC 24 452214721 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.45354228 Aug 29 12:51:51 PM UTC 24 Aug 29 12:52:36 PM UTC 24 2276541916 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1062806958 Aug 29 12:52:24 PM UTC 24 Aug 29 12:52:36 PM UTC 24 123329853 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.3665817468 Aug 29 12:52:34 PM UTC 24 Aug 29 12:52:38 PM UTC 24 51464138 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.4279780777 Aug 29 12:52:22 PM UTC 24 Aug 29 12:52:38 PM UTC 24 192188689 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1883785695 Aug 29 12:52:25 PM UTC 24 Aug 29 12:52:39 PM UTC 24 254734744 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.498928015 Aug 29 12:52:14 PM UTC 24 Aug 29 12:52:39 PM UTC 24 772570052 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3616568985 Aug 29 12:52:41 PM UTC 24 Aug 29 12:52:43 PM UTC 24 73035488 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3287700708 Aug 29 12:52:05 PM UTC 24 Aug 29 12:52:40 PM UTC 24 1034107910 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.1302836319 Aug 29 12:52:34 PM UTC 24 Aug 29 12:52:40 PM UTC 24 276152343 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2512170208 Aug 29 12:52:00 PM UTC 24 Aug 29 12:52:40 PM UTC 24 822025878 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.3455931208 Aug 29 12:52:22 PM UTC 24 Aug 29 12:52:42 PM UTC 24 198838308 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1470563769 Aug 29 12:52:25 PM UTC 24 Aug 29 12:52:42 PM UTC 24 3428781051 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.3076788546 Aug 29 12:52:39 PM UTC 24 Aug 29 12:52:42 PM UTC 24 29780894 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3672828848 Aug 29 12:52:41 PM UTC 24 Aug 29 12:52:45 PM UTC 24 266668100 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.203327996 Aug 29 12:51:31 PM UTC 24 Aug 29 12:52:43 PM UTC 24 12728959815 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2445451194 Aug 29 12:52:17 PM UTC 24 Aug 29 12:52:43 PM UTC 24 14877079450 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.3347886041 Aug 29 12:52:26 PM UTC 24 Aug 29 12:52:44 PM UTC 24 483401690 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.3606084993 Aug 29 12:52:44 PM UTC 24 Aug 29 12:52:46 PM UTC 24 34030562 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.949487626 Aug 29 12:52:38 PM UTC 24 Aug 29 12:52:49 PM UTC 24 2555783801 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.3617817671 Aug 29 12:52:44 PM UTC 24 Aug 29 12:52:49 PM UTC 24 1877529678 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.3109267649 Aug 29 12:52:31 PM UTC 24 Aug 29 12:52:53 PM UTC 24 416528416 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1190613104 Aug 29 12:52:41 PM UTC 24 Aug 29 12:52:54 PM UTC 24 83053257 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2220859011 Aug 29 12:52:49 PM UTC 24 Aug 29 12:52:54 PM UTC 24 1222716968 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2007004550 Aug 29 12:52:46 PM UTC 24 Aug 29 12:52:55 PM UTC 24 2246608984 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1759015242 Aug 29 12:52:31 PM UTC 24 Aug 29 12:52:56 PM UTC 24 1879593124 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.3160684057 Aug 29 12:52:44 PM UTC 24 Aug 29 12:52:56 PM UTC 24 1500798057 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.3391047196 Aug 29 12:52:49 PM UTC 24 Aug 29 12:52:56 PM UTC 24 747895192 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.4109573765 Aug 29 12:52:21 PM UTC 24 Aug 29 12:52:57 PM UTC 24 211307795 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.158825116 Aug 29 12:52:55 PM UTC 24 Aug 29 12:52:57 PM UTC 24 32349770 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.70039611 Aug 29 12:52:37 PM UTC 24 Aug 29 12:52:59 PM UTC 24 453210575 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.528319644 Aug 29 12:52:57 PM UTC 24 Aug 29 12:52:59 PM UTC 24 14125925 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3252542715 Aug 29 12:52:44 PM UTC 24 Aug 29 12:53:01 PM UTC 24 407640016 ps
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T266 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.951018056 Aug 29 12:52:44 PM UTC 24 Aug 29 12:53:02 PM UTC 24 300503738 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.3070289857 Aug 29 12:52:58 PM UTC 24 Aug 29 12:53:02 PM UTC 24 109895098 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1626101707 Aug 29 12:52:45 PM UTC 24 Aug 29 12:53:03 PM UTC 24 267667189 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.63073713 Aug 29 12:53:02 PM UTC 24 Aug 29 12:53:04 PM UTC 24 30315188 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.4215418183 Aug 29 12:52:34 PM UTC 24 Aug 29 12:53:05 PM UTC 24 1518784653 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.884822556 Aug 29 12:52:50 PM UTC 24 Aug 29 12:53:07 PM UTC 24 2017330979 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.161288283 Aug 29 12:52:37 PM UTC 24 Aug 29 12:53:07 PM UTC 24 3562076250 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.1494254119 Aug 29 12:52:50 PM UTC 24 Aug 29 12:53:07 PM UTC 24 235658095 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.1984391718 Aug 29 12:52:57 PM UTC 24 Aug 29 12:53:08 PM UTC 24 189511398 ps
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T273 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1517263926 Aug 29 12:52:52 PM UTC 24 Aug 29 12:53:12 PM UTC 24 6809984554 ps
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T274 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1706337132 Aug 29 12:52:58 PM UTC 24 Aug 29 12:53:15 PM UTC 24 1993497188 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.545759199 Aug 29 12:53:03 PM UTC 24 Aug 29 12:53:15 PM UTC 24 1719121975 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.849543621 Aug 29 12:53:04 PM UTC 24 Aug 29 12:53:15 PM UTC 24 1356116276 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3273626925 Aug 29 12:52:49 PM UTC 24 Aug 29 12:53:16 PM UTC 24 5011843585 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3197167971 Aug 29 12:53:13 PM UTC 24 Aug 29 12:53:16 PM UTC 24 45300713 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.245228237 Aug 29 12:53:13 PM UTC 24 Aug 29 12:53:16 PM UTC 24 47779736 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.1057322718 Aug 29 12:53:05 PM UTC 24 Aug 29 12:53:17 PM UTC 24 1163226215 ps
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T281 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3817738905 Aug 29 12:53:18 PM UTC 24 Aug 29 12:53:20 PM UTC 24 41553025 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2658349032 Aug 29 12:53:06 PM UTC 24 Aug 29 12:53:21 PM UTC 24 8552274305 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.982751747 Aug 29 12:53:17 PM UTC 24 Aug 29 12:53:21 PM UTC 24 450870848 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1820222727 Aug 29 12:53:08 PM UTC 24 Aug 29 12:53:21 PM UTC 24 368313253 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.1477628547 Aug 29 12:53:00 PM UTC 24 Aug 29 12:53:21 PM UTC 24 410785785 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2536626886 Aug 29 12:52:41 PM UTC 24 Aug 29 12:53:22 PM UTC 24 1407584258 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.2343042841 Aug 29 12:53:08 PM UTC 24 Aug 29 12:53:23 PM UTC 24 1780121200 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.4123255799 Aug 29 12:52:11 PM UTC 24 Aug 29 12:53:24 PM UTC 24 7784283209 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2729972640 Aug 29 12:52:44 PM UTC 24 Aug 29 12:53:24 PM UTC 24 1523321736 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2026662551 Aug 29 12:53:21 PM UTC 24 Aug 29 12:53:26 PM UTC 24 480391068 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.879497810 Aug 29 12:53:18 PM UTC 24 Aug 29 12:53:26 PM UTC 24 467591402 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3204653296 Aug 29 12:53:16 PM UTC 24 Aug 29 12:53:27 PM UTC 24 143264479 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.4122511939 Aug 29 12:53:03 PM UTC 24 Aug 29 12:53:27 PM UTC 24 2361094198 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1750546473 Aug 29 12:53:27 PM UTC 24 Aug 29 12:53:29 PM UTC 24 19977537 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1280240488 Aug 29 12:53:27 PM UTC 24 Aug 29 12:53:30 PM UTC 24 15978195 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.1088640721 Aug 29 12:53:08 PM UTC 24 Aug 29 12:53:31 PM UTC 24 3982625109 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.229301751 Aug 29 12:51:38 PM UTC 24 Aug 29 12:53:45 PM UTC 24 8467911454 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.781394605 Aug 29 12:53:27 PM UTC 24 Aug 29 12:53:31 PM UTC 24 30536058 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.3643777408 Aug 29 12:53:17 PM UTC 24 Aug 29 12:53:32 PM UTC 24 213137624 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1841280170 Aug 29 12:53:17 PM UTC 24 Aug 29 12:53:33 PM UTC 24 275547089 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3929992590 Aug 29 12:53:19 PM UTC 24 Aug 29 12:53:34 PM UTC 24 284533006 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2724451119 Aug 29 12:53:31 PM UTC 24 Aug 29 12:53:34 PM UTC 24 21065782 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.267279057 Aug 29 12:52:55 PM UTC 24 Aug 29 12:53:34 PM UTC 24 1648182758 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.1728299965 Aug 29 12:51:59 PM UTC 24 Aug 29 12:53:35 PM UTC 24 4141017561 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.4002136836 Aug 29 12:52:47 PM UTC 24 Aug 29 12:53:35 PM UTC 24 3347730131 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1174703187 Aug 29 12:52:57 PM UTC 24 Aug 29 12:53:36 PM UTC 24 1318014144 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.2969278326 Aug 29 12:53:17 PM UTC 24 Aug 29 12:53:36 PM UTC 24 1212155578 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.262389096 Aug 29 12:53:24 PM UTC 24 Aug 29 12:53:36 PM UTC 24 225355143 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1785036526 Aug 29 12:53:34 PM UTC 24 Aug 29 12:53:36 PM UTC 24 13837804 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2672703023 Aug 29 12:53:24 PM UTC 24 Aug 29 12:53:37 PM UTC 24 276997132 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3351330062 Aug 29 12:53:24 PM UTC 24 Aug 29 12:53:39 PM UTC 24 263536757 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.669930674 Aug 29 12:53:22 PM UTC 24 Aug 29 12:53:39 PM UTC 24 1403985510 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1386376162 Aug 29 12:53:07 PM UTC 24 Aug 29 12:53:39 PM UTC 24 2966024546 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.590084168 Aug 29 12:53:30 PM UTC 24 Aug 29 12:53:41 PM UTC 24 336821897 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2057831969 Aug 29 12:53:34 PM UTC 24 Aug 29 12:53:41 PM UTC 24 386438084 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.2748180747 Aug 29 12:53:40 PM UTC 24 Aug 29 12:53:43 PM UTC 24 155855153 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3041368328 Aug 29 12:52:29 PM UTC 24 Aug 29 12:53:43 PM UTC 24 14027484237 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1136727860 Aug 29 12:53:22 PM UTC 24 Aug 29 12:53:43 PM UTC 24 2670067858 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1473059468 Aug 29 12:53:32 PM UTC 24 Aug 29 12:53:43 PM UTC 24 224928488 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.3720985341 Aug 29 12:53:36 PM UTC 24 Aug 29 12:53:44 PM UTC 24 696067031 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3678847589 Aug 29 12:53:38 PM UTC 24 Aug 29 12:53:44 PM UTC 24 3450056333 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2265044256 Aug 29 12:53:43 PM UTC 24 Aug 29 12:53:45 PM UTC 24 18272878 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1751336561 Aug 29 12:53:36 PM UTC 24 Aug 29 12:53:46 PM UTC 24 6452151803 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.3877968704 Aug 29 12:53:41 PM UTC 24 Aug 29 12:53:47 PM UTC 24 124502661 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2306241244 Aug 29 12:53:45 PM UTC 24 Aug 29 12:53:47 PM UTC 24 13942896 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1391434355 Aug 29 12:53:44 PM UTC 24 Aug 29 12:53:48 PM UTC 24 92479783 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.4251310445 Aug 29 12:53:33 PM UTC 24 Aug 29 12:53:49 PM UTC 24 475426175 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.2225207803 Aug 29 12:53:15 PM UTC 24 Aug 29 12:53:50 PM UTC 24 1534739159 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1465022773 Aug 29 12:53:23 PM UTC 24 Aug 29 12:53:50 PM UTC 24 914105286 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1916824042 Aug 29 12:53:32 PM UTC 24 Aug 29 12:53:51 PM UTC 24 1559523417 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1237998151 Aug 29 12:53:47 PM UTC 24 Aug 29 12:53:51 PM UTC 24 315192354 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.244418666 Aug 29 12:53:40 PM UTC 24 Aug 29 12:53:52 PM UTC 24 568806601 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1876770909 Aug 29 12:53:38 PM UTC 24 Aug 29 12:53:52 PM UTC 24 5093041976 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2647487088 Aug 29 12:53:39 PM UTC 24 Aug 29 12:53:53 PM UTC 24 477293494 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1391282656 Aug 29 12:53:38 PM UTC 24 Aug 29 12:53:54 PM UTC 24 4699561811 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.776299276 Aug 29 12:53:45 PM UTC 24 Aug 29 12:53:55 PM UTC 24 383817497 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.2192819993 Aug 29 12:53:44 PM UTC 24 Aug 29 12:53:56 PM UTC 24 486656335 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.825954001 Aug 29 12:53:54 PM UTC 24 Aug 29 12:53:56 PM UTC 24 13092866 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3058030245 Aug 29 12:53:29 PM UTC 24 Aug 29 12:53:56 PM UTC 24 1054166011 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.79277551 Aug 29 12:53:45 PM UTC 24 Aug 29 12:53:56 PM UTC 24 1791012792 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.724378343 Aug 29 12:53:54 PM UTC 24 Aug 29 12:53:56 PM UTC 24 24670278 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.1180558676 Aug 29 12:53:38 PM UTC 24 Aug 29 12:53:57 PM UTC 24 1144073235 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.3468229645 Aug 29 12:53:54 PM UTC 24 Aug 29 12:53:58 PM UTC 24 33928133 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.539372850 Aug 29 12:53:48 PM UTC 24 Aug 29 12:54:00 PM UTC 24 294237701 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.1210886525 Aug 29 12:53:57 PM UTC 24 Aug 29 12:54:00 PM UTC 24 33976186 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.3793687556 Aug 29 12:53:56 PM UTC 24 Aug 29 12:54:00 PM UTC 24 89081557 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2157908551 Aug 29 12:53:44 PM UTC 24 Aug 29 12:54:00 PM UTC 24 437451661 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.3259913898 Aug 29 12:53:03 PM UTC 24 Aug 29 12:54:00 PM UTC 24 1132341604 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.2631284858 Aug 29 12:53:51 PM UTC 24 Aug 29 12:54:01 PM UTC 24 339415227 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1109579989 Aug 29 12:53:19 PM UTC 24 Aug 29 12:54:01 PM UTC 24 2024299401 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1522318675 Aug 29 12:53:44 PM UTC 24 Aug 29 12:54:02 PM UTC 24 5491050310 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.842342060 Aug 29 12:53:51 PM UTC 24 Aug 29 12:54:03 PM UTC 24 297679727 ps
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T334 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.152422602 Aug 29 12:53:50 PM UTC 24 Aug 29 12:54:04 PM UTC 24 447440678 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.1752789923 Aug 29 12:52:16 PM UTC 24 Aug 29 12:54:04 PM UTC 24 3079749448 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.4064909837 Aug 29 12:53:55 PM UTC 24 Aug 29 12:54:07 PM UTC 24 131403516 ps
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T338 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3568539131 Aug 29 12:54:05 PM UTC 24 Aug 29 12:54:07 PM UTC 24 20240447 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3606762642 Aug 29 12:54:01 PM UTC 24 Aug 29 12:54:08 PM UTC 24 127366056 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3610743696 Aug 29 12:53:43 PM UTC 24 Aug 29 12:54:08 PM UTC 24 159292338 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.790457510 Aug 29 12:53:47 PM UTC 24 Aug 29 12:54:10 PM UTC 24 3951796174 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.302641517 Aug 29 12:54:20 PM UTC 24 Aug 29 12:54:33 PM UTC 24 597258413 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.136185202 Aug 29 12:53:57 PM UTC 24 Aug 29 12:54:10 PM UTC 24 228582569 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4022189464 Aug 29 12:54:08 PM UTC 24 Aug 29 12:54:11 PM UTC 24 11240122 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.2415632938 Aug 29 12:53:56 PM UTC 24 Aug 29 12:54:12 PM UTC 24 748243609 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1953031529 Aug 29 12:54:10 PM UTC 24 Aug 29 12:54:13 PM UTC 24 28631416 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.572935079 Aug 29 12:53:57 PM UTC 24 Aug 29 12:54:14 PM UTC 24 1075238324 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1998960074 Aug 29 12:54:03 PM UTC 24 Aug 29 12:54:17 PM UTC 24 1439832784 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1389433082 Aug 29 12:54:03 PM UTC 24 Aug 29 12:54:17 PM UTC 24 1628289728 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.1348367455 Aug 29 12:53:36 PM UTC 24 Aug 29 12:54:18 PM UTC 24 5116541512 ps
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T158 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1460328597 Aug 29 12:54:22 PM UTC 24 Aug 29 12:54:44 PM UTC 24 228956381 ps
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