Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61182821

1

T1

1158

T2

5153

T3

1009

auto[1]

1121103

1

T4

693

T5

99

T11

392

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61169153

1

T1

1158

T2

5153

T3

1009

auto[1]

1134771

1

T4

495

T5

99

T11

490

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5313058	1			T1	90		T2	1776		T3	105
auto[IdleSt]	15152046	1			T1	170		T2	1782		T3	904
auto[ClkMuxSt]	28323	1			T1	1		T2	20		T4	12
auto[CntIncrSt]	28107	1			T1	1		T2	20		T4	12
auto[CntProgSt]	1196504	1			T1	2		T2	40		T4	348
auto[TransCheckSt]	22450	1			T1	1		T2	20		T5	6
auto[TokenHashSt]	20165556	1			T1	113		T2	382		T5	277
auto[FlashRmaSt]	28781	1			T1	1		T2	39		T5	6
auto[TokenCheck0St]	10301	1			T1	1		T2	20		T5	6
auto[TokenCheck1St]	7561	1			T1	1		T2	20		T5	6
auto[TransProgSt]	317288	1			T1	2		T2	40		T5	12
auto[PostTransSt]	8644756	1			T1	775		T2	994		T4	944
auto[ScrapSt]	156162	1			T15	20		T12	551		T46	783
auto[EscalateSt]	4487817	1			T4	1659		T5	485		T11	3741
auto[InvalidSt]	6743793	1			T5	253		T17	2148		T45	7735

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1421	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6743793	1			T5	253		T17	2148		T45	7735
EscalateSt	4487817	1			T4	1659		T5	485		T11	3741
ScrapSt	156162	1			T15	20		T12	551		T46	783
PostTransSt	8644756	1			T1	775		T2	994		T4	944
TransProgSt	317288	1			T1	2		T2	40		T5	12
TokenCheck1St	7561	1			T1	1		T2	20		T5	6
TokenCheck0St	10301	1			T1	1		T2	20		T5	6
FlashRmaSt	28781	1			T1	1		T2	39		T5	6
TokenHashSt	20165556	1			T1	113		T2	382		T5	277
TransCheckSt	22450	1			T1	1		T2	20		T5	6
CntProgSt	1196504	1			T1	2		T2	40		T4	348
CntIncrSt	28107	1			T1	1		T2	20		T4	12
ClkMuxSt	28323	1			T1	1		T2	20		T4	12
IdleSt	15152046	1			T1	170		T2	1782		T3	904
ResetSt	5313058	1			T1	90		T2	1776		T3	105
arcs[ResetSt=>IdleSt]	41803	1			T1	1		T2	20		T3	1
arcs[IdleSt=>ScrapSt]	245	1			T15	5		T12	1		T46	1
arcs[IdleSt=>ClkMuxSt]	28149	1			T1	1		T2	20		T4	12
arcs[ClkMuxSt=>CntIncrSt]	28107	1			T1	1		T2	20		T4	12
arcs[CntIncrSt=>PostTransSt]	1150	1			T14	12		T43	12		T44	11
arcs[CntIncrSt=>CntProgSt]	26887	1			T1	1		T2	20		T4	12
arcs[CntProgSt=>PostTransSt]	3434	1			T4	12		T11	9		T14	5
arcs[CntProgSt=>TransCheckSt]	22450	1			T1	1		T2	20		T5	6
arcs[TransCheckSt=>PostTransSt]	3105	1			T14	8		T16	36		T43	12
arcs[TransCheckSt=>TokenHashSt]	19224	1			T1	1		T2	20		T5	6
arcs[TokenHashSt=>PostTransSt]	8077	1			T14	23		T16	4		T17	5
arcs[TokenHashSt=>FlashRmaSt]	10341	1			T1	1		T2	20		T5	6
arcs[FlashRmaSt=>TokenCheck0St]	10301	1			T1	1		T2	20		T5	6
arcs[TokenCheck0St=>PostTransSt]	2687	1			T14	3		T16	11		T17	15
arcs[TokenCheck0St=>TokenCheck1St]	7561	1			T1	1		T2	20		T5	6
arcs[TokenCheck1St=>PostTransSt]	583	1			T14	5		T16	9		T48	4
arcs[TransProgSt=>PostTransSt]	6179	1			T1	1		T2	20		T5	6
arcs[IdleSt=>EscalateSt]	186	1			T15	8		T40	6		T58	6
arcs[ClkMuxSt=>EscalateSt]	42	1			T40	1		T58	1		T59	2
arcs[CntIncrSt=>EscalateSt]	70	1			T41	3		T58	2		T60	1
arcs[CntProgSt=>EscalateSt]	1003	1			T15	26		T40	3		T41	32
arcs[TransCheckSt=>EscalateSt]	121	1			T15	1		T40	6		T41	1
arcs[TokenHashSt=>EscalateSt]	806	1			T15	11		T40	17		T41	8
arcs[FlashRmaSt=>EscalateSt]	40	1			T58	1		T61	1		T62	1
arcs[TokenCheck0St=>EscalateSt]	53	1			T40	1		T58	1		T60	2
arcs[TokenCheck1St=>EscalateSt]	36	1			T58	3		T60	1		T61	2
arcs[TransProgSt=>EscalateSt]	763	1			T15	30		T40	6		T41	18
arcs[PostTransSt=>EscalateSt]	3782	1			T4	12		T11	9		T14	5
arcs[InvalidSt=>EscalateSt]	9783	1			T5	2		T17	11		T45	56

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5312875	1			T1	90		T2	1776		T3	105
auto[0]	auto[IdleSt]	15151923	1			T1	170		T2	1782		T3	904
auto[0]	auto[ClkMuxSt]	28298	1			T1	1		T2	20		T4	12
auto[0]	auto[CntIncrSt]	28065	1			T1	1		T2	20		T4	12
auto[0]	auto[CntProgSt]	1195836	1			T1	2		T2	40		T4	348
auto[0]	auto[TransCheckSt]	22375	1			T1	1		T2	20		T5	6
auto[0]	auto[TokenHashSt]	20165027	1			T1	113		T2	382		T5	277
auto[0]	auto[FlashRmaSt]	28751	1			T1	1		T2	39		T5	6
auto[0]	auto[TokenCheck0St]	10263	1			T1	1		T2	20		T5	6
auto[0]	auto[TokenCheck1St]	7537	1			T1	1		T2	20		T5	6
auto[0]	auto[TransProgSt]	316775	1			T1	2		T2	40		T5	12
auto[0]	auto[PostTransSt]	8642863	1			T1	775		T2	994		T4	937
auto[0]	auto[ScrapSt]	156115	1			T15	18		T12	551		T46	783
auto[0]	auto[EscalateSt]	3375762	1			T4	973		T5	387		T11	3353
auto[0]	auto[InvalidSt]	6738935	1			T5	252		T17	2141		T45	7704
auto[1]	auto[ResetSt]	183	1			T15	5		T40	2		T41	4
auto[1]	auto[IdleSt]	123	1			T15	7		T40	3		T58	4
auto[1]	auto[ClkMuxSt]	25	1			T58	1		T59	1		T61	1
auto[1]	auto[CntIncrSt]	42	1			T41	3		T58	2		T59	1
auto[1]	auto[CntProgSt]	668	1			T15	19		T40	2		T41	21
auto[1]	auto[TransCheckSt]	75	1			T40	3		T41	1		T58	4
auto[1]	auto[TokenHashSt]	529	1			T15	9		T40	11		T41	7
auto[1]	auto[FlashRmaSt]	30	1			T58	1		T61	1		T62	1
auto[1]	auto[TokenCheck0St]	38	1			T58	1		T60	2		T59	2
auto[1]	auto[TokenCheck1St]	24	1			T58	1		T60	1		T61	1
auto[1]	auto[TransProgSt]	513	1			T15	18		T40	3		T41	14
auto[1]	auto[PostTransSt]	1893	1			T4	7		T11	4		T14	2
auto[1]	auto[ScrapSt]	47	1			T15	2		T40	1		T41	1
auto[1]	auto[EscalateSt]	1112055	1			T4	686		T5	98		T11	388
auto[1]	auto[InvalidSt]	4858	1			T5	1		T17	7		T45	31

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5312881	1			T1	90		T2	1776		T3	105
auto[0]	auto[IdleSt]	15151914	1			T1	170		T2	1782		T3	904
auto[0]	auto[ClkMuxSt]	28287	1			T1	1		T2	20		T4	12
auto[0]	auto[CntIncrSt]	28063	1			T1	1		T2	20		T4	12
auto[0]	auto[CntProgSt]	1195854	1			T1	2		T2	40		T4	348
auto[0]	auto[TransCheckSt]	22376	1			T1	1		T2	20		T5	6
auto[0]	auto[TokenHashSt]	20165021	1			T1	113		T2	382		T5	277
auto[0]	auto[FlashRmaSt]	28759	1			T1	1		T2	39		T5	6
auto[0]	auto[TokenCheck0St]	10266	1			T1	1		T2	20		T5	6
auto[0]	auto[TokenCheck1St]	7536	1			T1	1		T2	20		T5	6
auto[0]	auto[TransProgSt]	316780	1			T1	2		T2	40		T5	12
auto[0]	auto[PostTransSt]	8642741	1			T1	775		T2	994		T4	939
auto[0]	auto[ScrapSt]	156114	1			T15	15		T12	551		T46	783
auto[0]	auto[EscalateSt]	3362272	1			T4	1169		T5	387		T11	3256
auto[0]	auto[InvalidSt]	6738868	1			T5	252		T17	2144		T45	7710
auto[1]	auto[ResetSt]	177	1			T15	6		T40	2		T41	5
auto[1]	auto[IdleSt]	132	1			T15	7		T40	4		T58	5
auto[1]	auto[ClkMuxSt]	36	1			T40	1		T58	1		T59	2
auto[1]	auto[CntIncrSt]	44	1			T41	1		T58	2		T60	1
auto[1]	auto[CntProgSt]	650	1			T15	16		T40	2		T41	21
auto[1]	auto[TransCheckSt]	74	1			T15	1		T40	5		T41	1
auto[1]	auto[TokenHashSt]	535	1			T15	5		T40	10		T41	6
auto[1]	auto[FlashRmaSt]	22	1			T58	1		T61	1		T219	1
auto[1]	auto[TokenCheck0St]	35	1			T40	1		T219	1		T220	1
auto[1]	auto[TokenCheck1St]	25	1			T58	2		T61	2		T221	3
auto[1]	auto[TransProgSt]	508	1			T15	20		T40	5		T41	10
auto[1]	auto[PostTransSt]	2015	1			T4	5		T11	5		T14	3
auto[1]	auto[ScrapSt]	48	1			T15	5		T41	2		T58	1
auto[1]	auto[EscalateSt]	1125545	1			T4	490		T5	98		T11	485
auto[1]	auto[InvalidSt]	4925	1			T5	1		T17	4		T45	25