Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.95 98.04 95.77 93.40 97.67 98.76 98.76 96.29


Total tests in report: 1001
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.15 60.15 80.53 80.53 49.68 49.68 57.88 57.88 34.88 34.88 74.90 74.90 91.54 91.54 31.63 31.63 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.4226760930
71.13 10.98 87.68 7.14 76.87 27.18 74.24 16.36 39.53 4.65 83.40 8.51 94.28 2.74 41.87 10.25 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1748913334
79.38 8.26 89.19 1.51 79.21 2.34 82.69 8.45 58.14 18.60 89.63 6.22 94.28 0.00 62.54 20.67 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.856215533
84.90 5.52 89.34 0.15 79.48 0.27 82.69 0.00 88.37 30.23 90.46 0.83 94.53 0.25 69.43 6.89 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3082570447
87.28 2.38 95.82 6.49 80.56 1.08 83.99 1.30 88.37 0.00 93.15 2.70 94.53 0.00 74.56 5.12 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3584334132
88.66 1.37 95.82 0.00 80.74 0.18 88.04 4.05 88.37 0.00 93.78 0.62 94.53 0.00 79.33 4.77 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3151261099
89.86 1.20 96.43 0.60 83.80 3.06 88.20 0.16 88.37 0.00 94.61 0.83 95.27 0.75 82.33 3.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2726713996
90.96 1.10 96.53 0.10 85.15 1.35 88.24 0.04 88.37 0.00 95.23 0.62 96.27 1.00 86.93 4.59 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.305148900
91.78 0.82 96.63 0.10 85.96 0.81 88.64 0.40 90.70 2.33 95.85 0.62 96.52 0.25 88.16 1.24 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.3296423398
92.59 0.81 97.13 0.50 87.58 1.62 88.65 0.01 93.02 2.33 96.89 1.04 96.52 0.00 88.34 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1741764349
93.19 0.60 97.13 0.00 88.66 1.08 89.77 1.11 93.02 0.00 96.89 0.00 96.77 0.25 90.11 1.77 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.427857984
93.60 0.41 97.28 0.15 89.92 1.26 89.77 0.00 93.02 0.00 97.30 0.41 96.77 0.00 91.17 1.06 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1238794107
94.00 0.39 97.38 0.10 90.10 0.18 90.22 0.46 93.02 0.00 97.72 0.41 96.77 0.00 92.76 1.59 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3857880868
94.37 0.37 97.38 0.00 90.10 0.00 90.51 0.28 95.35 2.33 97.72 0.00 96.77 0.00 92.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1877407412
94.74 0.37 97.43 0.05 90.10 0.00 90.51 0.00 97.67 2.33 97.93 0.21 96.77 0.00 92.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1970869502
95.03 0.29 97.43 0.00 90.19 0.09 91.24 0.73 97.67 0.00 97.93 0.00 96.77 0.00 93.99 1.24 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.771454318
95.24 0.21 97.43 0.00 90.19 0.00 91.24 0.00 97.67 0.00 97.93 0.00 98.26 1.49 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2282702253
95.44 0.20 97.79 0.35 91.09 0.90 91.37 0.13 97.67 0.00 97.93 0.00 98.26 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2225661820
95.63 0.19 97.79 0.00 91.27 0.18 92.52 1.15 97.67 0.00 97.93 0.00 98.26 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.902362603
95.79 0.15 97.79 0.00 92.17 0.90 92.52 0.00 97.67 0.00 97.93 0.00 98.26 0.00 94.17 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1113627159
95.93 0.15 97.84 0.05 92.44 0.27 92.66 0.14 97.67 0.00 98.13 0.21 98.26 0.00 94.52 0.35 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2451592750
96.06 0.13 97.84 0.00 92.80 0.36 92.66 0.00 97.67 0.00 98.13 0.00 98.26 0.00 95.05 0.53 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3942962095
96.16 0.10 97.94 0.10 92.80 0.00 92.72 0.06 97.67 0.00 98.34 0.21 98.26 0.00 95.41 0.35 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2187931446
96.25 0.09 97.94 0.00 93.43 0.63 92.72 0.00 97.67 0.00 98.34 0.00 98.26 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.781843252
96.33 0.07 97.94 0.00 93.43 0.00 93.23 0.51 97.67 0.00 98.34 0.00 98.26 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.4105765916
96.40 0.07 97.94 0.00 93.43 0.00 93.23 0.00 97.67 0.00 98.34 0.00 98.76 0.50 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2126554945
96.46 0.06 98.04 0.10 93.52 0.09 93.25 0.02 97.67 0.00 98.55 0.21 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2353757732
96.50 0.04 98.04 0.00 93.79 0.27 93.28 0.03 97.67 0.00 98.55 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2191326723
96.54 0.04 98.04 0.00 94.06 0.27 93.28 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3179799964
96.58 0.04 98.04 0.00 94.33 0.27 93.28 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.450449290
96.61 0.04 98.04 0.00 94.60 0.27 93.28 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1492560554
96.65 0.04 98.04 0.00 94.87 0.27 93.28 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1349246584
96.69 0.04 98.04 0.00 94.96 0.09 93.28 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.97554828
96.72 0.03 98.04 0.00 94.96 0.00 93.28 0.00 97.67 0.00 98.76 0.21 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1952529077
96.75 0.03 98.04 0.00 94.96 0.00 93.30 0.02 97.67 0.00 98.76 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3760207490
96.77 0.03 98.04 0.00 95.14 0.18 93.30 0.00 97.67 0.00 98.76 0.00 98.76 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.903152974
96.80 0.03 98.04 0.00 95.32 0.18 93.30 0.00 97.67 0.00 98.76 0.00 98.76 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3283082373
96.83 0.03 98.04 0.00 95.32 0.00 93.30 0.00 97.67 0.00 98.76 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.4226652047
96.85 0.03 98.04 0.00 95.32 0.00 93.30 0.00 97.67 0.00 98.76 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1510973544
96.88 0.03 98.04 0.00 95.32 0.00 93.30 0.00 97.67 0.00 98.76 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2676528865
96.89 0.01 98.04 0.00 95.32 0.00 93.39 0.09 97.67 0.00 98.76 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.4028001719
96.90 0.01 98.04 0.00 95.41 0.09 93.39 0.00 97.67 0.00 98.76 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3235140211
96.91 0.01 98.04 0.00 95.50 0.09 93.39 0.00 97.67 0.00 98.76 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3934791656
96.93 0.01 98.04 0.00 95.59 0.09 93.39 0.00 97.67 0.00 98.76 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3650477210
96.94 0.01 98.04 0.00 95.68 0.09 93.39 0.00 97.67 0.00 98.76 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2459500681
96.95 0.01 98.04 0.00 95.77 0.09 93.39 0.00 97.67 0.00 98.76 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2110745028
96.95 0.01 98.04 0.00 95.77 0.00 93.40 0.01 97.67 0.00 98.76 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3821663264

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2257442582
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1934620367
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4228274072
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3315116629
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1832791896
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.888659118
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2513526055
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.25708901
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4075921624
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2655477208
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.684771313
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1875350199
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2608463406
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.927365153
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1053742426
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2989764418
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.98158594
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3887832924
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.435005694
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.512529972
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3625167601
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1554675445
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1453648674
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.992325969
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.806906531
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2205275596
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1611899059
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1157748438
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.213350635
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.318882915
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3815518371
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2123925813
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1232822372
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2231836876
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1984630542
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1530891444
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2860549216
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1462461522
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2021067957
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.703677979
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2945564847
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1598134750
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1324748886
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3286276812
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1108438270
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3083200831
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1129878111
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2170657835
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2818038906
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2422337518
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2824918407
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2900291925
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3051513683
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1825533781
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3645865021
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4122036135
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1543186793
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3827458147
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4174897716
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1674142839
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2976541725
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1093626318
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3009881738
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2353510584
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.394550083
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3125602638
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1054748004
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2323541318
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4143052303
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3532410053
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3240879082
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3629387455
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2288588981
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1135375155
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3426951613
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.520358964
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3069639338
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2954084353
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2043228326
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.813959632
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4218121439
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4005153294
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.363970500
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4195908771
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2226219955
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.825980376
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3305888801
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3600577226
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2570313491
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3385731318
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3206842739
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.18563510
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2265755223
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3421564110
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2733332729
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2434097395
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2470685205
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2558903485
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.710675560
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.935710042
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3421942324
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2389542571
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3508804239
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1123566303
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4218097373
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3112835141
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1935934665
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1552418956
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.381373608
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1676932473
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2369850890
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.406488851
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3083716159
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.921286110
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1323539218
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.849983858
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4068294430
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2470305818
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2817027668
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.417861897
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3499519270
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2301776678
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3461832276
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2096884202
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1276070289
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1489424463
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1531231265
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1102067918
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1665434715
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1143971896
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.414369119
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1245582887
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3312489508
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.852615981
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.663858946
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1722595956
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2669289393
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2086331637
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.871252458
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4211772120
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3931264758
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1145459456
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.799829895
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2571997152
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3339717096
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4256719128
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.276054926
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.818466611
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1419179071
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1592691084
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2508050004
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1773676966
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3265548816
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4092221286
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3866393992
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3135406632
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1266606132
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3864353054
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2688269476
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2256773561
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.262862578
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3792862941
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1485601322
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1470684917
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3572318502
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3271095153
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3182202725
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3702277046
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3874010304
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.927564308
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1182342572
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1471341040
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.2730011344
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.42636551
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3530878273
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1905302074
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.2073002124
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3694379250
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.981016413
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1302179998
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1786223828
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.841028525
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2138833918
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3527471954
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2546709139
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1602823808
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3976193159
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.309327046
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2934595171
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3658090462
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.825053159
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.3182767950
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.814420135
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1306989710
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2763290773
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3816483111
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1963457990
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.3290342355
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.2356554114
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.4104410483
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3375039253
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3438864906
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.4253020013
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.2173055036
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3632088498
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3269961287
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2455241918
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.2311465039
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.1898921356
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.297831403
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.314827994
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1858807983
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3106212905
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.725437877
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.1481839950
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.1669110997
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2479259088
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.3292653975
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.3140262004
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2069719279
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2057527788
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1736739626
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.4232578884
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.665829425
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2555311010
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.4014280777
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.2337762837
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3623011442
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.291065233
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2360481784
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3714475044
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.3426533446
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.1414914771
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1389013908
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.35885946
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2892845832
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.414870151
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.426513662
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.116796389
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2683999296
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.2239758038
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.1655521964
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.2278675299
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.847496755
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3879845613
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.704806686
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.1835741953
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.1152241889
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1657923392
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.1069451682
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1146252438
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.4113070011
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2865029437
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.3697087713
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2345900358
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.43100233
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.1446801790
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.3287928448
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.30257131
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.181637610
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3474738141
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.3146752301
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.1097673687
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.1319045000
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.1025114785
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.1101642602
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2309239871
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.4194333706
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.701334504
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.1898223385
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.3834479478
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1698901278
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.3302044433
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.2902109166
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.1538957514
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.2152934501
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.375815199
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.151938528
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.577819802
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.140792005
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.3759149875
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.2716205389
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.3797267274
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.468842960
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3000720305
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.4121590747
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.4274925255
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3041165971
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.248798003
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.639020826
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3974668511
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.2050384978
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.596974605
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.2709209695
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.4036827069
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.650383616
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.3818365629
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3281912373
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.2329327503
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.826497093
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1108740721
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3212489141
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2531250044
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.4246759470
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1515920574
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.4039914654
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.629596600
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.1463860634
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3031705242
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.727545199
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.128289061
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.447552747
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.1814791284
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2964375932
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.223002057
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.942167894
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.1377976177
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.409994438
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.3083145182
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.2251931699
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3113155218
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.2067834644
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.3915351845
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.2661343582
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3709164264
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.805637845
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.4164458140
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.575505878
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.2736334273
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.1466184287
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.4076762623
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.1723606391
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.352720419
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.49683926
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2906800709
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.1406382077
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.555174469
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2328195700
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3142189020
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.2470249471
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3956433357
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.3347270654
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.713650515
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.2230625007
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.3352351151
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.2973856504
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.2821063126
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.4268105117
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.3590608400
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.1259315587
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.580000978
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3119109872
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.4147029004
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.1177712587
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.1056844040
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.3087811897
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1158104309
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3796041323
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3493560216
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.1040665458
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.1791170475
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.2198448493
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.140847835
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.487339419
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1767260008
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.3715572254
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.4208902908
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2738989761
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.1114035064
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.1438688739
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.1324996512
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.3652410546
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.1392840683
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.3384945345
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.4262516761
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2574242811
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3304389163
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1584795779
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1228170304
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.457609365
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3943660532
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2598238028
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.223152787
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1193290262
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.528567965
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.2940933650
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1723781963
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.687160376
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.366924854
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.425065886
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1140596036
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3261875710
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.963311329
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1790257880
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.2220896418
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3412487334
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.511484279
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.675733351
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.4007160498
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.2002039422
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.1847054766
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.3570486491
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.2510851562
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.2819479684
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1736421842
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.2211940319
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3770113039
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2074238335
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.2495070955
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.619743763
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.405109950
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.227938114
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.554417770
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1989439835
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.1920606905
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3985295332
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2584201984
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2491404950
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3567378927
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.3146682556
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.3515788306
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3386909354
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.2751094747
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.12651185
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1995383438
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.503795343
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2193090740
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1054551226
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.50691109
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.3243050316
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.2184190240
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.4119974077
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.3240652568
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.3362505857
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1722223193
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1624420402
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.1853868323
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1513833238
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2836894965
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3795082621
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3084651899
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1310417121
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.3310352622
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.951294549
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.1710533358
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.2724990559
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3179304452
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.440992252
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.2334712419
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.2777170683
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.3547136377
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1207318589
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.3664643872
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.112881570
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.1730459809
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.3099954067
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.763330251
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1650165840
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.2373291272
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.4211984209
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3255309242
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.1358747384
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.2468013400
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.660929588
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3054050010
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.925993651
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.3525617787
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1035078361
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.2512805914
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.305176018
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.3934516628
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.1805744977
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.3894464276
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.3980515150
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2690313526
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.1882368186
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.655682502
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.4237478411
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3968217933
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1191155432
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.1498409844
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.4011724086
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1884117816
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.4279574684
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.321591678
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2403290847
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.602494876
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.1818619832
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.3270748593
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.1505995460
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3286322560
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.604562737
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.644459740
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.2727844333
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.1618671275
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.1027033889
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.4249420923
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.2799687888
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.95356720
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.3513801878
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.3304492915
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.1787236602
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2542207114
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.2525891746
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.2397609405
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3483909825
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.596767820
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.4116561155
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.720333408
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3061802609
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.3490633888
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.3957544477
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3366141648
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.3254311209
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.2255140054
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.3448915985
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1321172668
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.3545693680
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.645870541
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1861637274
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3627601234
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.1104694805
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.314364218
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.4185634033
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.354102098
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3259967049
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.2854547371
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.3019747193
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.8421736
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.1394743706
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.2395219991
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2664737100
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.940604307
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.529689201
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.1048645594
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.2008616405
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2197498525
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.108161576
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2242253346
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1836635794
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1300886295
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2588013048
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.4277966067
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.3028857174
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1875219307
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.3296695774
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2535579282
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.139259773
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.3633563785
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3447997541
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.3567498173
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2070524480
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3580485278
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2717832871
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2755835333
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.4293261364
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.1644330916
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2212845424
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1366509921
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.2950417510
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3492611986
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3567367165
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2047986515
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.68445358
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.791039530
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.3479391343
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2099887091
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2427708944
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.2155427979
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3139500307
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.371107964
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.2791374054
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2857427066
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.2671743818
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.933936724
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.1764137034
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2037742894
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.2100551695
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.391069654
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1583286304
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.391820631
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3889174008
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2965474658
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.3997843602
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.1269810174
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.2885729060
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.2231653352
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.646775530
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3187798000
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3092664505
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3559977016
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.882202371
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.4054681307
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3130867205
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3716320144
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2198435850
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2725184302
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2758547553
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.2571201247
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1485860295
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1694614592
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2304344971
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.2732869051
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.3619893385
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3088614408
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.2354489498
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3739126883
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.1873148812
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2790563139
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.610203264
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.3168113917
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3122214035
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3634709866
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3795726802
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2882595733
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2301258886
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3467975620
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.1958743342
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.4014338621
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.2756100041
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.3692496791
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1380761340
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1499914547
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1214862641
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1808060558
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.1438825594
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.2619689225
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.607231742
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.2404279802
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.1957760878
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2554940275
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2228316191
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.4028148243
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2962118777
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2938567618
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.4179244490
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3152550831
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2814666739
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.85271606
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.3706257092
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.1165693725
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1117558527
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.2823005731
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.2117783301
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1754777185
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.1882455868
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.1809222665
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.2692520746
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1804085930
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.4141069043
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.2950640117
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3818218354
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.3320855965
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.4002458758
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2085089408
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.2939356410
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.3600353432
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.903384536
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.2595313018
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.2675051619
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1220041893
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.544915635
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.438323361
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.1300716485
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1481378307
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2938605672
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3014268462
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.1626817013
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3679464360
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1411321191
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2076858486
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1320660000
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.933272490
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3169085611
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2459191634
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2294007170
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1654973953
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1760494749
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.4119365968
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.645501829
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1284194694
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.453546254
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.2608282389
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.105404500
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2170876555
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.1500861663
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.414818530
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.4125198102
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.884269467
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2141497533
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3772945609
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.4076167032
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.1843766505
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2727328660
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1555860244
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.1697699722
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1135264213
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.4082952371
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1782175636
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1919270896
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1886104454
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1631930742
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.4133185979
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3074439323
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2190371303
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1111508899
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.4136775881
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3886412750
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1254632910
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.3658599534
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2762594774
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.165321055
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.2111743026
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.2889422224
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.1664156167
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2815280049
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.2650046851
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2723709303
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.341068596
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.985090377
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1550060301
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.1325597398
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2873168043
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.2319015191
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4251446245
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.927642422
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.3303096315
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2356884652
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.2608775478
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.2444001332
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.1557496712
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.1887566356
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.5827969
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1327072248
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.985778830
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.2532005719
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1826548077
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1020563644
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3513957255
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1892588203
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.418644728
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.2655224564
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1782847990
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.2944311426
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3154643861
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.2495239115
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.1745134667
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.3001026318
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.3459264429
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1202697224
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2617602681
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1997100211
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2401134418
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1011820741
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.205381749
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.879017494
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.3838590173
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3343266914
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.3483302933
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2647259235
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.455204568
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3132428183
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.1587274589
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.3015032478
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.885755847
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1031631847
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3159035013
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1583241849
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.1626157623
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.165800947
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2535033416
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.3538680753
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.351127363
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.1702006098
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1448151052
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.780869599
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3731451592
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3818795494
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2686942096
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.1117141144
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.204703856
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.3202764870
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1515207617
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.4220467234
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.4251458394
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3496014994
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.3106828057
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3421236968
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.2223184913
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.4253039736
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1181135717
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1200514527
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2541559461
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.3569018852
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.1296751601
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.848648853
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.4293670050
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1173125076
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.2558519326
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.1891324647
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.3679407650
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.3528513829
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2784387544
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3096359440
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.261930383
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.984674069
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.3006591021
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3739531260
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.663044587
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.1758068464
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.3787945784
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.3045450570
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.3741192744
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1184914073
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1032198481
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.1488903535
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.247646733
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1593464244
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3531426259
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.460411573
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.3870522231
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.4181882341
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.1353550420
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2431612956
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.2489461266
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1119429520
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1572684508
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.106248661
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2262787127
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.2839688846
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.3974192751
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.121353608
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3697251587
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.910856794
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.3979496535
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1708908234
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.3357077727
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.2547705978
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.2338221494
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.94849817
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.3147334172
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.418731627
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2768023945
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2737453234
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.829290616
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2133608167
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2580452019
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.443341360
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.530115631
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.798021440
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3598461574
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2355760679
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3071665904
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2587939331
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1153674283
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.4020976091
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2668864076
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.2689416147
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.1927260620
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.275138193
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2696155521
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.357793510
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.598332436
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.932982394
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2322539209
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.372414669
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.467587296
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.53401137
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.4210494827
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.1654265394
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.1742135167
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2924529030
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3703105181
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.3464567771
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.355963121
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3674789356
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3600523105
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.2970107424
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3367912574
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2113766902
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2888677253
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1456213058
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1692725349
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1560452810
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.1542259853
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.768717184
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2763651491
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.930305548
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.3326973513
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1886658086
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1143084798
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3673416800
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.259796939
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1424149869
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.490843207
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2676449050
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.4043209914
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.852397625
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.866011289
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1805921699
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2058490986
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.195210937
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3459763107
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.726401586
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3995292267
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3571574823
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3813203676
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.395123554
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3854775683
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3563170245
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.181291285
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.586859963
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3959534434
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2409227420
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3143724938
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1691168743
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.256238113
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1626132620
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.368212003
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3813991513
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.740248254
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.1469673688
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.666675984
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1770819650
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3448828778
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.526847
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2003321151
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.2197358070
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.781842333
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1418749457
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4111712970
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1162716419
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3671669402
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3301734393
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.4241851938
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3478026231
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.3429957679
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.834120393
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.257413290
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2299978719
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3533522272
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.1537895656
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.2160503613
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1671128318
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.4240602737
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1485904120
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2868114761
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2114104043
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2161399999
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.399876597
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.509344801
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3176757517
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3405625584
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1999538995



Total test records in report: 1001
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.981016413 Sep 01 11:07:57 PM UTC 24 Sep 01 11:07:59 PM UTC 24 89122208 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.4226760930 Sep 01 11:07:57 PM UTC 24 Sep 01 11:08:01 PM UTC 24 286429763 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.4226652047 Sep 01 11:08:01 PM UTC 24 Sep 01 11:08:04 PM UTC 24 40379291 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1471341040 Sep 01 11:07:59 PM UTC 24 Sep 01 11:08:05 PM UTC 24 235713301 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3694379250 Sep 01 11:07:59 PM UTC 24 Sep 01 11:08:08 PM UTC 24 91281805 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.2730011344 Sep 01 11:08:01 PM UTC 24 Sep 01 11:08:10 PM UTC 24 987858847 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.927564308 Sep 01 11:08:02 PM UTC 24 Sep 01 11:08:10 PM UTC 24 1299233787 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3702277046 Sep 01 11:08:07 PM UTC 24 Sep 01 11:08:14 PM UTC 24 150539908 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3874010304 Sep 01 11:08:09 PM UTC 24 Sep 01 11:08:16 PM UTC 24 269155151 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2187931446 Sep 01 11:08:05 PM UTC 24 Sep 01 11:08:16 PM UTC 24 253226782 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.856215533 Sep 01 11:07:59 PM UTC 24 Sep 01 11:08:16 PM UTC 24 352661245 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1905302074 Sep 01 11:08:01 PM UTC 24 Sep 01 11:08:20 PM UTC 24 1407221388 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3857880868 Sep 01 11:08:13 PM UTC 24 Sep 01 11:08:23 PM UTC 24 205479538 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2225661820 Sep 01 11:08:21 PM UTC 24 Sep 01 11:08:24 PM UTC 24 122311684 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2763290773 Sep 01 11:08:24 PM UTC 24 Sep 01 11:08:27 PM UTC 24 33808587 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3584334132 Sep 01 11:08:11 PM UTC 24 Sep 01 11:08:29 PM UTC 24 1403659392 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.3182767950 Sep 01 11:08:24 PM UTC 24 Sep 01 11:08:30 PM UTC 24 62042716 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.2073002124 Sep 01 11:07:59 PM UTC 24 Sep 01 11:08:34 PM UTC 24 467322473 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.309327046 Sep 01 11:08:31 PM UTC 24 Sep 01 11:08:34 PM UTC 24 102591948 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3821663264 Sep 01 11:08:10 PM UTC 24 Sep 01 11:08:40 PM UTC 24 7141255926 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1748913334 Sep 01 11:08:03 PM UTC 24 Sep 01 11:08:41 PM UTC 24 896566436 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1306989710 Sep 01 11:08:30 PM UTC 24 Sep 01 11:08:42 PM UTC 24 318777762 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3530878273 Sep 01 11:08:15 PM UTC 24 Sep 01 11:08:43 PM UTC 24 2066544239 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3760207490 Sep 01 11:08:42 PM UTC 24 Sep 01 11:08:44 PM UTC 24 34045251 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2451592750 Sep 01 11:08:35 PM UTC 24 Sep 01 11:08:48 PM UTC 24 1030010540 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1602823808 Sep 01 11:08:43 PM UTC 24 Sep 01 11:08:51 PM UTC 24 1644788826 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2934595171 Sep 01 11:08:41 PM UTC 24 Sep 01 11:08:52 PM UTC 24 220396544 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.42636551 Sep 01 11:08:17 PM UTC 24 Sep 01 11:08:55 PM UTC 24 398307740 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2138833918 Sep 01 11:08:53 PM UTC 24 Sep 01 11:08:57 PM UTC 24 434702947 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.814420135 Sep 01 11:08:27 PM UTC 24 Sep 01 11:09:01 PM UTC 24 584207191 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2726713996 Sep 01 11:08:52 PM UTC 24 Sep 01 11:09:02 PM UTC 24 1470903091 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1182342572 Sep 01 11:08:02 PM UTC 24 Sep 01 11:09:07 PM UTC 24 25224518425 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1786223828 Sep 01 11:08:35 PM UTC 24 Sep 01 11:09:08 PM UTC 24 981457426 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3527471954 Sep 01 11:08:50 PM UTC 24 Sep 01 11:09:10 PM UTC 24 492392229 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.825053159 Sep 01 11:09:01 PM UTC 24 Sep 01 11:09:14 PM UTC 24 386224120 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.97554828 Sep 01 11:08:58 PM UTC 24 Sep 01 11:09:15 PM UTC 24 237113832 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1302179998 Sep 01 11:09:13 PM UTC 24 Sep 01 11:09:16 PM UTC 24 44385703 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3658090462 Sep 01 11:09:02 PM UTC 24 Sep 01 11:09:16 PM UTC 24 469948397 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3976193159 Sep 01 11:08:45 PM UTC 24 Sep 01 11:09:16 PM UTC 24 3330641477 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2353757732 Sep 01 11:08:06 PM UTC 24 Sep 01 11:09:16 PM UTC 24 8725668077 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.675733351 Sep 01 11:09:15 PM UTC 24 Sep 01 11:09:17 PM UTC 24 14585698 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.2220896418 Sep 01 11:09:14 PM UTC 24 Sep 01 11:09:20 PM UTC 24 355883911 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.687160376 Sep 01 11:09:17 PM UTC 24 Sep 01 11:09:21 PM UTC 24 156588573 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1584795779 Sep 01 11:09:20 PM UTC 24 Sep 01 11:09:22 PM UTC 24 17435712 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2546709139 Sep 01 11:08:56 PM UTC 24 Sep 01 11:09:23 PM UTC 24 2539438767 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.528567965 Sep 01 11:09:22 PM UTC 24 Sep 01 11:09:26 PM UTC 24 170283486 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3151261099 Sep 01 11:08:17 PM UTC 24 Sep 01 11:09:28 PM UTC 24 24947737869 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3412487334 Sep 01 11:09:17 PM UTC 24 Sep 01 11:09:32 PM UTC 24 88355026 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1790257880 Sep 01 11:09:17 PM UTC 24 Sep 01 11:09:32 PM UTC 24 222618816 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.4028001719 Sep 01 11:08:44 PM UTC 24 Sep 01 11:09:35 PM UTC 24 1066779157 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1723781963 Sep 01 11:09:25 PM UTC 24 Sep 01 11:09:36 PM UTC 24 675436680 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.223152787 Sep 01 11:09:27 PM UTC 24 Sep 01 11:09:39 PM UTC 24 360857706 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.366924854 Sep 01 11:09:18 PM UTC 24 Sep 01 11:09:43 PM UTC 24 344631603 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2598238028 Sep 01 11:09:33 PM UTC 24 Sep 01 11:09:45 PM UTC 24 1347076169 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1228170304 Sep 01 11:09:17 PM UTC 24 Sep 01 11:09:48 PM UTC 24 596051563 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.457609365 Sep 01 11:09:32 PM UTC 24 Sep 01 11:09:49 PM UTC 24 438934424 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3304389163 Sep 01 11:09:50 PM UTC 24 Sep 01 11:09:53 PM UTC 24 13814673 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.841028525 Sep 01 11:08:51 PM UTC 24 Sep 01 11:09:53 PM UTC 24 1891818789 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.963311329 Sep 01 11:09:37 PM UTC 24 Sep 01 11:09:54 PM UTC 24 971090323 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3261875710 Sep 01 11:09:40 PM UTC 24 Sep 01 11:09:54 PM UTC 24 287475641 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1140596036 Sep 01 11:09:37 PM UTC 24 Sep 01 11:09:56 PM UTC 24 760699718 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.3567498173 Sep 01 11:09:53 PM UTC 24 Sep 01 11:09:57 PM UTC 24 434738613 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2755835333 Sep 01 11:09:55 PM UTC 24 Sep 01 11:09:57 PM UTC 24 13117040 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3580485278 Sep 01 11:09:55 PM UTC 24 Sep 01 11:10:01 PM UTC 24 53232525 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.902362603 Sep 01 11:09:16 PM UTC 24 Sep 01 11:10:01 PM UTC 24 1328057205 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1875219307 Sep 01 11:09:58 PM UTC 24 Sep 01 11:10:02 PM UTC 24 52917301 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.1048645594 Sep 01 11:10:01 PM UTC 24 Sep 01 11:10:04 PM UTC 24 29661702 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3943660532 Sep 01 11:09:29 PM UTC 24 Sep 01 11:10:09 PM UTC 24 2209318389 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1193290262 Sep 01 11:09:33 PM UTC 24 Sep 01 11:10:11 PM UTC 24 1079767213 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.2940933650 Sep 01 11:09:23 PM UTC 24 Sep 01 11:10:12 PM UTC 24 7269250736 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3082570447 Sep 01 11:09:58 PM UTC 24 Sep 01 11:10:13 PM UTC 24 430016736 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2588013048 Sep 01 11:10:01 PM UTC 24 Sep 01 11:10:13 PM UTC 24 1060251627 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1836635794 Sep 01 11:10:05 PM UTC 24 Sep 01 11:10:14 PM UTC 24 397896935 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.2008616405 Sep 01 11:09:58 PM UTC 24 Sep 01 11:10:15 PM UTC 24 262633820 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2197498525 Sep 01 11:10:12 PM UTC 24 Sep 01 11:10:16 PM UTC 24 626921669 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2242253346 Sep 01 11:10:13 PM UTC 24 Sep 01 11:10:19 PM UTC 24 799634758 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.3028857174 Sep 01 11:10:03 PM UTC 24 Sep 01 11:10:22 PM UTC 24 362551782 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.3296423398 Sep 01 11:09:11 PM UTC 24 Sep 01 11:10:24 PM UTC 24 654685159 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.3296695774 Sep 01 11:09:58 PM UTC 24 Sep 01 11:10:26 PM UTC 24 585961617 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.529689201 Sep 01 11:10:25 PM UTC 24 Sep 01 11:10:28 PM UTC 24 76394313 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3886412750 Sep 01 11:10:25 PM UTC 24 Sep 01 11:10:28 PM UTC 24 65642387 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3447997541 Sep 01 11:10:14 PM UTC 24 Sep 01 11:10:29 PM UTC 24 1206119413 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1741764349 Sep 01 11:10:27 PM UTC 24 Sep 01 11:10:29 PM UTC 24 43453410 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.139259773 Sep 01 11:10:14 PM UTC 24 Sep 01 11:10:31 PM UTC 24 422537843 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.3633563785 Sep 01 11:10:16 PM UTC 24 Sep 01 11:10:32 PM UTC 24 906031557 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.425065886 Sep 01 11:09:49 PM UTC 24 Sep 01 11:10:34 PM UTC 24 419010307 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1510973544 Sep 01 11:10:33 PM UTC 24 Sep 01 11:10:35 PM UTC 24 13573041 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2070524480 Sep 01 11:09:55 PM UTC 24 Sep 01 11:10:35 PM UTC 24 276054988 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1886104454 Sep 01 11:10:30 PM UTC 24 Sep 01 11:10:36 PM UTC 24 64040156 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.3658599534 Sep 01 11:10:29 PM UTC 24 Sep 01 11:10:40 PM UTC 24 168135369 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.4082952371 Sep 01 11:10:35 PM UTC 24 Sep 01 11:10:42 PM UTC 24 862524002 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1631930742 Sep 01 11:10:33 PM UTC 24 Sep 01 11:10:43 PM UTC 24 223653386 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.1697699722 Sep 01 11:10:37 PM UTC 24 Sep 01 11:10:46 PM UTC 24 685064816 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.4136775881 Sep 01 11:10:32 PM UTC 24 Sep 01 11:10:47 PM UTC 24 630743482 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.427857984 Sep 01 11:09:09 PM UTC 24 Sep 01 11:10:48 PM UTC 24 2082487690 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.4076167032 Sep 01 11:10:31 PM UTC 24 Sep 01 11:10:50 PM UTC 24 401658512 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.1843766505 Sep 01 11:10:43 PM UTC 24 Sep 01 11:10:54 PM UTC 24 1717165485 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1300886295 Sep 01 11:10:14 PM UTC 24 Sep 01 11:10:56 PM UTC 24 2514919088 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2535579282 Sep 01 11:10:23 PM UTC 24 Sep 01 11:10:56 PM UTC 24 240639388 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3772945609 Sep 01 11:10:54 PM UTC 24 Sep 01 11:10:57 PM UTC 24 38017639 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2322539209 Sep 01 11:10:57 PM UTC 24 Sep 01 11:11:00 PM UTC 24 85448990 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.357793510 Sep 01 11:10:56 PM UTC 24 Sep 01 11:11:00 PM UTC 24 40124450 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1919270896 Sep 01 11:10:36 PM UTC 24 Sep 01 11:11:01 PM UTC 24 1377785171 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.108161576 Sep 01 11:10:10 PM UTC 24 Sep 01 11:11:04 PM UTC 24 1847935165 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1135264213 Sep 01 11:10:45 PM UTC 24 Sep 01 11:11:05 PM UTC 24 3378707569 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.598332436 Sep 01 11:11:01 PM UTC 24 Sep 01 11:11:06 PM UTC 24 185268669 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.4020976091 Sep 01 11:11:01 PM UTC 24 Sep 01 11:11:06 PM UTC 24 298145056 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2676528865 Sep 01 11:11:04 PM UTC 24 Sep 01 11:11:07 PM UTC 24 10842264 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.771454318 Sep 01 11:09:08 PM UTC 24 Sep 01 11:11:08 PM UTC 24 17606201561 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1254632910 Sep 01 11:10:28 PM UTC 24 Sep 01 11:11:10 PM UTC 24 263048148 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1111508899 Sep 01 11:10:46 PM UTC 24 Sep 01 11:11:10 PM UTC 24 466360432 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1555860244 Sep 01 11:10:44 PM UTC 24 Sep 01 11:11:10 PM UTC 24 910047398 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3074439323 Sep 01 11:10:46 PM UTC 24 Sep 01 11:11:11 PM UTC 24 535906514 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2190371303 Sep 01 11:10:48 PM UTC 24 Sep 01 11:11:12 PM UTC 24 448569637 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2355760679 Sep 01 11:11:07 PM UTC 24 Sep 01 11:11:13 PM UTC 24 660451346 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2696155521 Sep 01 11:11:02 PM UTC 24 Sep 01 11:11:17 PM UTC 24 433528946 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3598461574 Sep 01 11:11:10 PM UTC 24 Sep 01 11:11:17 PM UTC 24 242800821 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2587939331 Sep 01 11:11:06 PM UTC 24 Sep 01 11:11:17 PM UTC 24 498168475 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.4105765916 Sep 01 11:10:57 PM UTC 24 Sep 01 11:11:17 PM UTC 24 195936485 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.443341360 Sep 01 11:11:01 PM UTC 24 Sep 01 11:11:19 PM UTC 24 395700534 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2763651491 Sep 01 11:11:18 PM UTC 24 Sep 01 11:11:20 PM UTC 24 41703310 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2580452019 Sep 01 11:11:18 PM UTC 24 Sep 01 11:11:20 PM UTC 24 13309503 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1692725349 Sep 01 11:11:18 PM UTC 24 Sep 01 11:11:23 PM UTC 24 189070880 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.275138193 Sep 01 11:11:12 PM UTC 24 Sep 01 11:11:24 PM UTC 24 234343913 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.4277966067 Sep 01 11:10:02 PM UTC 24 Sep 01 11:11:24 PM UTC 24 13874512892 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3600523105 Sep 01 11:11:22 PM UTC 24 Sep 01 11:11:25 PM UTC 24 104165039 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2668864076 Sep 01 11:11:03 PM UTC 24 Sep 01 11:11:26 PM UTC 24 1406155242 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3071665904 Sep 01 11:11:12 PM UTC 24 Sep 01 11:11:27 PM UTC 24 1340823699 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.530115631 Sep 01 11:11:09 PM UTC 24 Sep 01 11:11:28 PM UTC 24 600496021 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.467587296 Sep 01 11:11:26 PM UTC 24 Sep 01 11:11:29 PM UTC 24 29098803 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2727328660 Sep 01 11:10:41 PM UTC 24 Sep 01 11:11:30 PM UTC 24 10954493411 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.1542259853 Sep 01 11:11:22 PM UTC 24 Sep 01 11:11:32 PM UTC 24 58828903 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.1927260620 Sep 01 11:11:13 PM UTC 24 Sep 01 11:11:34 PM UTC 24 1962363595 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1153674283 Sep 01 11:11:07 PM UTC 24 Sep 01 11:11:35 PM UTC 24 628445266 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.3464567771 Sep 01 11:11:27 PM UTC 24 Sep 01 11:11:35 PM UTC 24 863682328 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.1742135167 Sep 01 11:11:31 PM UTC 24 Sep 01 11:11:37 PM UTC 24 184381821 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.53401137 Sep 01 11:11:24 PM UTC 24 Sep 01 11:11:37 PM UTC 24 271560593 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.4210494827 Sep 01 11:11:31 PM UTC 24 Sep 01 11:11:39 PM UTC 24 603597802 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.372414669 Sep 01 11:11:38 PM UTC 24 Sep 01 11:11:40 PM UTC 24 78232701 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1456213058 Sep 01 11:11:25 PM UTC 24 Sep 01 11:11:41 PM UTC 24 1114269835 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.2689416147 Sep 01 11:11:12 PM UTC 24 Sep 01 11:11:42 PM UTC 24 567929631 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3995292267 Sep 01 11:11:39 PM UTC 24 Sep 01 11:11:43 PM UTC 24 34652134 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2924529030 Sep 01 11:11:30 PM UTC 24 Sep 01 11:11:43 PM UTC 24 1469606167 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3854775683 Sep 01 11:11:41 PM UTC 24 Sep 01 11:11:44 PM UTC 24 15787159 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.866011289 Sep 01 11:11:45 PM UTC 24 Sep 01 11:11:50 PM UTC 24 256675376 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.4133185979 Sep 01 11:10:51 PM UTC 24 Sep 01 11:11:50 PM UTC 24 205789659 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1560452810 Sep 01 11:11:21 PM UTC 24 Sep 01 11:11:50 PM UTC 24 1057097344 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2113766902 Sep 01 11:11:36 PM UTC 24 Sep 01 11:11:50 PM UTC 24 1008361587 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.3326973513 Sep 01 11:11:50 PM UTC 24 Sep 01 11:11:52 PM UTC 24 19577268 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1782175636 Sep 01 11:10:36 PM UTC 24 Sep 01 11:11:52 PM UTC 24 2995038813 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2888677253 Sep 01 11:11:35 PM UTC 24 Sep 01 11:11:52 PM UTC 24 315780194 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3674789356 Sep 01 11:11:28 PM UTC 24 Sep 01 11:11:52 PM UTC 24 741561075 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3813203676 Sep 01 11:11:43 PM UTC 24 Sep 01 11:11:53 PM UTC 24 90223165 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.726401586 Sep 01 11:11:45 PM UTC 24 Sep 01 11:11:54 PM UTC 24 540077827 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3367912574 Sep 01 11:11:33 PM UTC 24 Sep 01 11:11:55 PM UTC 24 971111161 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1805921699 Sep 01 11:11:45 PM UTC 24 Sep 01 11:11:56 PM UTC 24 366480313 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3703105181 Sep 01 11:11:33 PM UTC 24 Sep 01 11:11:58 PM UTC 24 651521684 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.2970107424 Sep 01 11:11:25 PM UTC 24 Sep 01 11:11:58 PM UTC 24 3448562655 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1886658086 Sep 01 11:11:45 PM UTC 24 Sep 01 11:11:59 PM UTC 24 930577148 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.930305548 Sep 01 11:12:01 PM UTC 24 Sep 01 11:12:03 PM UTC 24 18365735 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1424149869 Sep 01 11:11:54 PM UTC 24 Sep 01 11:12:03 PM UTC 24 383599313 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2676449050 Sep 01 11:11:50 PM UTC 24 Sep 01 11:12:04 PM UTC 24 2956464175 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1143084798 Sep 01 11:11:54 PM UTC 24 Sep 01 11:12:04 PM UTC 24 1497272493 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.259796939 Sep 01 11:11:54 PM UTC 24 Sep 01 11:12:06 PM UTC 24 3999579479 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1162716419 Sep 01 11:12:04 PM UTC 24 Sep 01 11:12:06 PM UTC 24 40323852 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2058490986 Sep 01 11:11:55 PM UTC 24 Sep 01 11:12:08 PM UTC 24 247394445 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2003321151 Sep 01 11:12:04 PM UTC 24 Sep 01 11:12:09 PM UTC 24 37229000 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3459763107 Sep 01 11:11:55 PM UTC 24 Sep 01 11:12:09 PM UTC 24 234021981 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.490843207 Sep 01 11:11:54 PM UTC 24 Sep 01 11:12:11 PM UTC 24 3673785813 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3571574823 Sep 01 11:11:42 PM UTC 24 Sep 01 11:12:11 PM UTC 24 296133765 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.852397625 Sep 01 11:11:51 PM UTC 24 Sep 01 11:12:12 PM UTC 24 1728423592 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.181291285 Sep 01 11:12:10 PM UTC 24 Sep 01 11:12:12 PM UTC 24 16920659 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.740248254 Sep 01 11:12:07 PM UTC 24 Sep 01 11:12:14 PM UTC 24 351014126 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.195210937 Sep 01 11:11:57 PM UTC 24 Sep 01 11:12:14 PM UTC 24 2297632870 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.781842333 Sep 01 11:12:05 PM UTC 24 Sep 01 11:12:15 PM UTC 24 68344854 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.1654265394 Sep 01 11:11:31 PM UTC 24 Sep 01 11:12:17 PM UTC 24 1912949884 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3959534434 Sep 01 11:12:14 PM UTC 24 Sep 01 11:12:19 PM UTC 24 73309723 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.1469673688 Sep 01 11:12:09 PM UTC 24 Sep 01 11:12:20 PM UTC 24 202221471 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1626132620 Sep 01 11:12:10 PM UTC 24 Sep 01 11:12:20 PM UTC 24 970767349 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.526847 Sep 01 11:12:09 PM UTC 24 Sep 01 11:12:20 PM UTC 24 1328432896 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1691168743 Sep 01 11:12:13 PM UTC 24 Sep 01 11:12:21 PM UTC 24 151215070 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1999538995 Sep 01 11:12:22 PM UTC 24 Sep 01 11:12:24 PM UTC 24 15933950 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3563170245 Sep 01 11:12:22 PM UTC 24 Sep 01 11:12:24 PM UTC 24 108287637 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.399876597 Sep 01 11:12:22 PM UTC 24 Sep 01 11:12:25 PM UTC 24 86745366 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3143724938 Sep 01 11:12:16 PM UTC 24 Sep 01 11:12:26 PM UTC 24 1948692709 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3813991513 Sep 01 11:12:12 PM UTC 24 Sep 01 11:12:29 PM UTC 24 1713470231 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1671128318 Sep 01 11:12:25 PM UTC 24 Sep 01 11:12:30 PM UTC 24 95175948 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3673416800 Sep 01 11:11:54 PM UTC 24 Sep 01 11:12:30 PM UTC 24 1546528599 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.586859963 Sep 01 11:12:07 PM UTC 24 Sep 01 11:12:31 PM UTC 24 5150789280 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3448828778 Sep 01 11:12:20 PM UTC 24 Sep 01 11:12:32 PM UTC 24 231497166 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.3140262004 Sep 01 11:13:14 PM UTC 24 Sep 01 11:13:21 PM UTC 24 1346666014 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3301734393 Sep 01 11:12:32 PM UTC 24 Sep 01 11:12:34 PM UTC 24 13980978 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.256238113 Sep 01 11:12:16 PM UTC 24 Sep 01 11:12:37 PM UTC 24 928490487 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1770819650 Sep 01 11:12:20 PM UTC 24 Sep 01 11:12:37 PM UTC 24 410275970 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.355963121 Sep 01 11:11:27 PM UTC 24 Sep 01 11:12:37 PM UTC 24 2282478558 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2161399999 Sep 01 11:12:27 PM UTC 24 Sep 01 11:12:37 PM UTC 24 419573181 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3176757517 Sep 01 11:12:25 PM UTC 24 Sep 01 11:12:37 PM UTC 24 331745962 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.666675984 Sep 01 11:12:18 PM UTC 24 Sep 01 11:12:38 PM UTC 24 1856231454 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3533522272 Sep 01 11:12:32 PM UTC 24 Sep 01 11:12:39 PM UTC 24 218350124 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.4241851938 Sep 01 11:12:26 PM UTC 24 Sep 01 11:12:40 PM UTC 24 1235625992 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.2197358070 Sep 01 11:12:05 PM UTC 24 Sep 01 11:12:43 PM UTC 24 1196715235 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3478026231 Sep 01 11:12:38 PM UTC 24 Sep 01 11:12:44 PM UTC 24 1280596126 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.834120393 Sep 01 11:12:38 PM UTC 24 Sep 01 11:12:45 PM UTC 24 236875875 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3671669402 Sep 01 11:12:44 PM UTC 24 Sep 01 11:12:47 PM UTC 24 18803060 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.4240602737 Sep 01 11:12:30 PM UTC 24 Sep 01 11:12:47 PM UTC 24 650207041 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3106212905 Sep 01 11:12:45 PM UTC 24 Sep 01 11:12:47 PM UTC 24 12369870 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.1898921356 Sep 01 11:12:45 PM UTC 24 Sep 01 11:12:49 PM UTC 24 35361490 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2868114761 Sep 01 11:12:40 PM UTC 24 Sep 01 11:12:50 PM UTC 24 276353877 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2114104043 Sep 01 11:12:39 PM UTC 24 Sep 01 11:12:50 PM UTC 24 1296179911 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.2173055036 Sep 01 11:12:48 PM UTC 24 Sep 01 11:12:52 PM UTC 24 102846992 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.4014280777 Sep 01 11:13:10 PM UTC 24 Sep 01 11:13:21 PM UTC 24 412257794 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.798021440 Sep 01 11:11:08 PM UTC 24 Sep 01 11:12:55 PM UTC 24 6850838749 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.2160503613 Sep 01 11:12:33 PM UTC 24 Sep 01 11:12:55 PM UTC 24 318685798 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2299978719 Sep 01 11:12:38 PM UTC 24 Sep 01 11:12:56 PM UTC 24 707183585 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.257413290 Sep 01 11:12:35 PM UTC 24 Sep 01 11:12:59 PM UTC 24 1160552825 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2409227420 Sep 01 11:12:13 PM UTC 24 Sep 01 11:12:59 PM UTC 24 2658322742 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.2311465039 Sep 01 11:12:51 PM UTC 24 Sep 01 11:13:00 PM UTC 24 159246686 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1485904120 Sep 01 11:12:38 PM UTC 24 Sep 01 11:13:01 PM UTC 24 1377906883 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.509344801 Sep 01 11:12:24 PM UTC 24 Sep 01 11:13:01 PM UTC 24 173920350 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.4043209914 Sep 01 11:11:51 PM UTC 24 Sep 01 11:13:01 PM UTC 24 10249220174 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.314827994 Sep 01 11:12:48 PM UTC 24 Sep 01 11:13:03 PM UTC 24 78969560 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.4104410483 Sep 01 11:12:56 PM UTC 24 Sep 01 11:13:05 PM UTC 24 4408014562 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3375039253 Sep 01 11:12:52 PM UTC 24 Sep 01 11:13:05 PM UTC 24 2481411567 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3816483111 Sep 01 11:13:04 PM UTC 24 Sep 01 11:13:07 PM UTC 24 33776238 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.1537895656 Sep 01 11:12:32 PM UTC 24 Sep 01 11:13:09 PM UTC 24 8025159618 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3714475044 Sep 01 11:13:06 PM UTC 24 Sep 01 11:13:09 PM UTC 24 19673725 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.2337762837 Sep 01 11:13:06 PM UTC 24 Sep 01 11:13:09 PM UTC 24 104758189 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.368212003 Sep 01 11:12:12 PM UTC 24 Sep 01 11:13:15 PM UTC 24 6720318189 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3632088498 Sep 01 11:13:01 PM UTC 24 Sep 01 11:13:15 PM UTC 24 189519103 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1736739626 Sep 01 11:13:10 PM UTC 24 Sep 01 11:13:15 PM UTC 24 651686407 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2455241918 Sep 01 11:13:02 PM UTC 24 Sep 01 11:13:15 PM UTC 24 912074082 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.297831403 Sep 01 11:12:47 PM UTC 24 Sep 01 11:13:16 PM UTC 24 932634436 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.511484279 Sep 01 11:09:44 PM UTC 24 Sep 01 11:13:16 PM UTC 24 7085917649 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3269961287 Sep 01 11:13:02 PM UTC 24 Sep 01 11:13:16 PM UTC 24 1720664104 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1963457990 Sep 01 11:12:50 PM UTC 24 Sep 01 11:13:17 PM UTC 24 625432583 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.291065233 Sep 01 11:13:09 PM UTC 24 Sep 01 11:13:18 PM UTC 24 74913223 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2762594774 Sep 01 11:10:48 PM UTC 24 Sep 01 11:13:18 PM UTC 24 7181096950 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.1669110997 Sep 01 11:13:18 PM UTC 24 Sep 01 11:13:22 PM UTC 24 67917014 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.725437877 Sep 01 11:13:22 PM UTC 24 Sep 01 11:13:24 PM UTC 24 31990465 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.3290342355 Sep 01 11:12:59 PM UTC 24 Sep 01 11:13:25 PM UTC 24 1117977092 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1657923392 Sep 01 11:13:23 PM UTC 24 Sep 01 11:13:25 PM UTC 24 42057366 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1877407412 Sep 01 11:11:06 PM UTC 24 Sep 01 11:13:26 PM UTC 24 21001821551 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3405625584 Sep 01 11:12:40 PM UTC 24 Sep 01 11:13:27 PM UTC 24 971394015 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1952529077 Sep 01 11:13:23 PM UTC 24 Sep 01 11:13:27 PM UTC 24 27801001 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.1481839950 Sep 01 11:13:10 PM UTC 24 Sep 01 11:13:29 PM UTC 24 1060824663 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.704806686 Sep 01 11:13:25 PM UTC 24 Sep 01 11:13:31 PM UTC 24 52042339 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.4253020013 Sep 01 11:12:55 PM UTC 24 Sep 01 11:13:31 PM UTC 24 988640065 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2683999296 Sep 01 11:13:26 PM UTC 24 Sep 01 11:13:31 PM UTC 24 137244405 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.414870151 Sep 01 11:13:29 PM UTC 24 Sep 01 11:13:33 PM UTC 24 58396851 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.4232578884 Sep 01 11:13:18 PM UTC 24 Sep 01 11:13:33 PM UTC 24 509250189 ps