Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64847286

1

T1

1232

T2

2394

T3

1408

auto[1]

1129725

1

T3

99

T13

99

T14

7098

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64856966

1

T1

1232

T2

2394

T3

1507

auto[1]

1120045

1

T13

495

T14

7467

T15

2871

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5504033	1			T1	80		T2	605		T3	190
auto[IdleSt]	17484705	1			T1	200		T2	539		T3	1104
auto[ClkMuxSt]	28840	1			T2	5		T3	1		T4	8
auto[CntIncrSt]	28650	1			T2	5		T3	1		T4	8
auto[CntProgSt]	1286639	1			T2	10		T3	2		T4	105
auto[TransCheckSt]	22712	1			T2	5		T4	8		T13	8
auto[TokenHashSt]	18877029	1			T2	303		T4	29916		T13	240
auto[FlashRmaSt]	28529	1			T2	24		T4	24		T13	8
auto[TokenCheck0St]	10183	1			T2	5		T4	8		T13	8
auto[TokenCheck1St]	7361	1			T2	5		T4	8		T13	8
auto[TransProgSt]	315021	1			T2	10		T4	135		T13	216
auto[PostTransSt]	9408525	1			T1	952		T2	857		T3	72
auto[ScrapSt]	112002	1			T2	21		T5	775		T11	1912
auto[EscalateSt]	5043874	1			T3	137		T13	1503		T14	10514
auto[InvalidSt]	7817540	1			T13	777		T15	8275		T17	20537

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1368	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7817540	1			T13	777		T15	8275		T17	20537
EscalateSt	5043874	1			T3	137		T13	1503		T14	10514
ScrapSt	112002	1			T2	21		T5	775		T11	1912
PostTransSt	9408525	1			T1	952		T2	857		T3	72
TransProgSt	315021	1			T2	10		T4	135		T13	216
TokenCheck1St	7361	1			T2	5		T4	8		T13	8
TokenCheck0St	10183	1			T2	5		T4	8		T13	8
FlashRmaSt	28529	1			T2	24		T4	24		T13	8
TokenHashSt	18877029	1			T2	303		T4	29916		T13	240
TransCheckSt	22712	1			T2	5		T4	8		T13	8
CntProgSt	1286639	1			T2	10		T3	2		T4	105
CntIncrSt	28650	1			T2	5		T3	1		T4	8
ClkMuxSt	28840	1			T2	5		T3	1		T4	8
IdleSt	17484705	1			T1	200		T2	539		T3	1104
ResetSt	5504033	1			T1	80		T2	605		T3	190
arcs[ResetSt=>IdleSt]	42512	1			T1	1		T2	6		T3	2
arcs[IdleSt=>ScrapSt]	219	1			T2	1		T5	2		T11	2
arcs[IdleSt=>ClkMuxSt]	28683	1			T2	5		T3	1		T4	8
arcs[ClkMuxSt=>CntIncrSt]	28650	1			T2	5		T3	1		T4	8
arcs[CntIncrSt=>PostTransSt]	1258	1			T23	6		T37	9		T19	6
arcs[CntIncrSt=>CntProgSt]	27331	1			T2	5		T3	1		T4	8
arcs[CntProgSt=>PostTransSt]	3697	1			T3	1		T7	18		T23	18
arcs[CntProgSt=>TransCheckSt]	22712	1			T2	5		T4	8		T13	8
arcs[TransCheckSt=>PostTransSt]	3126	1			T16	44		T23	13		T37	6
arcs[TransCheckSt=>TokenHashSt]	19449	1			T2	5		T4	8		T13	8
arcs[TokenHashSt=>PostTransSt]	8348	1			T16	9		T23	38		T40	3
arcs[TokenHashSt=>FlashRmaSt]	10221	1			T2	5		T4	8		T13	8
arcs[FlashRmaSt=>TokenCheck0St]	10183	1			T2	5		T4	8		T13	8
arcs[TokenCheck0St=>PostTransSt]	2764	1			T16	24		T23	9		T40	7
arcs[TokenCheck0St=>TokenCheck1St]	7361	1			T2	5		T4	8		T13	8
arcs[TokenCheck1St=>PostTransSt]	623	1			T16	10		T23	1		T37	1
arcs[TransProgSt=>PostTransSt]	6052	1			T2	5		T4	8		T13	8
arcs[IdleSt=>EscalateSt]	121	1			T41	2		T35	5		T58	6
arcs[ClkMuxSt=>EscalateSt]	33	1			T14	1		T41	1		T35	1
arcs[CntIncrSt=>EscalateSt]	61	1			T41	2		T39	1		T58	1
arcs[CntProgSt=>EscalateSt]	922	1			T14	3		T41	7		T39	11
arcs[TransCheckSt=>EscalateSt]	137	1			T14	5		T41	9		T35	6
arcs[TokenHashSt=>EscalateSt]	880	1			T14	20		T41	24		T39	11
arcs[FlashRmaSt=>EscalateSt]	38	1			T41	2		T39	1		T58	1
arcs[TokenCheck0St=>EscalateSt]	58	1			T14	2		T41	5		T35	2
arcs[TokenCheck1St=>EscalateSt]	28	1			T14	1		T39	2		T35	3
arcs[TransProgSt=>EscalateSt]	658	1			T14	3		T41	8		T39	14
arcs[PostTransSt=>EscalateSt]	4135	1			T3	1		T14	18		T7	18
arcs[InvalidSt=>EscalateSt]	10039	1			T13	6		T15	45		T17	7

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5503847	1			T1	80		T2	605		T3	190
auto[0]	auto[IdleSt]	17484626	1			T1	200		T2	539		T3	1104
auto[0]	auto[ClkMuxSt]	28819	1			T2	5		T3	1		T4	8
auto[0]	auto[CntIncrSt]	28609	1			T2	5		T3	1		T4	8
auto[0]	auto[CntProgSt]	1286024	1			T2	10		T3	2		T4	105
auto[0]	auto[TransCheckSt]	22627	1			T2	5		T4	8		T13	8
auto[0]	auto[TokenHashSt]	18876469	1			T2	303		T4	29916		T13	240
auto[0]	auto[FlashRmaSt]	28501	1			T2	24		T4	24		T13	8
auto[0]	auto[TokenCheck0St]	10143	1			T2	5		T4	8		T13	8
auto[0]	auto[TokenCheck1St]	7345	1			T2	5		T4	8		T13	8
auto[0]	auto[TransProgSt]	314571	1			T2	10		T4	135		T13	216
auto[0]	auto[PostTransSt]	9406439	1			T1	952		T2	857		T3	71
auto[0]	auto[ScrapSt]	111960	1			T2	21		T5	775		T11	1912
auto[0]	auto[EscalateSt]	3923486	1			T3	39		T13	1405		T14	3454
auto[0]	auto[InvalidSt]	7812452	1			T13	776		T15	8259		T17	20536
auto[1]	auto[ResetSt]	186	1			T14	3		T41	5		T39	6
auto[1]	auto[IdleSt]	79	1			T41	2		T35	2		T58	4
auto[1]	auto[ClkMuxSt]	21	1			T14	1		T41	1		T228	1
auto[1]	auto[CntIncrSt]	41	1			T41	2		T39	1		T58	1
auto[1]	auto[CntProgSt]	615	1			T14	3		T41	4		T39	5
auto[1]	auto[TransCheckSt]	85	1			T14	2		T41	7		T35	3
auto[1]	auto[TokenHashSt]	560	1			T14	11		T41	13		T39	6
auto[1]	auto[FlashRmaSt]	28	1			T41	1		T58	1		T229	1
auto[1]	auto[TokenCheck0St]	40	1			T14	1		T41	1		T35	2
auto[1]	auto[TokenCheck1St]	16	1			T14	1		T35	2		T230	1
auto[1]	auto[TransProgSt]	450	1			T14	2		T41	7		T39	10
auto[1]	auto[PostTransSt]	2086	1			T3	1		T14	14		T7	13
auto[1]	auto[ScrapSt]	42	1			T41	2		T35	2		T167	1
auto[1]	auto[EscalateSt]	1120388	1			T3	98		T13	98		T14	7060
auto[1]	auto[InvalidSt]	5088	1			T13	1		T15	16		T17	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5503869	1			T1	80		T2	605		T3	190
auto[0]	auto[IdleSt]	17484625	1			T1	200		T2	539		T3	1104
auto[0]	auto[ClkMuxSt]	28813	1			T2	5		T3	1		T4	8
auto[0]	auto[CntIncrSt]	28611	1			T2	5		T3	1		T4	8
auto[0]	auto[CntProgSt]	1286032	1			T2	10		T3	2		T4	105
auto[0]	auto[TransCheckSt]	22623	1			T2	5		T4	8		T13	8
auto[0]	auto[TokenHashSt]	18876437	1			T2	303		T4	29916		T13	240
auto[0]	auto[FlashRmaSt]	28505	1			T2	24		T4	24		T13	8
auto[0]	auto[TokenCheck0St]	10139	1			T2	5		T4	8		T13	8
auto[0]	auto[TokenCheck1St]	7345	1			T2	5		T4	8		T13	8
auto[0]	auto[TransProgSt]	314593	1			T2	10		T4	135		T13	216
auto[0]	auto[PostTransSt]	9406343	1			T1	952		T2	857		T3	72
auto[0]	auto[ScrapSt]	111964	1			T2	21		T5	775		T11	1912
auto[0]	auto[EscalateSt]	3933110	1			T3	137		T13	1013		T14	3087
auto[0]	auto[InvalidSt]	7812589	1			T13	772		T15	8246		T17	20531
auto[1]	auto[ResetSt]	164	1			T14	3		T41	3		T39	4
auto[1]	auto[IdleSt]	80	1			T41	1		T35	4		T58	5
auto[1]	auto[ClkMuxSt]	27	1			T14	1		T35	1		T228	2
auto[1]	auto[CntIncrSt]	39	1			T41	1		T39	1		T167	4
auto[1]	auto[CntProgSt]	607	1			T14	1		T41	5		T39	10
auto[1]	auto[TransCheckSt]	89	1			T14	4		T41	4		T35	4
auto[1]	auto[TokenHashSt]	592	1			T14	15		T41	20		T39	9
auto[1]	auto[FlashRmaSt]	24	1			T41	1		T39	1		T58	1
auto[1]	auto[TokenCheck0St]	44	1			T14	1		T41	5		T35	1
auto[1]	auto[TokenCheck1St]	16	1			T14	1		T39	2		T35	1
auto[1]	auto[TransProgSt]	428	1			T14	2		T41	3		T39	8
auto[1]	auto[PostTransSt]	2182	1			T14	12		T7	5		T23	11
auto[1]	auto[ScrapSt]	38	1			T41	1		T39	1		T35	1
auto[1]	auto[EscalateSt]	1110764	1			T13	490		T14	7427		T15	2842
auto[1]	auto[InvalidSt]	4951	1			T13	5		T15	29		T17	6