Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.99 97.99 96.13 93.40 97.67 98.55 98.76 96.47


Total tests in report: 1001
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.16 65.16 80.78 80.78 45.00 45.00 55.89 55.89 55.81 55.81 79.67 79.67 91.79 91.79 47.17 47.17 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.4256444560
76.43 11.27 87.98 7.19 72.82 27.81 70.19 14.30 69.77 13.95 86.72 7.05 93.28 1.49 54.24 7.07 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4056445872
81.77 5.34 95.07 7.09 74.71 1.89 72.74 2.55 76.74 6.98 90.46 3.73 93.78 0.50 68.90 14.66 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3050675329
84.32 2.55 96.08 1.01 83.71 9.00 75.35 2.61 76.74 0.00 91.91 1.45 94.53 0.75 71.91 3.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1941206032
86.69 2.37 96.18 0.10 83.98 0.27 75.81 0.47 88.37 11.63 92.74 0.83 95.02 0.50 74.73 2.83 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3743216275
88.41 1.72 96.18 0.00 84.25 0.27 84.71 8.90 88.37 0.00 93.15 0.41 95.02 0.00 77.21 2.47 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1469110277
89.61 1.19 96.38 0.20 86.14 1.89 84.75 0.04 88.37 0.00 93.78 0.62 96.02 1.00 81.80 4.59 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2590709459
90.69 1.09 96.88 0.50 87.58 1.44 84.76 0.01 93.02 4.65 94.61 0.83 96.02 0.00 81.98 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2102313984
91.71 1.02 96.88 0.00 87.67 0.09 86.58 1.82 93.02 0.00 95.44 0.83 96.02 0.00 86.40 4.42 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3363736183
92.54 0.82 96.98 0.10 88.48 0.81 87.01 0.43 95.35 2.33 96.06 0.62 96.27 0.25 87.63 1.24 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1306695288
93.13 0.59 96.98 0.00 88.48 0.00 90.41 3.40 95.35 0.00 96.27 0.21 96.27 0.00 88.16 0.53 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3446576824
93.62 0.49 97.08 0.10 89.56 1.08 90.45 0.04 95.35 0.00 96.47 0.21 96.52 0.25 89.93 1.77 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1237467496
94.01 0.39 97.08 0.00 90.64 1.08 90.45 0.00 95.35 0.00 96.47 0.00 96.77 0.25 91.34 1.41 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.655839729
94.39 0.38 97.28 0.20 90.64 0.00 90.47 0.02 95.35 0.00 97.30 0.83 96.77 0.00 92.93 1.59 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2693271556
94.72 0.33 97.28 0.00 90.64 0.00 90.47 0.00 97.67 2.33 97.30 0.00 96.77 0.00 92.93 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.2716181920
95.00 0.28 97.64 0.35 91.54 0.90 90.93 0.47 97.67 0.00 97.51 0.21 96.77 0.00 92.93 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1540370510
95.22 0.22 97.64 0.00 91.54 0.00 92.13 1.19 97.67 0.00 97.51 0.00 96.77 0.00 93.29 0.35 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.2667409685
95.44 0.22 97.69 0.05 92.44 0.90 92.13 0.00 97.67 0.00 97.93 0.41 96.77 0.00 93.46 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.209541870
95.65 0.21 97.69 0.00 92.44 0.00 92.13 0.00 97.67 0.00 97.93 0.00 98.26 1.49 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3100673197
95.86 0.21 97.79 0.10 92.53 0.09 92.13 0.00 97.67 0.00 98.13 0.21 98.26 0.00 94.52 1.06 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2585770852
96.06 0.20 97.94 0.15 92.53 0.00 92.53 0.40 97.67 0.00 98.34 0.21 98.51 0.25 94.88 0.35 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.4255958873
96.20 0.14 97.99 0.05 92.71 0.18 92.95 0.41 97.67 0.00 98.34 0.00 98.51 0.00 95.23 0.35 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3145921436
96.28 0.08 97.99 0.00 93.07 0.36 92.95 0.00 97.67 0.00 98.34 0.00 98.51 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2907321219
96.34 0.06 97.99 0.00 93.52 0.45 92.95 0.00 97.67 0.00 98.34 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1109973948
96.40 0.06 97.99 0.00 93.70 0.18 92.97 0.02 97.67 0.00 98.55 0.21 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2538222563
96.44 0.04 97.99 0.00 93.70 0.00 93.27 0.30 97.67 0.00 98.55 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.828412569
96.48 0.04 97.99 0.00 93.97 0.27 93.27 0.00 97.67 0.00 98.55 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4089619091
96.52 0.04 97.99 0.00 94.24 0.27 93.27 0.00 97.67 0.00 98.55 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.860251266
96.56 0.04 97.99 0.00 94.51 0.27 93.27 0.00 97.67 0.00 98.55 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.154764088
96.60 0.04 97.99 0.00 94.78 0.27 93.27 0.00 97.67 0.00 98.55 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2905387286
96.63 0.04 97.99 0.00 94.78 0.00 93.27 0.00 97.67 0.00 98.55 0.00 98.76 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2312096666
96.66 0.03 97.99 0.00 94.78 0.00 93.29 0.02 97.67 0.00 98.55 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.1017395864
96.69 0.03 97.99 0.00 94.87 0.09 93.38 0.09 97.67 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2315430504
96.71 0.03 97.99 0.00 95.05 0.18 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2204984440
96.74 0.03 97.99 0.00 95.23 0.18 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3370705117
96.76 0.03 97.99 0.00 95.41 0.18 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2625503199
96.79 0.03 97.99 0.00 95.59 0.18 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3183843381
96.81 0.03 97.99 0.00 95.77 0.18 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1486580418
96.84 0.03 97.99 0.00 95.77 0.00 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2970187719
96.86 0.03 97.99 0.00 95.77 0.00 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.605795620
96.89 0.03 97.99 0.00 95.77 0.00 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.3757136246
96.92 0.03 97.99 0.00 95.77 0.00 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.477003212
96.94 0.03 97.99 0.00 95.77 0.00 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 96.47 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.123215172
96.95 0.01 97.99 0.00 95.86 0.09 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2316374151
96.97 0.01 97.99 0.00 95.95 0.09 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3415440997
96.98 0.01 97.99 0.00 96.04 0.09 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4179246953
96.99 0.01 97.99 0.00 96.13 0.09 93.38 0.00 97.67 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3517070182
96.99 0.01 97.99 0.00 96.13 0.00 93.40 0.02 97.67 0.00 98.55 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1633093822

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2194988531
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1940534000
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.975331837
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.957957839
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1079369426
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.742097720
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.989368259
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.970059111
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3667549319
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2701358280
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2650560431
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2396450223
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1439903296
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2062279603
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2708819109
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3689467491
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2148804875
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3499913522
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1866071098
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3917991669
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.294594023
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1031530263
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1972098878
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1791155726
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.526019532
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.926405645
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2703879111
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1332355616
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2204627914
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1694790057
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3877797928
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1037725619
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3344468473
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4060976599
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3358178788
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4260082677
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4026768068
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3084092638
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.629452318
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4215326490
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/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1185729460
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/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4027418566



Total test records in report: 1001
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2538222563 Sep 04 04:49:07 PM UTC 24 Sep 04 04:49:10 PM UTC 24 12988999 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2315430504 Sep 04 04:49:06 PM UTC 24 Sep 04 04:49:10 PM UTC 24 149721718 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.801974423 Sep 04 04:49:09 PM UTC 24 Sep 04 04:49:12 PM UTC 24 62838378 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.1017395864 Sep 04 04:49:10 PM UTC 24 Sep 04 04:49:12 PM UTC 24 11193059 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.4255958873 Sep 04 04:49:10 PM UTC 24 Sep 04 04:49:20 PM UTC 24 346463280 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.1044341685 Sep 04 04:49:08 PM UTC 24 Sep 04 04:49:20 PM UTC 24 531123302 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.4256444560 Sep 04 04:49:09 PM UTC 24 Sep 04 04:49:20 PM UTC 24 248640308 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.4134941339 Sep 04 04:49:11 PM UTC 24 Sep 04 04:49:21 PM UTC 24 404589682 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1941206032 Sep 04 04:49:12 PM UTC 24 Sep 04 04:49:27 PM UTC 24 5336790943 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.9997669 Sep 04 04:49:08 PM UTC 24 Sep 04 04:49:30 PM UTC 24 226247841 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1633093822 Sep 04 04:49:11 PM UTC 24 Sep 04 04:49:33 PM UTC 24 504743962 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.373725376 Sep 04 04:49:21 PM UTC 24 Sep 04 04:49:35 PM UTC 24 728604407 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1849027672 Sep 04 04:49:21 PM UTC 24 Sep 04 04:49:37 PM UTC 24 5157788168 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1540370510 Sep 04 04:49:36 PM UTC 24 Sep 04 04:49:40 PM UTC 24 83194775 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3363736183 Sep 04 04:49:11 PM UTC 24 Sep 04 04:49:41 PM UTC 24 4650643307 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1526805793 Sep 04 04:49:38 PM UTC 24 Sep 04 04:49:42 PM UTC 24 98995617 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2196787043 Sep 04 04:49:09 PM UTC 24 Sep 04 04:49:42 PM UTC 24 633134000 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3543710213 Sep 04 04:49:41 PM UTC 24 Sep 04 04:49:43 PM UTC 24 14309532 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3050675329 Sep 04 04:49:21 PM UTC 24 Sep 04 04:49:43 PM UTC 24 483872856 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1007526067 Sep 04 04:49:43 PM UTC 24 Sep 04 04:49:47 PM UTC 24 106128163 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2970187719 Sep 04 04:49:48 PM UTC 24 Sep 04 04:49:51 PM UTC 24 12470283 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.377436596 Sep 04 04:49:22 PM UTC 24 Sep 04 04:49:52 PM UTC 24 2859711233 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.264427996 Sep 04 04:49:43 PM UTC 24 Sep 04 04:49:55 PM UTC 24 223910232 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.3090826472 Sep 04 04:49:43 PM UTC 24 Sep 04 04:49:58 PM UTC 24 888886032 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2747333036 Sep 04 04:49:44 PM UTC 24 Sep 04 04:50:00 PM UTC 24 412877462 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3743216275 Sep 04 04:49:44 PM UTC 24 Sep 04 04:50:01 PM UTC 24 812403899 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.1591996000 Sep 04 04:49:58 PM UTC 24 Sep 04 04:50:03 PM UTC 24 560863457 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.2309791111 Sep 04 04:49:52 PM UTC 24 Sep 04 04:50:05 PM UTC 24 1276476379 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4056445872 Sep 04 04:49:11 PM UTC 24 Sep 04 04:50:08 PM UTC 24 1524805577 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2093130444 Sep 04 04:50:01 PM UTC 24 Sep 04 04:50:08 PM UTC 24 259344952 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3387388753 Sep 04 04:49:11 PM UTC 24 Sep 04 04:50:10 PM UTC 24 1791479641 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.2114329476 Sep 04 04:49:12 PM UTC 24 Sep 04 04:50:11 PM UTC 24 1924030431 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1629195107 Sep 04 04:50:12 PM UTC 24 Sep 04 04:50:14 PM UTC 24 57692064 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3127947518 Sep 04 04:49:53 PM UTC 24 Sep 04 04:50:15 PM UTC 24 541770877 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.106913639 Sep 04 04:49:56 PM UTC 24 Sep 04 04:50:16 PM UTC 24 506274974 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.2694753690 Sep 04 04:50:15 PM UTC 24 Sep 04 04:50:18 PM UTC 24 148951753 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2102766559 Sep 04 04:50:16 PM UTC 24 Sep 04 04:50:18 PM UTC 24 13099029 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.2932591719 Sep 04 04:50:06 PM UTC 24 Sep 04 04:50:20 PM UTC 24 280458895 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.3546835306 Sep 04 04:49:43 PM UTC 24 Sep 04 04:50:20 PM UTC 24 636006679 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1306695288 Sep 04 04:49:34 PM UTC 24 Sep 04 04:50:21 PM UTC 24 221459382 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.947221719 Sep 04 04:50:19 PM UTC 24 Sep 04 04:50:22 PM UTC 24 79189344 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2222160298 Sep 04 04:50:03 PM UTC 24 Sep 04 04:50:24 PM UTC 24 4401290480 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.3757136246 Sep 04 04:50:23 PM UTC 24 Sep 04 04:50:25 PM UTC 24 33299239 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2693271556 Sep 04 04:50:05 PM UTC 24 Sep 04 04:50:28 PM UTC 24 580615185 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.605795620 Sep 04 04:50:04 PM UTC 24 Sep 04 04:50:30 PM UTC 24 1253082079 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3258693609 Sep 04 04:50:19 PM UTC 24 Sep 04 04:50:30 PM UTC 24 641578753 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3888813810 Sep 04 04:50:21 PM UTC 24 Sep 04 04:50:31 PM UTC 24 175970689 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2012369276 Sep 04 04:50:23 PM UTC 24 Sep 04 04:50:32 PM UTC 24 193998851 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2585770852 Sep 04 04:50:21 PM UTC 24 Sep 04 04:50:33 PM UTC 24 480012197 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.4082379292 Sep 04 04:50:31 PM UTC 24 Sep 04 04:50:35 PM UTC 24 35522739 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.1339202876 Sep 04 04:50:29 PM UTC 24 Sep 04 04:50:38 PM UTC 24 1443776018 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.4118177573 Sep 04 04:50:11 PM UTC 24 Sep 04 04:50:41 PM UTC 24 133472858 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.4042679204 Sep 04 04:50:23 PM UTC 24 Sep 04 04:50:42 PM UTC 24 471361817 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.4176860273 Sep 04 04:50:26 PM UTC 24 Sep 04 04:50:43 PM UTC 24 327421536 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2400072184 Sep 04 04:50:32 PM UTC 24 Sep 04 04:50:44 PM UTC 24 1385574570 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2825004230 Sep 04 04:50:36 PM UTC 24 Sep 04 04:50:46 PM UTC 24 653274001 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.4098236614 Sep 04 04:50:44 PM UTC 24 Sep 04 04:50:46 PM UTC 24 18568941 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1276888253 Sep 04 04:50:33 PM UTC 24 Sep 04 04:50:46 PM UTC 24 616350686 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3145921436 Sep 04 04:50:17 PM UTC 24 Sep 04 04:50:48 PM UTC 24 200434169 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.3182560701 Sep 04 04:50:46 PM UTC 24 Sep 04 04:50:49 PM UTC 24 32971773 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.872243035 Sep 04 04:50:47 PM UTC 24 Sep 04 04:50:49 PM UTC 24 25401911 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.4086352757 Sep 04 04:50:47 PM UTC 24 Sep 04 04:50:52 PM UTC 24 80610896 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.1435777264 Sep 04 04:50:53 PM UTC 24 Sep 04 04:50:55 PM UTC 24 15053807 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.3193038821 Sep 04 04:50:34 PM UTC 24 Sep 04 04:50:57 PM UTC 24 8939495244 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3275930311 Sep 04 04:50:37 PM UTC 24 Sep 04 04:50:58 PM UTC 24 433021579 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3666599988 Sep 04 04:50:47 PM UTC 24 Sep 04 04:50:59 PM UTC 24 77529685 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.3390649627 Sep 04 04:49:52 PM UTC 24 Sep 04 04:51:04 PM UTC 24 1190213840 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.3193371831 Sep 04 04:50:56 PM UTC 24 Sep 04 04:51:05 PM UTC 24 747652094 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.1963067734 Sep 04 04:50:47 PM UTC 24 Sep 04 04:51:06 PM UTC 24 880469061 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.237960933 Sep 04 04:50:49 PM UTC 24 Sep 04 04:51:08 PM UTC 24 356266226 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.523776881 Sep 04 04:50:50 PM UTC 24 Sep 04 04:51:11 PM UTC 24 1345579412 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.2940148126 Sep 04 04:50:59 PM UTC 24 Sep 04 04:51:12 PM UTC 24 263868980 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.1499074276 Sep 04 04:50:44 PM UTC 24 Sep 04 04:51:12 PM UTC 24 131120211 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3181875483 Sep 04 04:50:48 PM UTC 24 Sep 04 04:51:13 PM UTC 24 645242984 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.359467346 Sep 04 04:51:08 PM UTC 24 Sep 04 04:51:32 PM UTC 24 2151348520 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3402809439 Sep 04 04:49:56 PM UTC 24 Sep 04 04:51:17 PM UTC 24 10998338517 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1237467496 Sep 04 04:50:08 PM UTC 24 Sep 04 04:51:17 PM UTC 24 18059929701 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2236649308 Sep 04 04:51:15 PM UTC 24 Sep 04 04:51:18 PM UTC 24 35643619 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.3322670783 Sep 04 04:51:04 PM UTC 24 Sep 04 04:51:18 PM UTC 24 349321285 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.2517787819 Sep 04 04:51:18 PM UTC 24 Sep 04 04:51:22 PM UTC 24 29617173 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2613156685 Sep 04 04:51:18 PM UTC 24 Sep 04 04:51:21 PM UTC 24 51455571 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.420491510 Sep 04 04:51:09 PM UTC 24 Sep 04 04:51:21 PM UTC 24 407771346 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2405024866 Sep 04 04:51:12 PM UTC 24 Sep 04 04:51:22 PM UTC 24 261743103 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.3425622487 Sep 04 04:50:59 PM UTC 24 Sep 04 04:51:23 PM UTC 24 4643396721 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.2290671882 Sep 04 04:51:21 PM UTC 24 Sep 04 04:51:25 PM UTC 24 29454938 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2086316142 Sep 04 04:51:07 PM UTC 24 Sep 04 04:51:25 PM UTC 24 4173888858 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1508936705 Sep 04 04:51:24 PM UTC 24 Sep 04 04:51:27 PM UTC 24 32681652 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.1504511123 Sep 04 04:51:25 PM UTC 24 Sep 04 04:51:30 PM UTC 24 56956209 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.3776430462 Sep 04 04:51:19 PM UTC 24 Sep 04 04:51:33 PM UTC 24 90724213 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.1005509794 Sep 04 04:51:23 PM UTC 24 Sep 04 04:51:34 PM UTC 24 851351625 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.1681645587 Sep 04 04:51:34 PM UTC 24 Sep 04 04:51:38 PM UTC 24 242789666 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1469110277 Sep 04 04:51:18 PM UTC 24 Sep 04 04:51:40 PM UTC 24 174131002 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.3872378002 Sep 04 04:51:30 PM UTC 24 Sep 04 04:51:40 PM UTC 24 1104117636 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1016230772 Sep 04 04:51:23 PM UTC 24 Sep 04 04:51:42 PM UTC 24 324571348 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2742946052 Sep 04 04:51:35 PM UTC 24 Sep 04 04:51:42 PM UTC 24 524918972 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2543109926 Sep 04 04:50:31 PM UTC 24 Sep 04 04:51:48 PM UTC 24 2495310003 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.1455442577 Sep 04 04:51:23 PM UTC 24 Sep 04 04:51:49 PM UTC 24 1382257321 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1695620964 Sep 04 04:51:50 PM UTC 24 Sep 04 04:51:52 PM UTC 24 86617787 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.2961361157 Sep 04 04:51:03 PM UTC 24 Sep 04 04:51:53 PM UTC 24 2358481350 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2720463860 Sep 04 04:51:53 PM UTC 24 Sep 04 04:51:56 PM UTC 24 16647567 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.1135524565 Sep 04 04:51:06 PM UTC 24 Sep 04 04:51:56 PM UTC 24 12306359531 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.2414073501 Sep 04 04:51:51 PM UTC 24 Sep 04 04:51:57 PM UTC 24 104823297 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1617773004 Sep 04 04:51:27 PM UTC 24 Sep 04 04:51:58 PM UTC 24 2197909985 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2600629651 Sep 04 04:51:41 PM UTC 24 Sep 04 04:51:59 PM UTC 24 1426522077 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.921204440 Sep 04 04:51:15 PM UTC 24 Sep 04 04:51:59 PM UTC 24 435049750 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.4147640968 Sep 04 04:50:58 PM UTC 24 Sep 04 04:52:00 PM UTC 24 2204013509 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.1011042414 Sep 04 04:51:56 PM UTC 24 Sep 04 04:52:01 PM UTC 24 54148439 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.2365528957 Sep 04 04:51:41 PM UTC 24 Sep 04 04:52:01 PM UTC 24 366301944 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.3449167039 Sep 04 04:51:57 PM UTC 24 Sep 04 04:52:02 PM UTC 24 56286368 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.477003212 Sep 04 04:52:01 PM UTC 24 Sep 04 04:52:03 PM UTC 24 33137501 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3651913537 Sep 04 04:51:39 PM UTC 24 Sep 04 04:52:05 PM UTC 24 426349779 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3785306156 Sep 04 04:50:42 PM UTC 24 Sep 04 04:52:06 PM UTC 24 6498368152 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1092486487 Sep 04 04:52:03 PM UTC 24 Sep 04 04:52:08 PM UTC 24 78640109 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2373619700 Sep 04 04:52:01 PM UTC 24 Sep 04 04:52:08 PM UTC 24 1097864712 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2971006890 Sep 04 04:51:59 PM UTC 24 Sep 04 04:52:13 PM UTC 24 279561846 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2080308327 Sep 04 04:52:05 PM UTC 24 Sep 04 04:52:14 PM UTC 24 780796290 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1812817326 Sep 04 04:51:54 PM UTC 24 Sep 04 04:52:15 PM UTC 24 2937248966 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3471791376 Sep 04 04:52:16 PM UTC 24 Sep 04 04:52:18 PM UTC 24 30321000 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.828412569 Sep 04 04:50:25 PM UTC 24 Sep 04 04:52:19 PM UTC 24 7478744421 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.707751857 Sep 04 04:51:57 PM UTC 24 Sep 04 04:52:19 PM UTC 24 443466948 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.1117861973 Sep 04 04:52:11 PM UTC 24 Sep 04 04:52:21 PM UTC 24 1637628787 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.1120613786 Sep 04 04:52:09 PM UTC 24 Sep 04 04:52:21 PM UTC 24 231510086 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.620708169 Sep 04 04:52:02 PM UTC 24 Sep 04 04:52:21 PM UTC 24 272217453 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2840077427 Sep 04 04:52:19 PM UTC 24 Sep 04 04:52:22 PM UTC 24 31017750 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4042897612 Sep 04 04:52:20 PM UTC 24 Sep 04 04:52:23 PM UTC 24 53985557 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2128737710 Sep 04 04:51:50 PM UTC 24 Sep 04 04:52:24 PM UTC 24 392663071 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2529243428 Sep 04 04:51:36 PM UTC 24 Sep 04 04:52:25 PM UTC 24 5716408792 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1377916019 Sep 04 04:52:22 PM UTC 24 Sep 04 04:52:25 PM UTC 24 13971008 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.1828589451 Sep 04 04:52:06 PM UTC 24 Sep 04 04:52:25 PM UTC 24 4476671987 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3446576824 Sep 04 04:49:27 PM UTC 24 Sep 04 04:52:25 PM UTC 24 5044262393 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.1028839173 Sep 04 04:52:20 PM UTC 24 Sep 04 04:52:26 PM UTC 24 576002691 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3460699271 Sep 04 04:52:00 PM UTC 24 Sep 04 04:52:26 PM UTC 24 1011588281 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.779566478 Sep 04 04:52:24 PM UTC 24 Sep 04 04:52:26 PM UTC 24 23774304 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.91585428 Sep 04 04:52:08 PM UTC 24 Sep 04 04:52:27 PM UTC 24 1472257543 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2987215275 Sep 04 04:51:26 PM UTC 24 Sep 04 04:52:27 PM UTC 24 2537604311 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.4126705440 Sep 04 04:52:25 PM UTC 24 Sep 04 04:52:28 PM UTC 24 92587012 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3484334278 Sep 04 04:51:33 PM UTC 24 Sep 04 04:52:29 PM UTC 24 10447783592 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.821890248 Sep 04 04:52:07 PM UTC 24 Sep 04 04:52:29 PM UTC 24 6263298973 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2040630645 Sep 04 04:52:26 PM UTC 24 Sep 04 04:52:32 PM UTC 24 117972818 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.999564785 Sep 04 04:52:23 PM UTC 24 Sep 04 04:52:33 PM UTC 24 873045641 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.2977832216 Sep 04 04:52:22 PM UTC 24 Sep 04 04:52:33 PM UTC 24 437937368 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1766515322 Sep 04 04:52:42 PM UTC 24 Sep 04 04:52:51 PM UTC 24 306122526 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1595333824 Sep 04 04:52:33 PM UTC 24 Sep 04 04:52:36 PM UTC 24 46635325 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.709323007 Sep 04 04:52:28 PM UTC 24 Sep 04 04:52:37 PM UTC 24 179717867 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2337534160 Sep 04 04:52:35 PM UTC 24 Sep 04 04:52:37 PM UTC 24 40500220 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1270232084 Sep 04 04:52:35 PM UTC 24 Sep 04 04:52:38 PM UTC 24 29965428 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.426038840 Sep 04 04:52:24 PM UTC 24 Sep 04 04:52:40 PM UTC 24 2664711724 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1882397407 Sep 04 04:52:26 PM UTC 24 Sep 04 04:52:41 PM UTC 24 1198414598 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3589256123 Sep 04 04:52:28 PM UTC 24 Sep 04 04:52:41 PM UTC 24 1392127382 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.1559565448 Sep 04 04:52:26 PM UTC 24 Sep 04 04:52:52 PM UTC 24 589192120 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.3721941336 Sep 04 04:52:28 PM UTC 24 Sep 04 04:52:41 PM UTC 24 482712236 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.42422398 Sep 04 04:52:37 PM UTC 24 Sep 04 04:52:43 PM UTC 24 288255478 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.4018984950 Sep 04 04:52:41 PM UTC 24 Sep 04 04:52:44 PM UTC 24 13664974 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.1724366976 Sep 04 04:52:29 PM UTC 24 Sep 04 04:52:44 PM UTC 24 1026216109 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.567717329 Sep 04 04:52:02 PM UTC 24 Sep 04 04:52:45 PM UTC 24 925499780 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.4052140555 Sep 04 04:52:20 PM UTC 24 Sep 04 04:52:46 PM UTC 24 293172941 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3424784936 Sep 04 04:52:37 PM UTC 24 Sep 04 04:52:49 PM UTC 24 113391331 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.3707965005 Sep 04 04:52:38 PM UTC 24 Sep 04 04:52:51 PM UTC 24 3352120557 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.4099095760 Sep 04 04:52:39 PM UTC 24 Sep 04 04:52:52 PM UTC 24 234982626 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1003557612 Sep 04 04:52:38 PM UTC 24 Sep 04 04:52:52 PM UTC 24 2057113638 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3507661235 Sep 04 04:52:45 PM UTC 24 Sep 04 04:52:54 PM UTC 24 493704572 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2728313951 Sep 04 04:52:28 PM UTC 24 Sep 04 04:52:55 PM UTC 24 5802584915 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2800219536 Sep 04 04:52:30 PM UTC 24 Sep 04 04:52:55 PM UTC 24 835606872 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.2667409685 Sep 04 04:50:08 PM UTC 24 Sep 04 04:52:56 PM UTC 24 26732626647 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3976517346 Sep 04 04:52:05 PM UTC 24 Sep 04 04:52:56 PM UTC 24 1500761624 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.4111859960 Sep 04 04:52:53 PM UTC 24 Sep 04 04:52:56 PM UTC 24 40429344 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3020442854 Sep 04 04:52:37 PM UTC 24 Sep 04 04:52:57 PM UTC 24 696854171 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.3915781922 Sep 04 04:52:53 PM UTC 24 Sep 04 04:52:58 PM UTC 24 245197774 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2102313984 Sep 04 04:52:56 PM UTC 24 Sep 04 04:52:58 PM UTC 24 16214482 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2457529428 Sep 04 04:52:15 PM UTC 24 Sep 04 04:52:58 PM UTC 24 3661873607 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.2750542986 Sep 04 04:52:44 PM UTC 24 Sep 04 04:53:00 PM UTC 24 3115463308 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.4218227156 Sep 04 04:52:59 PM UTC 24 Sep 04 04:53:01 PM UTC 24 24886438 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.4020318961 Sep 04 04:52:45 PM UTC 24 Sep 04 04:53:01 PM UTC 24 2382034770 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3988292403 Sep 04 04:52:56 PM UTC 24 Sep 04 04:53:03 PM UTC 24 697393913 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.848048540 Sep 04 04:52:50 PM UTC 24 Sep 04 04:53:04 PM UTC 24 297329747 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.2115492550 Sep 04 04:52:59 PM UTC 24 Sep 04 04:53:04 PM UTC 24 457129544 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1106890087 Sep 04 04:52:48 PM UTC 24 Sep 04 04:53:05 PM UTC 24 3452496950 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1127283451 Sep 04 04:52:57 PM UTC 24 Sep 04 04:53:06 PM UTC 24 906381263 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1638146073 Sep 04 04:52:50 PM UTC 24 Sep 04 04:53:09 PM UTC 24 3156514033 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.1427591889 Sep 04 04:52:59 PM UTC 24 Sep 04 04:53:10 PM UTC 24 354182289 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.3236275563 Sep 04 04:52:43 PM UTC 24 Sep 04 04:53:10 PM UTC 24 2195046175 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.2755356713 Sep 04 04:53:04 PM UTC 24 Sep 04 04:53:11 PM UTC 24 700468250 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.534391457 Sep 04 04:53:02 PM UTC 24 Sep 04 04:53:13 PM UTC 24 2812710438 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.98256453 Sep 04 04:53:04 PM UTC 24 Sep 04 04:53:13 PM UTC 24 1102582271 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2990257589 Sep 04 04:52:26 PM UTC 24 Sep 04 04:53:13 PM UTC 24 3897295596 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3864829948 Sep 04 04:53:11 PM UTC 24 Sep 04 04:53:13 PM UTC 24 15980982 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1750146619 Sep 04 04:52:52 PM UTC 24 Sep 04 04:53:13 PM UTC 24 384179902 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1665154040 Sep 04 04:52:57 PM UTC 24 Sep 04 04:53:14 PM UTC 24 572607403 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.182820605 Sep 04 04:52:57 PM UTC 24 Sep 04 04:53:14 PM UTC 24 673453146 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1746046573 Sep 04 04:53:13 PM UTC 24 Sep 04 04:53:16 PM UTC 24 37001424 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4027418566 Sep 04 04:53:15 PM UTC 24 Sep 04 04:53:18 PM UTC 24 16937104 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3591065181 Sep 04 04:53:08 PM UTC 24 Sep 04 04:53:18 PM UTC 24 226841740 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.969089497 Sep 04 04:53:01 PM UTC 24 Sep 04 04:53:18 PM UTC 24 419749846 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1185729460 Sep 04 04:53:06 PM UTC 24 Sep 04 04:53:18 PM UTC 24 269207926 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.3591812161 Sep 04 04:53:15 PM UTC 24 Sep 04 04:53:19 PM UTC 24 61193360 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.123215172 Sep 04 04:53:19 PM UTC 24 Sep 04 04:53:21 PM UTC 24 13403257 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.798449098 Sep 04 04:53:10 PM UTC 24 Sep 04 04:53:22 PM UTC 24 808357857 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3941229667 Sep 04 04:52:43 PM UTC 24 Sep 04 04:53:24 PM UTC 24 1652955861 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2645752651 Sep 04 04:53:15 PM UTC 24 Sep 04 04:53:25 PM UTC 24 497238547 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.2792864028 Sep 04 04:52:45 PM UTC 24 Sep 04 04:53:25 PM UTC 24 3281008255 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.4107497543 Sep 04 04:53:15 PM UTC 24 Sep 04 04:53:25 PM UTC 24 571411437 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.556317817 Sep 04 04:53:15 PM UTC 24 Sep 04 04:53:27 PM UTC 24 543165980 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.581045061 Sep 04 04:52:56 PM UTC 24 Sep 04 04:53:28 PM UTC 24 247818219 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.3991563420 Sep 04 04:53:49 PM UTC 24 Sep 04 04:54:02 PM UTC 24 1571401496 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.2377851594 Sep 04 04:53:23 PM UTC 24 Sep 04 04:53:29 PM UTC 24 856749646 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.1277369775 Sep 04 04:53:19 PM UTC 24 Sep 04 04:53:29 PM UTC 24 499002026 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.3948070625 Sep 04 04:53:17 PM UTC 24 Sep 04 04:53:30 PM UTC 24 264080310 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3338347077 Sep 04 04:53:30 PM UTC 24 Sep 04 04:53:32 PM UTC 24 18074182 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1365484739 Sep 04 04:53:30 PM UTC 24 Sep 04 04:53:32 PM UTC 24 45645551 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.4084791590 Sep 04 04:53:30 PM UTC 24 Sep 04 04:53:33 PM UTC 24 37882039 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1263055955 Sep 04 04:52:26 PM UTC 24 Sep 04 04:53:33 PM UTC 24 1339286370 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1259275508 Sep 04 04:53:06 PM UTC 24 Sep 04 04:53:33 PM UTC 24 7189308487 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1950570301 Sep 04 04:53:20 PM UTC 24 Sep 04 04:53:37 PM UTC 24 310401122 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1690278753 Sep 04 04:53:33 PM UTC 24 Sep 04 04:53:37 PM UTC 24 184825748 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.1893172422 Sep 04 04:53:20 PM UTC 24 Sep 04 04:53:38 PM UTC 24 2644234813 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.296372751 Sep 04 04:53:26 PM UTC 24 Sep 04 04:53:40 PM UTC 24 1090097252 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2154982093 Sep 04 04:53:27 PM UTC 24 Sep 04 04:53:40 PM UTC 24 955117653 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3976985429 Sep 04 04:53:26 PM UTC 24 Sep 04 04:53:40 PM UTC 24 1248334973 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.4078805724 Sep 04 04:53:15 PM UTC 24 Sep 04 04:53:41 PM UTC 24 300161819 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1220092846 Sep 04 04:53:31 PM UTC 24 Sep 04 04:53:42 PM UTC 24 299141046 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1737140667 Sep 04 04:53:24 PM UTC 24 Sep 04 04:53:42 PM UTC 24 1043910583 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3699657741 Sep 04 04:53:34 PM UTC 24 Sep 04 04:53:43 PM UTC 24 249722668 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2652826944 Sep 04 04:53:34 PM UTC 24 Sep 04 04:53:44 PM UTC 24 610274665 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.4087067294 Sep 04 04:53:43 PM UTC 24 Sep 04 04:53:45 PM UTC 24 11575576 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.2599844514 Sep 04 04:53:34 PM UTC 24 Sep 04 04:53:47 PM UTC 24 831079858 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1411497011 Sep 04 04:53:44 PM UTC 24 Sep 04 04:53:47 PM UTC 24 22012212 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1515259607 Sep 04 04:53:38 PM UTC 24 Sep 04 04:53:48 PM UTC 24 1958516444 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1246134199 Sep 04 04:53:44 PM UTC 24 Sep 04 04:53:48 PM UTC 24 70618418 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3334177977 Sep 04 04:53:26 PM UTC 24 Sep 04 04:53:48 PM UTC 24 345535081 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2544517594 Sep 04 04:53:38 PM UTC 24 Sep 04 04:53:49 PM UTC 24 1966381775 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1028797798 Sep 04 04:53:48 PM UTC 24 Sep 04 04:53:51 PM UTC 24 23407333 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3757499190 Sep 04 04:53:42 PM UTC 24 Sep 04 04:53:54 PM UTC 24 314535203 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1180325544 Sep 04 04:53:42 PM UTC 24 Sep 04 04:53:55 PM UTC 24 3717828621 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3103143875 Sep 04 04:53:40 PM UTC 24 Sep 04 04:53:56 PM UTC 24 341778978 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.4111459432 Sep 04 04:53:00 PM UTC 24 Sep 04 04:53:59 PM UTC 24 2339961711 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1997537754 Sep 04 04:53:39 PM UTC 24 Sep 04 04:54:00 PM UTC 24 3069611056 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3940847154 Sep 04 04:53:48 PM UTC 24 Sep 04 04:54:00 PM UTC 24 235856667 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.1510432331 Sep 04 04:53:49 PM UTC 24 Sep 04 04:54:02 PM UTC 24 387886806 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2593088184 Sep 04 04:53:49 PM UTC 24 Sep 04 04:54:01 PM UTC 24 5004847942 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.3425266288 Sep 04 04:53:30 PM UTC 24 Sep 04 04:54:04 PM UTC 24 650242831 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.4021938343 Sep 04 04:53:51 PM UTC 24 Sep 04 04:54:06 PM UTC 24 1693920126 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.1772711349 Sep 04 04:54:04 PM UTC 24 Sep 04 04:54:07 PM UTC 24 21666252 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.4206933994 Sep 04 04:53:56 PM UTC 24 Sep 04 04:54:07 PM UTC 24 1310125898 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.2736892358 Sep 04 04:53:58 PM UTC 24 Sep 04 04:54:08 PM UTC 24 694173705 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3534838453 Sep 04 04:53:46 PM UTC 24 Sep 04 04:54:09 PM UTC 24 407895499 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3426779897 Sep 04 04:54:07 PM UTC 24 Sep 04 04:54:09 PM UTC 24 19762316 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.3880600559 Sep 04 04:54:05 PM UTC 24 Sep 04 04:54:09 PM UTC 24 29852005 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.110399193 Sep 04 04:54:11 PM UTC 24 Sep 04 04:54:13 PM UTC 24 74683850 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3733988391 Sep 04 04:54:01 PM UTC 24 Sep 04 04:54:14 PM UTC 24 5705028267 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2172411044 Sep 04 04:54:09 PM UTC 24 Sep 04 04:54:14 PM UTC 24 86188047 ps