Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	714216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

897990

1

T1

12

T2

276

T3

479

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1324813	1			T1	10		T2	331		T3	656
values[0x0]	143257	1			T1	7		T2	84		T3	96
values[0x1]	144136	1			T1	9		T2	74		T3	88

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	564420	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1047786

1

T1

17

T2

331

T3

547

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5659	1			T3	1		T14	11		T15	3
valid_sources[0x01]	5018	1			T2	3		T3	1		T14	8
valid_sources[0x02]	7203	1			T2	4		T3	3		T4	1
valid_sources[0x03]	7276	1			T2	2		T3	5		T14	6
valid_sources[0x04]	5382	1			T2	5		T3	1		T14	5
valid_sources[0x05]	6164	1			T2	1		T3	6		T13	1
valid_sources[0x06]	5243	1			T3	3		T4	2		T14	1
valid_sources[0x07]	5131	1			T3	1		T14	5		T15	7
valid_sources[0x08]	5058	1			T2	1		T3	5		T14	3
valid_sources[0x09]	5018	1			T3	1		T13	1		T14	6
valid_sources[0x0a]	9237	1			T2	2		T14	16		T15	3
valid_sources[0x0b]	10298	1			T2	3		T14	8		T15	6
valid_sources[0x0c]	5520	1			T2	2		T3	3		T6	1
valid_sources[0x0d]	5407	1			T2	1		T3	5		T14	8
valid_sources[0x0e]	11702	1			T2	2		T3	3		T14	4
valid_sources[0x0f]	5613	1			T3	5		T14	8		T15	2
valid_sources[0x10]	4875	1			T2	3		T14	6		T15	1
valid_sources[0x11]	7347	1			T2	3		T3	3		T14	9
valid_sources[0x12]	5329	1			T2	2		T3	1		T4	2
valid_sources[0x13]	5204	1			T2	1		T3	4		T4	1
valid_sources[0x14]	5928	1			T2	1		T3	1		T14	5
valid_sources[0x15]	4867	1			T13	1		T14	5		T15	4
valid_sources[0x16]	5484	1			T2	2		T4	1		T14	5
valid_sources[0x17]	5635	1			T2	4		T3	2		T4	2
valid_sources[0x18]	5525	1			T2	2		T3	3		T14	10
valid_sources[0x19]	6113	1			T2	3		T14	3		T15	9
valid_sources[0x1a]	6166	1			T3	4		T14	12		T15	1
valid_sources[0x1b]	5221	1			T2	2		T14	4		T15	11
valid_sources[0x1c]	6499	1			T2	1		T3	4		T14	13
valid_sources[0x1d]	6238	1			T2	2		T14	9		T15	11
valid_sources[0x1e]	5208	1			T2	1		T3	1		T14	11
valid_sources[0x1f]	4851	1			T3	5		T4	2		T14	7
valid_sources[0x20]	5033	1			T3	13		T14	11		T15	8
valid_sources[0x21]	5406	1			T2	4		T3	5		T4	1
valid_sources[0x22]	6320	1			T2	4		T14	8		T15	7
valid_sources[0x23]	5712	1			T2	2		T3	2		T14	10
valid_sources[0x24]	5398	1			T1	3		T2	3		T14	8
valid_sources[0x25]	5018	1			T2	2		T3	18		T13	1
valid_sources[0x26]	5241	1			T2	1		T3	3		T14	3
valid_sources[0x27]	5185	1			T3	1		T4	1		T14	2
valid_sources[0x28]	7521	1			T2	1		T3	8		T14	3
valid_sources[0x29]	5832	1			T2	1		T3	1		T14	7
valid_sources[0x2a]	5488	1			T2	1		T14	7		T15	6
valid_sources[0x2b]	5051	1			T2	1		T3	5		T4	1
valid_sources[0x2c]	4996	1			T3	4		T6	18		T14	1
valid_sources[0x2d]	8191	1			T2	1		T4	1		T14	8
valid_sources[0x2e]	10192	1			T2	3		T3	2		T14	6
valid_sources[0x2f]	5311	1			T3	9		T14	6		T15	14
valid_sources[0x30]	5635	1			T2	4		T3	2		T14	7
valid_sources[0x31]	8078	1			T2	2		T3	5		T14	8
valid_sources[0x32]	5193	1			T2	1		T14	10		T15	7
valid_sources[0x33]	5384	1			T13	1		T14	9		T15	1
valid_sources[0x34]	5102	1			T3	1		T14	6		T15	4
valid_sources[0x35]	4921	1			T2	1		T3	8		T4	1
valid_sources[0x36]	5373	1			T2	1		T3	4		T14	8
valid_sources[0x37]	8616	1			T3	7		T13	1		T14	8
valid_sources[0x38]	8861	1			T1	1		T2	1		T3	11
valid_sources[0x39]	4731	1			T2	3		T3	2		T14	5
valid_sources[0x3a]	4889	1			T2	1		T3	1		T13	1
valid_sources[0x3b]	6610	1			T2	2		T3	6		T14	4
valid_sources[0x3c]	20902	1			T2	4		T3	8		T14	14
valid_sources[0x3d]	6558	1			T2	1		T14	9		T15	10
valid_sources[0x3e]	7719	1			T2	1		T3	2		T14	8
valid_sources[0x3f]	5028	1			T2	3		T13	1		T14	3
valid_sources[0x40]	11185	1			T2	2		T3	2		T13	2
valid_sources[0x41]	4872	1			T2	6		T3	2		T14	4
valid_sources[0x42]	5092	1			T2	4		T14	2		T15	1
valid_sources[0x43]	5071	1			T3	3		T13	2		T14	8
valid_sources[0x44]	6684	1			T2	1		T3	1		T13	2
valid_sources[0x45]	5162	1			T2	2		T3	3		T14	6
valid_sources[0x46]	13202	1			T2	2		T3	3		T14	7
valid_sources[0x47]	5051	1			T2	3		T14	8		T15	4
valid_sources[0x48]	5538	1			T2	1		T14	6		T15	7
valid_sources[0x49]	5949	1			T2	1		T3	2		T14	8
valid_sources[0x4a]	4953	1			T2	1		T3	5		T4	1
valid_sources[0x4b]	5194	1			T2	9		T3	9		T14	13
valid_sources[0x4c]	5390	1			T2	3		T3	10		T14	5
valid_sources[0x4d]	5506	1			T2	4		T14	8		T15	1
valid_sources[0x4e]	5224	1			T2	5		T3	2		T4	1
valid_sources[0x4f]	6711	1			T3	5		T14	7		T15	5
valid_sources[0x50]	5731	1			T2	1		T3	1		T14	7
valid_sources[0x51]	5607	1			T2	1		T3	2		T13	3
valid_sources[0x52]	4881	1			T2	5		T3	3		T4	1
valid_sources[0x53]	5020	1			T2	3		T3	11		T4	1
valid_sources[0x54]	5454	1			T2	2		T3	4		T14	6
valid_sources[0x55]	6844	1			T1	2		T2	3		T3	3
valid_sources[0x56]	4859	1			T2	7		T3	8		T14	9
valid_sources[0x57]	5329	1			T2	1		T6	17		T13	1
valid_sources[0x58]	5294	1			T2	3		T3	6		T14	6
valid_sources[0x59]	5435	1			T2	3		T14	7		T15	7
valid_sources[0x5a]	6244	1			T3	8		T14	2		T15	10
valid_sources[0x5b]	5053	1			T2	5		T3	4		T14	5
valid_sources[0x5c]	5179	1			T2	4		T3	8		T4	3
valid_sources[0x5d]	4900	1			T2	3		T3	1		T14	5
valid_sources[0x5e]	5605	1			T3	1		T14	13		T15	2
valid_sources[0x5f]	6211	1			T1	1		T3	2		T14	6
valid_sources[0x60]	5368	1			T3	2		T6	14		T14	8
valid_sources[0x61]	6829	1			T3	7		T15	7		T16	35
valid_sources[0x62]	5138	1			T2	2		T14	5		T15	2
valid_sources[0x63]	5265	1			T2	4		T3	2		T4	2
valid_sources[0x64]	6458	1			T2	6		T14	7		T15	15
valid_sources[0x65]	6186	1			T2	3		T3	12		T14	4
valid_sources[0x66]	7077	1			T3	4		T11	1		T14	4
valid_sources[0x67]	8195	1			T3	3		T14	3		T15	11
valid_sources[0x68]	5234	1			T1	2		T2	1		T3	4
valid_sources[0x69]	4953	1			T3	2		T14	14		T15	5
valid_sources[0x6a]	5879	1			T3	1		T14	7		T15	2
valid_sources[0x6b]	6834	1			T2	1		T3	3		T14	6
valid_sources[0x6c]	5170	1			T2	2		T3	4		T4	1
valid_sources[0x6d]	5472	1			T2	5		T3	8		T14	5
valid_sources[0x6e]	6641	1			T3	1		T4	1		T14	7
valid_sources[0x6f]	5386	1			T3	6		T14	10		T15	3
valid_sources[0x70]	6775	1			T2	2		T3	1		T14	7
valid_sources[0x71]	5146	1			T2	3		T3	3		T14	3
valid_sources[0x72]	5494	1			T2	1		T3	3		T4	2
valid_sources[0x73]	6462	1			T2	1		T3	4		T14	7
valid_sources[0x74]	5120	1			T2	1		T13	1		T14	3
valid_sources[0x75]	5518	1			T3	5		T14	7		T15	9
valid_sources[0x76]	5188	1			T2	1		T3	1		T14	5
valid_sources[0x77]	5341	1			T2	1		T14	7		T15	6
valid_sources[0x78]	5205	1			T2	1		T14	9		T15	4
valid_sources[0x79]	4977	1			T2	1		T3	1		T14	10
valid_sources[0x7a]	6386	1			T2	6		T3	7		T14	11
valid_sources[0x7b]	5217	1			T2	1		T3	8		T6	11
valid_sources[0x7c]	7623	1			T2	2		T3	12		T4	1
valid_sources[0x7d]	5362	1			T2	1		T3	1		T4	2
valid_sources[0x7e]	8512	1			T2	3		T4	1		T14	5
valid_sources[0x7f]	5018	1			T2	5		T14	12		T15	8
valid_sources[0x80]	6488	1			T2	4		T3	1		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

650913

1

T2

149

T3

319

T4

30

values[0x0]

all_enables

biggest_size

124109

1

T1

5

T2

71

T3

81

values[0x1]

all_enables

biggest_size

122968

1

T1

7

T2

56

T3

79