Unified Coverage Report :: Module

Module : tlul_cmd_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host.u_cmd_intg_gen	100.00	100.00					100.00

Module Instance : tb.dut.u_tap_tlul_host.u_cmd_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.78	95.45	91.67			100.00	100.00	u_tap_tlul_host

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_data_gen	100.00	100.00
u_cmd_gen	100.00	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_cmd_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	46	4	4	100.00
CONT_ASSIGN	54	1	1	100.00



19                        tl_h2d_cmd_intg_t cmd;
20         1/1            assign cmd = extract_h2d_cmd_intg(tl_i);
           Tests:       T1 T2 T3 
21                        logic [H2DCmdMaxWidth-1:0] unused_cmd_payload;
22                      
23                        logic [H2DCmdIntgWidth-1:0] cmd_intg;
24                        prim_secded_inv_64_57_enc u_cmd_gen (
25                          .data_i(H2DCmdMaxWidth'(cmd)),
26                          .data_o({cmd_intg, unused_cmd_payload})
27                        );
28                      
29                        logic [top_pkg::TL_DW-1:0] data_final;
30                        logic [DataIntgWidth-1:0] data_intg;
31                      
32                        if (EnableDataIntgGen) begin : gen_data_intg
33         1/1              assign data_final = tl_i.a_data;
           Tests:       T5 T6 T7 
34                      
35                          logic [DataMaxWidth-1:0] unused_data;
36                          prim_secded_inv_39_32_enc u_data_gen (
37                            .data_i(DataMaxWidth'(data_final)),
38                            .data_o({data_intg, unused_data})
39                          );
40                        end else begin : gen_passthrough_data_intg
41                          assign data_final = tl_i.a_data;
42                          assign data_intg = tl_i.a_user.data_intg;
43                        end
44                      
45                        always_comb begin
46         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
47         1/1              tl_o.a_data = data_final;
           Tests:       T1 T2 T3 
48         1/1              tl_o.a_user.cmd_intg = cmd_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.a_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                      
53                        logic unused_tl;
54         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Module : tlul_cmd_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayMaxWidthCheck_A	816	816	0	0

PayMaxWidthCheck_A

Name	Attempts	Real Successes
Total	816	816
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T7	1	1
T11	1	1
T12	1	1
T13	1	1