Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	63363127	13296	0	0
claim_transition_if_regwen_rd_A	63363127	830	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63363127	13296	0	0
T49	489743	0	0	0
T50	294450	8	0	0
T51	29247	0	0	0
T57	205135	8	0	0
T69	28157	0	0	0
T98	0	2	0	0
T99	0	8	0	0
T107	0	16	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	11	0	0
T146	0	5	0	0
T147	0	9	0	0
T148	21631	0	0	0
T149	26841	0	0	0
T150	9520	0	0	0
T151	199849	0	0	0
T152	34981	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63363127	830	0	0
T105	0	13	0	0
T114	0	6	0	0
T121	0	51	0	0
T153	80576	5	0	0
T154	0	9	0	0
T155	0	6	0	0
T156	0	10	0	0
T157	0	2	0	0
T158	0	25	0	0
T159	0	2	0	0
T160	24788	0	0	0
T161	1032	0	0	0
T162	2592	0	0	0
T163	501531	0	0	0
T164	3589	0	0	0
T165	39214	0	0	0
T166	26535	0	0	0
T167	31942	0	0	0
T168	40424	0	0	0