Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61528249

1

T1

2266

T2

1150

T3

5207

auto[1]

1082179

1

T4

792

T7

392

T16

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61519961

1

T1

2266

T2

1150

T3

5207

auto[1]

1090467

1

T4

693

T7

392

T16

693

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5253123	1			T1	109		T2	109		T3	832
auto[IdleSt]	17272804	1			T1	265		T2	1041		T3	837
auto[ClkMuxSt]	29155	1			T1	1		T3	5		T4	15
auto[CntIncrSt]	28956	1			T1	1		T3	5		T4	15
auto[CntProgSt]	1492545	1			T1	711		T3	117		T4	257
auto[TransCheckSt]	22855	1			T1	1		T3	5		T14	1
auto[TokenHashSt]	17314295	1			T1	103		T3	2041		T14	179
auto[FlashRmaSt]	28162	1			T1	1		T3	30		T14	1
auto[TokenCheck0St]	10166	1			T1	1		T3	5		T14	1
auto[TokenCheck1St]	7397	1			T1	1		T3	5		T14	1
auto[TransProgSt]	354912	1			T1	165		T3	95		T14	632
auto[PostTransSt]	9920922	1			T1	907		T3	1203		T4	904
auto[ScrapSt]	113844	1			T3	27		T17	4		T12	749
auto[EscalateSt]	4456364	1			T4	1893		T7	3415		T16	1500
auto[InvalidSt]	6303607	1			T18	734		T34	753		T22	4259

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1321	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6303607	1			T18	734		T34	753		T22	4259
EscalateSt	4456364	1			T4	1893		T7	3415		T16	1500
ScrapSt	113844	1			T3	27		T17	4		T12	749
PostTransSt	9920922	1			T1	907		T3	1203		T4	904
TransProgSt	354912	1			T1	165		T3	95		T14	632
TokenCheck1St	7397	1			T1	1		T3	5		T14	1
TokenCheck0St	10166	1			T1	1		T3	5		T14	1
FlashRmaSt	28162	1			T1	1		T3	30		T14	1
TokenHashSt	17314295	1			T1	103		T3	2041		T14	179
TransCheckSt	22855	1			T1	1		T3	5		T14	1
CntProgSt	1492545	1			T1	711		T3	117		T4	257
CntIncrSt	28956	1			T1	1		T3	5		T4	15
ClkMuxSt	29155	1			T1	1		T3	5		T4	15
IdleSt	17272804	1			T1	265		T2	1041		T3	837
ResetSt	5253123	1			T1	109		T2	109		T3	832
arcs[ResetSt=>IdleSt]	42073	1			T1	1		T2	1		T3	6
arcs[IdleSt=>ScrapSt]	225	1			T3	1		T17	1		T12	1
arcs[IdleSt=>ClkMuxSt]	28986	1			T1	1		T3	5		T4	15
arcs[ClkMuxSt=>CntIncrSt]	28956	1			T1	1		T3	5		T4	15
arcs[CntIncrSt=>PostTransSt]	1296	1			T20	5		T48	15		T49	8
arcs[CntIncrSt=>CntProgSt]	27595	1			T1	1		T3	5		T4	15
arcs[CntProgSt=>PostTransSt]	3727	1			T4	15		T7	8		T16	12
arcs[CntProgSt=>TransCheckSt]	22855	1			T1	1		T3	5		T14	1
arcs[TransCheckSt=>PostTransSt]	3128	1			T20	6		T42	38		T45	41
arcs[TransCheckSt=>TokenHashSt]	19642	1			T1	1		T3	5		T14	1
arcs[TokenHashSt=>PostTransSt]	8681	1			T20	19		T42	13		T43	87
arcs[TokenHashSt=>FlashRmaSt]	10203	1			T1	1		T3	5		T14	1
arcs[FlashRmaSt=>TokenCheck0St]	10166	1			T1	1		T3	5		T14	1
arcs[TokenCheck0St=>PostTransSt]	2704	1			T20	9		T42	19		T46	17
arcs[TokenCheck0St=>TokenCheck1St]	7397	1			T1	1		T3	5		T14	1
arcs[TokenCheck1St=>PostTransSt]	636	1			T20	2		T42	10		T45	12
arcs[TransProgSt=>PostTransSt]	5953	1			T1	1		T3	5		T14	1
arcs[IdleSt=>EscalateSt]	135	1			T17	9		T65	4		T69	5
arcs[ClkMuxSt=>EscalateSt]	30	1			T65	1		T66	2		T67	3
arcs[CntIncrSt=>EscalateSt]	65	1			T68	2		T69	3		T70	2
arcs[CntProgSt=>EscalateSt]	1013	1			T17	20		T36	6		T68	31
arcs[TransCheckSt=>EscalateSt]	85	1			T17	2		T36	2		T65	2
arcs[TokenHashSt=>EscalateSt]	758	1			T17	6		T20	2		T36	29
arcs[FlashRmaSt=>EscalateSt]	37	1			T36	1		T69	1		T67	1
arcs[TokenCheck0St=>EscalateSt]	65	1			T36	1		T68	1		T69	2
arcs[TokenCheck1St=>EscalateSt]	30	1			T36	1		T70	1		T74	2
arcs[TransProgSt=>EscalateSt]	778	1			T17	14		T36	5		T68	15
arcs[PostTransSt=>EscalateSt]	4049	1			T4	15		T7	8		T16	12
arcs[InvalidSt=>EscalateSt]	9398	1			T18	4		T34	4		T22	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5252958	1			T1	109		T2	109		T3	832
auto[0]	auto[IdleSt]	17272711	1			T1	265		T2	1041		T3	837
auto[0]	auto[ClkMuxSt]	29140	1			T1	1		T3	5		T4	15
auto[0]	auto[CntIncrSt]	28912	1			T1	1		T3	5		T4	15
auto[0]	auto[CntProgSt]	1491866	1			T1	711		T3	117		T4	257
auto[0]	auto[TransCheckSt]	22799	1			T1	1		T3	5		T14	1
auto[0]	auto[TokenHashSt]	17313805	1			T1	103		T3	2041		T14	179
auto[0]	auto[FlashRmaSt]	28137	1			T1	1		T3	30		T14	1
auto[0]	auto[TokenCheck0St]	10121	1			T1	1		T3	5		T14	1
auto[0]	auto[TokenCheck1St]	7372	1			T1	1		T3	5		T14	1
auto[0]	auto[TransProgSt]	354415	1			T1	165		T3	95		T14	632
auto[0]	auto[PostTransSt]	9918807	1			T1	907		T3	1203		T4	896
auto[0]	auto[ScrapSt]	113819	1			T3	27		T17	3		T12	749
auto[0]	auto[EscalateSt]	3383142	1			T4	1109		T7	3027		T16	1010
auto[0]	auto[InvalidSt]	6298924	1			T18	731		T34	752		T22	4257
auto[1]	auto[ResetSt]	165	1			T17	1		T36	4		T68	4
auto[1]	auto[IdleSt]	93	1			T17	6		T65	4		T69	3
auto[1]	auto[ClkMuxSt]	15	1			T66	1		T67	2		T226	1
auto[1]	auto[CntIncrSt]	44	1			T68	2		T69	1		T70	2
auto[1]	auto[CntProgSt]	679	1			T17	12		T36	5		T68	24
auto[1]	auto[TransCheckSt]	56	1			T36	1		T65	2		T69	2
auto[1]	auto[TokenHashSt]	490	1			T17	6		T36	20		T68	4
auto[1]	auto[FlashRmaSt]	25	1			T36	1		T67	1		T226	2
auto[1]	auto[TokenCheck0St]	45	1			T36	1		T68	1		T69	2
auto[1]	auto[TokenCheck1St]	25	1			T36	1		T70	1		T74	1
auto[1]	auto[TransProgSt]	497	1			T17	11		T36	3		T68	10
auto[1]	auto[PostTransSt]	2115	1			T4	8		T7	4		T16	5
auto[1]	auto[ScrapSt]	25	1			T17	1		T70	1		T66	1
auto[1]	auto[EscalateSt]	1073222	1			T4	784		T7	388		T16	490
auto[1]	auto[InvalidSt]	4683	1			T18	3		T34	1		T22	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5252960	1			T1	109		T2	109		T3	832
auto[0]	auto[IdleSt]	17272701	1			T1	265		T2	1041		T3	837
auto[0]	auto[ClkMuxSt]	29132	1			T1	1		T3	5		T4	15
auto[0]	auto[CntIncrSt]	28912	1			T1	1		T3	5		T4	15
auto[0]	auto[CntProgSt]	1491863	1			T1	711		T3	117		T4	257
auto[0]	auto[TransCheckSt]	22803	1			T1	1		T3	5		T14	1
auto[0]	auto[TokenHashSt]	17313774	1			T1	103		T3	2041		T14	179
auto[0]	auto[FlashRmaSt]	28135	1			T1	1		T3	30		T14	1
auto[0]	auto[TokenCheck0St]	10124	1			T1	1		T3	5		T14	1
auto[0]	auto[TokenCheck1St]	7377	1			T1	1		T3	5		T14	1
auto[0]	auto[TransProgSt]	354382	1			T1	165		T3	95		T14	632
auto[0]	auto[PostTransSt]	9918897	1			T1	907		T3	1203		T4	897
auto[0]	auto[ScrapSt]	113809	1			T3	27		T17	4		T12	749
auto[0]	auto[EscalateSt]	3374879	1			T4	1207		T7	3027		T16	814
auto[0]	auto[InvalidSt]	6298892	1			T18	733		T34	750		T22	4257
auto[1]	auto[ResetSt]	163	1			T17	5		T36	5		T68	4
auto[1]	auto[IdleSt]	103	1			T17	7		T65	4		T69	5
auto[1]	auto[ClkMuxSt]	23	1			T65	1		T66	2		T67	1
auto[1]	auto[CntIncrSt]	44	1			T68	2		T69	3		T74	1
auto[1]	auto[CntProgSt]	682	1			T17	15		T36	3		T68	18
auto[1]	auto[TransCheckSt]	52	1			T17	2		T36	1		T65	2
auto[1]	auto[TokenHashSt]	521	1			T17	3		T20	2		T36	17
auto[1]	auto[FlashRmaSt]	27	1			T36	1		T69	1		T67	1
auto[1]	auto[TokenCheck0St]	42	1			T69	1		T66	1		T67	1
auto[1]	auto[TokenCheck1St]	20	1			T70	1		T74	2		T67	1
auto[1]	auto[TransProgSt]	530	1			T17	9		T36	4		T68	10
auto[1]	auto[PostTransSt]	2025	1			T4	7		T7	4		T16	7
auto[1]	auto[ScrapSt]	35	1			T65	1		T70	1		T74	1
auto[1]	auto[EscalateSt]	1081485	1			T4	686		T7	388		T16	686
auto[1]	auto[InvalidSt]	4715	1			T18	1		T34	3		T22	2