Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 97.99 96.22 93.40 100.00 98.55 98.76 96.29


Total tests in report: 1001
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
56.43 56.43 79.12 79.12 44.73 44.73 43.74 43.74 37.21 37.21 69.09 69.09 92.29 92.29 28.80 28.80 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.382041244
69.21 12.79 82.24 3.12 48.69 3.96 65.04 21.30 55.81 18.60 83.61 14.52 92.54 0.25 56.54 27.74 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3066858535
78.91 9.69 88.93 6.69 75.61 26.91 80.24 15.20 60.47 4.65 89.21 5.60 94.28 1.74 63.60 7.07 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3552547899
83.54 4.64 89.19 0.25 81.10 5.49 83.17 2.92 79.07 18.60 90.87 1.66 94.28 0.00 67.14 3.53 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3412576879
85.64 2.09 95.62 6.44 81.37 0.27 83.56 0.39 79.07 0.00 92.95 2.07 94.28 0.00 72.61 5.48 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2797185156
87.27 1.63 95.62 0.00 81.37 0.00 83.56 0.00 88.37 9.30 92.95 0.00 94.28 0.00 74.73 2.12 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.72891941
88.70 1.43 95.67 0.05 82.99 1.62 85.24 1.68 90.70 2.33 93.15 0.21 94.53 0.25 78.62 3.89 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2799116680
89.93 1.23 96.33 0.65 85.96 2.97 85.42 0.17 90.70 0.00 94.19 1.04 95.27 0.75 81.63 3.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3940592054
90.92 0.99 96.53 0.20 87.67 1.71 85.52 0.10 90.70 0.00 94.81 0.62 96.02 0.75 85.16 3.53 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.841408678
91.77 0.86 96.53 0.00 87.67 0.00 87.99 2.47 90.70 0.00 94.81 0.00 96.02 0.00 88.69 3.53 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.234165977
92.58 0.81 97.03 0.50 89.29 1.62 88.00 0.01 93.02 2.33 95.85 1.04 96.02 0.00 88.87 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2131807912
93.31 0.73 97.08 0.05 89.92 0.63 88.40 0.40 95.35 2.33 96.06 0.21 96.27 0.25 90.11 1.24 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.893349423
93.72 0.41 97.08 0.00 89.92 0.00 90.41 2.00 95.35 0.00 96.06 0.00 96.27 0.00 90.99 0.88 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.852710124
94.13 0.41 97.13 0.05 91.18 1.26 90.41 0.00 95.35 0.00 96.47 0.41 96.52 0.25 91.87 0.88 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2262466064
94.49 0.36 97.13 0.00 91.18 0.00 90.41 0.00 97.67 2.33 96.47 0.00 96.52 0.00 92.05 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.4003642745
94.82 0.33 97.13 0.00 91.18 0.00 90.41 0.00 100.00 2.33 96.47 0.00 96.52 0.00 92.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2563337738
95.15 0.33 97.23 0.10 91.18 0.00 90.60 0.19 100.00 0.00 96.89 0.41 96.52 0.00 93.64 1.59 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3782720859
95.44 0.29 97.64 0.40 92.08 0.90 91.08 0.49 100.00 0.00 97.10 0.21 96.52 0.00 93.64 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2194275567
95.67 0.24 97.64 0.00 92.35 0.27 92.28 1.19 100.00 0.00 97.30 0.21 96.52 0.00 93.64 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.1984929962
95.89 0.21 97.64 0.00 92.35 0.00 92.28 0.00 100.00 0.00 97.30 0.00 98.01 1.49 93.64 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.641990515
96.07 0.18 97.64 0.00 92.53 0.18 92.60 0.32 100.00 0.00 97.72 0.41 98.01 0.00 93.99 0.35 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.308340630
96.22 0.15 97.74 0.10 92.53 0.00 92.78 0.18 100.00 0.00 97.93 0.21 98.01 0.00 94.52 0.53 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.4231168723
96.34 0.13 97.74 0.00 93.43 0.90 92.78 0.00 100.00 0.00 97.93 0.00 98.01 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2854715530
96.46 0.12 97.89 0.15 93.43 0.00 92.84 0.06 100.00 0.00 98.13 0.21 98.26 0.25 94.70 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.117963688
96.58 0.12 97.89 0.00 94.06 0.63 92.84 0.00 100.00 0.00 98.13 0.00 98.26 0.00 94.88 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1749791951
96.64 0.06 97.89 0.00 94.06 0.00 93.27 0.43 100.00 0.00 98.13 0.00 98.26 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1050957701
96.70 0.06 97.99 0.10 94.15 0.09 93.27 0.00 100.00 0.00 98.34 0.21 98.26 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.882119951
96.75 0.05 97.99 0.00 94.51 0.36 93.27 0.00 100.00 0.00 98.34 0.00 98.26 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3601600183
96.80 0.05 97.99 0.00 94.69 0.18 93.27 0.00 100.00 0.00 98.34 0.00 98.26 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3956764315
96.84 0.04 97.99 0.00 94.78 0.09 93.27 0.00 100.00 0.00 98.55 0.21 98.26 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.4278188783
96.88 0.04 97.99 0.00 95.05 0.27 93.27 0.00 100.00 0.00 98.55 0.00 98.26 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1629580635
96.92 0.04 97.99 0.00 95.05 0.00 93.27 0.00 100.00 0.00 98.55 0.00 98.51 0.25 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3627656603
96.95 0.04 97.99 0.00 95.05 0.00 93.27 0.00 100.00 0.00 98.55 0.00 98.76 0.25 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1557788494
96.98 0.03 97.99 0.00 95.05 0.00 93.30 0.03 100.00 0.00 98.55 0.00 98.76 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.238989319
97.01 0.03 97.99 0.00 95.23 0.18 93.30 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3063510363
97.03 0.03 97.99 0.00 95.41 0.18 93.30 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.421555062
97.06 0.03 97.99 0.00 95.41 0.00 93.30 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1920624098
97.08 0.03 97.99 0.00 95.41 0.00 93.30 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.3332507283
97.11 0.03 97.99 0.00 95.41 0.00 93.30 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2207667733
97.13 0.03 97.99 0.00 95.41 0.00 93.30 0.00 100.00 0.00 98.55 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.613837741
97.16 0.03 97.99 0.00 95.41 0.00 93.30 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.1606870651
97.18 0.03 97.99 0.00 95.41 0.00 93.30 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3399530729
97.20 0.01 97.99 0.00 95.41 0.00 93.40 0.10 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.2618477449
97.21 0.01 97.99 0.00 95.50 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3936680081
97.22 0.01 97.99 0.00 95.59 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2860689742
97.24 0.01 97.99 0.00 95.68 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1011668853
97.25 0.01 97.99 0.00 95.77 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3029501596
97.26 0.01 97.99 0.00 95.86 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.489375376
97.28 0.01 97.99 0.00 95.95 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2635661060
97.29 0.01 97.99 0.00 96.04 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1921296944
97.30 0.01 97.99 0.00 96.13 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3176816952
97.31 0.01 97.99 0.00 96.22 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.76 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2977552420

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1884619159
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2810412664
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2088816424
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2738916252
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1033034651
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.634794180
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3950770694
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2842574975
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4165623490
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3976500045
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2622297205
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.121515057
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2035131151
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1413195727
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.333337849
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1015605414
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4117678495
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.668758300
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3576778322
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.242764121
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4165197738
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2588377339
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.36107432
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3734689455
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.686826614
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4023294174
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3167771154
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1188214657
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1525995989
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1060168044
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4034331679
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3494050458
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.147245149
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3088249183
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/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.190463576



Total test records in report: 1001
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1727810386 Sep 11 06:47:48 PM UTC 24 Sep 11 06:47:50 PM UTC 24 45337381 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.324691577 Sep 11 06:47:49 PM UTC 24 Sep 11 06:47:51 PM UTC 24 19855371 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.382041244 Sep 11 06:47:48 PM UTC 24 Sep 11 06:47:51 PM UTC 24 53701116 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1920624098 Sep 11 06:47:48 PM UTC 24 Sep 11 06:47:53 PM UTC 24 216921362 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.238989319 Sep 11 06:47:51 PM UTC 24 Sep 11 06:47:53 PM UTC 24 19550024 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.1597468885 Sep 11 06:47:51 PM UTC 24 Sep 11 06:47:53 PM UTC 24 64305703 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1255336203 Sep 11 06:47:51 PM UTC 24 Sep 11 06:47:53 PM UTC 24 94801594 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2194275567 Sep 11 06:47:51 PM UTC 24 Sep 11 06:47:53 PM UTC 24 30009511 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.2843275448 Sep 11 06:47:51 PM UTC 24 Sep 11 06:47:54 PM UTC 24 27449362 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.4231168723 Sep 11 06:47:49 PM UTC 24 Sep 11 06:47:54 PM UTC 24 2359144177 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1855508016 Sep 11 06:47:51 PM UTC 24 Sep 11 06:47:55 PM UTC 24 873864489 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2180121740 Sep 11 06:47:48 PM UTC 24 Sep 11 06:47:55 PM UTC 24 231655718 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.308340630 Sep 11 06:47:48 PM UTC 24 Sep 11 06:47:57 PM UTC 24 87684698 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3517968482 Sep 11 06:47:49 PM UTC 24 Sep 11 06:47:57 PM UTC 24 734067255 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3066858535 Sep 11 06:47:48 PM UTC 24 Sep 11 06:47:57 PM UTC 24 439566930 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3940592054 Sep 11 06:47:50 PM UTC 24 Sep 11 06:47:58 PM UTC 24 1361260263 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.2228688580 Sep 11 06:47:55 PM UTC 24 Sep 11 06:47:58 PM UTC 24 29787631 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1376163140 Sep 11 06:47:49 PM UTC 24 Sep 11 06:47:59 PM UTC 24 854557989 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3634883355 Sep 11 06:47:51 PM UTC 24 Sep 11 06:47:59 PM UTC 24 207298156 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.721122937 Sep 11 06:47:57 PM UTC 24 Sep 11 06:47:59 PM UTC 24 12347217 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.4087091804 Sep 11 06:47:52 PM UTC 24 Sep 11 06:48:00 PM UTC 24 282313258 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3552547899 Sep 11 06:47:52 PM UTC 24 Sep 11 06:48:00 PM UTC 24 300732800 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.692976342 Sep 11 06:47:52 PM UTC 24 Sep 11 06:48:00 PM UTC 24 390327984 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.869102411 Sep 11 06:47:54 PM UTC 24 Sep 11 06:48:01 PM UTC 24 559291445 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3412576879 Sep 11 06:47:51 PM UTC 24 Sep 11 06:48:02 PM UTC 24 822163444 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2207667733 Sep 11 06:48:01 PM UTC 24 Sep 11 06:48:03 PM UTC 24 10919439 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.117963688 Sep 11 06:47:51 PM UTC 24 Sep 11 06:48:03 PM UTC 24 1341783583 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.13002947 Sep 11 06:47:56 PM UTC 24 Sep 11 06:48:03 PM UTC 24 208745791 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3782720859 Sep 11 06:47:51 PM UTC 24 Sep 11 06:48:03 PM UTC 24 332153483 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.13699011 Sep 11 06:47:59 PM UTC 24 Sep 11 06:48:03 PM UTC 24 183848698 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4205279910 Sep 11 06:48:01 PM UTC 24 Sep 11 06:48:05 PM UTC 24 193373361 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3709779480 Sep 11 06:47:51 PM UTC 24 Sep 11 06:48:05 PM UTC 24 420242093 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2797185156 Sep 11 06:47:51 PM UTC 24 Sep 11 06:48:06 PM UTC 24 1632234594 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3451787568 Sep 11 06:47:54 PM UTC 24 Sep 11 06:48:06 PM UTC 24 1385166711 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2305136426 Sep 11 06:47:59 PM UTC 24 Sep 11 06:48:07 PM UTC 24 976209633 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.1240236782 Sep 11 06:47:54 PM UTC 24 Sep 11 06:48:07 PM UTC 24 920065606 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.1816178311 Sep 11 06:47:59 PM UTC 24 Sep 11 06:48:07 PM UTC 24 60273766 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.348821700 Sep 11 06:47:54 PM UTC 24 Sep 11 06:48:07 PM UTC 24 2017007108 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.1315891260 Sep 11 06:47:54 PM UTC 24 Sep 11 06:48:07 PM UTC 24 910259153 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.3332507283 Sep 11 06:47:54 PM UTC 24 Sep 11 06:48:08 PM UTC 24 325902715 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2540874245 Sep 11 06:48:01 PM UTC 24 Sep 11 06:48:08 PM UTC 24 157699136 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2131807912 Sep 11 06:48:06 PM UTC 24 Sep 11 06:48:08 PM UTC 24 40184312 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.2985368615 Sep 11 06:48:06 PM UTC 24 Sep 11 06:48:08 PM UTC 24 49116114 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1104188818 Sep 11 06:47:49 PM UTC 24 Sep 11 06:48:09 PM UTC 24 2265734929 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.3173258415 Sep 11 06:47:51 PM UTC 24 Sep 11 06:48:09 PM UTC 24 395553418 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.4030544606 Sep 11 06:47:59 PM UTC 24 Sep 11 06:48:10 PM UTC 24 226542089 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2552896314 Sep 11 06:48:06 PM UTC 24 Sep 11 06:48:10 PM UTC 24 220530654 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2401443476 Sep 11 06:48:01 PM UTC 24 Sep 11 06:48:11 PM UTC 24 709450395 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3830494296 Sep 11 06:47:59 PM UTC 24 Sep 11 06:48:11 PM UTC 24 297028555 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.4165511608 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:11 PM UTC 24 42376306 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.2090541065 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:12 PM UTC 24 47856796 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1566857435 Sep 11 06:48:03 PM UTC 24 Sep 11 06:48:13 PM UTC 24 359886890 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.315565196 Sep 11 06:47:48 PM UTC 24 Sep 11 06:48:14 PM UTC 24 228055577 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.528274266 Sep 11 06:48:03 PM UTC 24 Sep 11 06:48:15 PM UTC 24 1449449111 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3804085960 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:16 PM UTC 24 936153777 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.3489269624 Sep 11 06:48:14 PM UTC 24 Sep 11 06:48:16 PM UTC 24 16159434 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2955346200 Sep 11 06:48:11 PM UTC 24 Sep 11 06:48:17 PM UTC 24 285122430 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.94977667 Sep 11 06:47:54 PM UTC 24 Sep 11 06:48:17 PM UTC 24 1059204486 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.613837741 Sep 11 06:48:01 PM UTC 24 Sep 11 06:48:18 PM UTC 24 1655387402 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3939918137 Sep 11 06:48:03 PM UTC 24 Sep 11 06:48:18 PM UTC 24 1670867881 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.568612288 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:18 PM UTC 24 388609841 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1608065430 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:18 PM UTC 24 304107883 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3860119323 Sep 11 06:48:12 PM UTC 24 Sep 11 06:48:19 PM UTC 24 908163077 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1324170362 Sep 11 06:48:16 PM UTC 24 Sep 11 06:48:19 PM UTC 24 40477836 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3046270297 Sep 11 06:47:51 PM UTC 24 Sep 11 06:48:19 PM UTC 24 4376949222 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.2062629324 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:19 PM UTC 24 1080775100 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1426920234 Sep 11 06:48:03 PM UTC 24 Sep 11 06:48:20 PM UTC 24 1380057749 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.337468769 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:20 PM UTC 24 164329968 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.2268363837 Sep 11 06:48:19 PM UTC 24 Sep 11 06:48:23 PM UTC 24 67283707 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.3735526903 Sep 11 06:48:11 PM UTC 24 Sep 11 06:48:23 PM UTC 24 1752621340 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.517835172 Sep 11 06:48:16 PM UTC 24 Sep 11 06:48:21 PM UTC 24 638624312 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2245692237 Sep 11 06:47:51 PM UTC 24 Sep 11 06:48:21 PM UTC 24 683352483 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.3489016701 Sep 11 06:48:03 PM UTC 24 Sep 11 06:48:21 PM UTC 24 446268174 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.815054703 Sep 11 06:48:19 PM UTC 24 Sep 11 06:48:21 PM UTC 24 11916599 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.1096004856 Sep 11 06:48:16 PM UTC 24 Sep 11 06:48:21 PM UTC 24 177565232 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.3146138374 Sep 11 06:48:12 PM UTC 24 Sep 11 06:48:22 PM UTC 24 682906806 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.2831966702 Sep 11 06:47:58 PM UTC 24 Sep 11 06:48:22 PM UTC 24 468926222 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.3256591532 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:23 PM UTC 24 806446103 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.3140264302 Sep 11 06:48:24 PM UTC 24 Sep 11 06:48:29 PM UTC 24 949269556 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2832375179 Sep 11 06:48:22 PM UTC 24 Sep 11 06:48:24 PM UTC 24 247108054 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2693490078 Sep 11 06:48:22 PM UTC 24 Sep 11 06:48:25 PM UTC 24 21351753 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2022030379 Sep 11 06:48:19 PM UTC 24 Sep 11 06:48:26 PM UTC 24 1755418069 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2696681352 Sep 11 06:48:24 PM UTC 24 Sep 11 06:48:27 PM UTC 24 21746872 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.2817688847 Sep 11 06:48:19 PM UTC 24 Sep 11 06:48:27 PM UTC 24 468992933 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1133656404 Sep 11 06:48:11 PM UTC 24 Sep 11 06:48:27 PM UTC 24 3382588045 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.1003523083 Sep 11 06:48:25 PM UTC 24 Sep 11 06:48:29 PM UTC 24 57869484 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.3778576899 Sep 11 06:48:22 PM UTC 24 Sep 11 06:48:29 PM UTC 24 198264990 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.1606870651 Sep 11 06:48:27 PM UTC 24 Sep 11 06:48:29 PM UTC 24 30571524 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1953535351 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:30 PM UTC 24 2054628181 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2170710993 Sep 11 06:48:19 PM UTC 24 Sep 11 06:48:30 PM UTC 24 1547154571 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.3239284695 Sep 11 06:48:12 PM UTC 24 Sep 11 06:48:32 PM UTC 24 439951648 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2270816943 Sep 11 06:48:25 PM UTC 24 Sep 11 06:48:32 PM UTC 24 71725604 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.1303536275 Sep 11 06:48:19 PM UTC 24 Sep 11 06:48:32 PM UTC 24 1409082982 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1980262461 Sep 11 06:48:22 PM UTC 24 Sep 11 06:48:33 PM UTC 24 397239151 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.243079818 Sep 11 06:47:49 PM UTC 24 Sep 11 06:48:34 PM UTC 24 1146449810 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.1909485873 Sep 11 06:48:27 PM UTC 24 Sep 11 06:48:34 PM UTC 24 1162348309 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2247149502 Sep 11 06:48:32 PM UTC 24 Sep 11 06:48:34 PM UTC 24 68881726 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.1550512292 Sep 11 06:48:25 PM UTC 24 Sep 11 06:48:34 PM UTC 24 194381748 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3138210314 Sep 11 06:48:29 PM UTC 24 Sep 11 06:48:37 PM UTC 24 2698400395 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.87390411 Sep 11 06:48:35 PM UTC 24 Sep 11 06:48:37 PM UTC 24 11882502 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.502781194 Sep 11 06:48:06 PM UTC 24 Sep 11 06:48:38 PM UTC 24 439752388 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.1955674449 Sep 11 06:48:29 PM UTC 24 Sep 11 06:48:38 PM UTC 24 1799895642 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.893349423 Sep 11 06:47:51 PM UTC 24 Sep 11 06:48:38 PM UTC 24 388862489 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.2486724170 Sep 11 06:48:35 PM UTC 24 Sep 11 06:48:39 PM UTC 24 48958770 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.4173858335 Sep 11 06:48:37 PM UTC 24 Sep 11 06:48:39 PM UTC 24 21062209 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2786790267 Sep 11 06:48:27 PM UTC 24 Sep 11 06:48:39 PM UTC 24 624758105 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.3075002410 Sep 11 06:48:35 PM UTC 24 Sep 11 06:48:39 PM UTC 24 45371027 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.3101596543 Sep 11 06:48:25 PM UTC 24 Sep 11 06:48:40 PM UTC 24 1220593206 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.234165977 Sep 11 06:47:54 PM UTC 24 Sep 11 06:49:05 PM UTC 24 3244518863 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2455246231 Sep 11 06:48:29 PM UTC 24 Sep 11 06:48:40 PM UTC 24 4831594836 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1227343256 Sep 11 06:48:16 PM UTC 24 Sep 11 06:48:41 PM UTC 24 1153594660 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.224601673 Sep 11 06:48:22 PM UTC 24 Sep 11 06:48:41 PM UTC 24 423691635 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.450829788 Sep 11 06:48:22 PM UTC 24 Sep 11 06:48:41 PM UTC 24 2909642866 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1514990878 Sep 11 06:48:32 PM UTC 24 Sep 11 06:48:42 PM UTC 24 864228031 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3914174133 Sep 11 06:48:32 PM UTC 24 Sep 11 06:48:43 PM UTC 24 300271330 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.580868411 Sep 11 06:48:32 PM UTC 24 Sep 11 06:48:43 PM UTC 24 1438378332 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.4083595481 Sep 11 06:48:38 PM UTC 24 Sep 11 06:48:43 PM UTC 24 362536976 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.2852611854 Sep 11 06:48:35 PM UTC 24 Sep 11 06:48:44 PM UTC 24 1340720399 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.307119845 Sep 11 06:48:35 PM UTC 24 Sep 11 06:48:45 PM UTC 24 236705663 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3560390735 Sep 11 06:48:35 PM UTC 24 Sep 11 06:48:45 PM UTC 24 62686835 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.1024609398 Sep 11 06:48:25 PM UTC 24 Sep 11 06:48:46 PM UTC 24 684040164 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2915178575 Sep 11 06:48:41 PM UTC 24 Sep 11 06:48:46 PM UTC 24 239227018 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.3596502476 Sep 11 06:48:44 PM UTC 24 Sep 11 06:48:46 PM UTC 24 25922819 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2193488454 Sep 11 06:48:44 PM UTC 24 Sep 11 06:48:46 PM UTC 24 26350510 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1780812377 Sep 11 06:48:41 PM UTC 24 Sep 11 06:48:46 PM UTC 24 795371840 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.101003375 Sep 11 06:48:22 PM UTC 24 Sep 11 06:49:05 PM UTC 24 14126330359 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.4273774401 Sep 11 06:48:27 PM UTC 24 Sep 11 06:48:48 PM UTC 24 2595007181 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3477276681 Sep 11 06:48:44 PM UTC 24 Sep 11 06:48:48 PM UTC 24 32656131 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1633786044 Sep 11 06:48:44 PM UTC 24 Sep 11 06:48:48 PM UTC 24 89840450 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.148067413 Sep 11 06:48:47 PM UTC 24 Sep 11 06:48:49 PM UTC 24 78843709 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.3411482273 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:49 PM UTC 24 1313838779 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2430001973 Sep 11 06:48:22 PM UTC 24 Sep 11 06:48:49 PM UTC 24 1925068632 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.1682216838 Sep 11 06:48:38 PM UTC 24 Sep 11 06:48:49 PM UTC 24 1199224708 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.215694891 Sep 11 06:48:09 PM UTC 24 Sep 11 06:48:50 PM UTC 24 8323750422 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.509411953 Sep 11 06:48:41 PM UTC 24 Sep 11 06:48:50 PM UTC 24 1011440308 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.3970003189 Sep 11 06:48:48 PM UTC 24 Sep 11 06:48:52 PM UTC 24 705069534 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2928956151 Sep 11 06:48:41 PM UTC 24 Sep 11 06:48:52 PM UTC 24 322387186 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2593935063 Sep 11 06:48:47 PM UTC 24 Sep 11 06:48:52 PM UTC 24 311864026 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.1501703892 Sep 11 06:48:44 PM UTC 24 Sep 11 06:48:53 PM UTC 24 45993347 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.1622883651 Sep 11 06:48:51 PM UTC 24 Sep 11 06:48:53 PM UTC 24 45387458 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2396036333 Sep 11 06:48:14 PM UTC 24 Sep 11 06:48:54 PM UTC 24 184519255 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.2966031377 Sep 11 06:48:21 PM UTC 24 Sep 11 06:48:54 PM UTC 24 669056726 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1541038595 Sep 11 06:47:55 PM UTC 24 Sep 11 06:48:54 PM UTC 24 469822129 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.3475176129 Sep 11 06:48:52 PM UTC 24 Sep 11 06:48:54 PM UTC 24 25342105 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.806236080 Sep 11 06:48:53 PM UTC 24 Sep 11 06:48:56 PM UTC 24 25251397 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3098659324 Sep 11 06:48:41 PM UTC 24 Sep 11 06:48:56 PM UTC 24 260941829 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2203288013 Sep 11 06:48:01 PM UTC 24 Sep 11 06:48:56 PM UTC 24 7651510598 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3616979395 Sep 11 06:48:38 PM UTC 24 Sep 11 06:48:57 PM UTC 24 702436988 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1615465046 Sep 11 06:48:37 PM UTC 24 Sep 11 06:48:57 PM UTC 24 3075094510 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1456332081 Sep 11 06:48:46 PM UTC 24 Sep 11 06:48:58 PM UTC 24 660799559 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.86670360 Sep 11 06:48:46 PM UTC 24 Sep 11 06:48:58 PM UTC 24 1479669749 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1132165201 Sep 11 06:48:56 PM UTC 24 Sep 11 06:48:58 PM UTC 24 87211934 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3349067894 Sep 11 06:48:54 PM UTC 24 Sep 11 06:48:58 PM UTC 24 148624192 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1871197091 Sep 11 06:48:49 PM UTC 24 Sep 11 06:48:58 PM UTC 24 718695884 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.660848565 Sep 11 06:48:53 PM UTC 24 Sep 11 06:49:00 PM UTC 24 107857951 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.3570586085 Sep 11 06:48:46 PM UTC 24 Sep 11 06:49:00 PM UTC 24 356743110 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1910677450 Sep 11 06:48:25 PM UTC 24 Sep 11 06:49:02 PM UTC 24 174555760 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1027532935 Sep 11 06:48:41 PM UTC 24 Sep 11 06:49:02 PM UTC 24 2458468043 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.1833335314 Sep 11 06:48:48 PM UTC 24 Sep 11 06:49:03 PM UTC 24 3503706521 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.3221477900 Sep 11 06:48:35 PM UTC 24 Sep 11 06:49:05 PM UTC 24 675633184 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3217781215 Sep 11 06:49:03 PM UTC 24 Sep 11 06:49:06 PM UTC 24 52612715 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.2221671043 Sep 11 06:48:47 PM UTC 24 Sep 11 06:49:06 PM UTC 24 2339560066 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.4029651087 Sep 11 06:49:03 PM UTC 24 Sep 11 06:49:07 PM UTC 24 49537677 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1565603787 Sep 11 06:48:51 PM UTC 24 Sep 11 06:49:07 PM UTC 24 487343555 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.190463576 Sep 11 06:49:04 PM UTC 24 Sep 11 06:49:07 PM UTC 24 44888011 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.852710124 Sep 11 06:48:01 PM UTC 24 Sep 11 06:49:07 PM UTC 24 1694434182 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.1884906038 Sep 11 06:48:54 PM UTC 24 Sep 11 06:49:07 PM UTC 24 3707444873 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3745223001 Sep 11 06:48:49 PM UTC 24 Sep 11 06:49:07 PM UTC 24 809510876 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3594389735 Sep 11 06:48:56 PM UTC 24 Sep 11 06:49:08 PM UTC 24 825941165 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.72891941 Sep 11 06:48:56 PM UTC 24 Sep 11 06:49:08 PM UTC 24 1308251171 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.1553649411 Sep 11 06:48:47 PM UTC 24 Sep 11 06:49:08 PM UTC 24 3435907511 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.3967406088 Sep 11 06:48:56 PM UTC 24 Sep 11 06:49:08 PM UTC 24 325768494 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.4112516955 Sep 11 06:48:57 PM UTC 24 Sep 11 06:49:10 PM UTC 24 619783647 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.4288715949 Sep 11 06:48:58 PM UTC 24 Sep 11 06:49:10 PM UTC 24 378025833 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.2613687478 Sep 11 06:47:52 PM UTC 24 Sep 11 06:49:10 PM UTC 24 2086412507 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.1466730047 Sep 11 06:48:49 PM UTC 24 Sep 11 06:49:11 PM UTC 24 2134271998 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3399530729 Sep 11 06:49:08 PM UTC 24 Sep 11 06:49:11 PM UTC 24 29483747 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3208333659 Sep 11 06:49:08 PM UTC 24 Sep 11 06:49:11 PM UTC 24 108233629 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.3833341 Sep 11 06:49:07 PM UTC 24 Sep 11 06:49:11 PM UTC 24 56867336 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1221590455 Sep 11 06:49:00 PM UTC 24 Sep 11 06:49:12 PM UTC 24 338582515 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.3546773327 Sep 11 06:47:49 PM UTC 24 Sep 11 06:49:12 PM UTC 24 3979217657 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.1798837834 Sep 11 06:48:48 PM UTC 24 Sep 11 06:49:13 PM UTC 24 896070742 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3660804941 Sep 11 06:49:10 PM UTC 24 Sep 11 06:49:14 PM UTC 24 123936542 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2526064186 Sep 11 06:49:06 PM UTC 24 Sep 11 06:49:15 PM UTC 24 97771368 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2589845175 Sep 11 06:48:22 PM UTC 24 Sep 11 06:49:15 PM UTC 24 951005750 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.411820991 Sep 11 06:49:13 PM UTC 24 Sep 11 06:49:15 PM UTC 24 49033699 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3282221153 Sep 11 06:49:00 PM UTC 24 Sep 11 06:49:16 PM UTC 24 13291119813 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.448745906 Sep 11 06:49:13 PM UTC 24 Sep 11 06:49:16 PM UTC 24 32634260 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.2176875162 Sep 11 06:49:13 PM UTC 24 Sep 11 06:49:16 PM UTC 24 44460917 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.11880019 Sep 11 06:49:33 PM UTC 24 Sep 11 06:49:39 PM UTC 24 113949496 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3679676490 Sep 11 06:49:09 PM UTC 24 Sep 11 06:49:16 PM UTC 24 390721146 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.423081408 Sep 11 06:48:57 PM UTC 24 Sep 11 06:49:16 PM UTC 24 361201110 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.4000392523 Sep 11 06:49:07 PM UTC 24 Sep 11 06:49:17 PM UTC 24 205298440 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.113915345 Sep 11 06:49:33 PM UTC 24 Sep 11 06:49:38 PM UTC 24 99154387 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.983484691 Sep 11 06:49:09 PM UTC 24 Sep 11 06:49:18 PM UTC 24 1599908080 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.748798272 Sep 11 06:49:00 PM UTC 24 Sep 11 06:49:18 PM UTC 24 9214847760 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3427447584 Sep 11 06:49:00 PM UTC 24 Sep 11 06:49:19 PM UTC 24 2414908518 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.764067843 Sep 11 06:48:19 PM UTC 24 Sep 11 06:49:19 PM UTC 24 2142339082 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.76100702 Sep 11 06:49:15 PM UTC 24 Sep 11 06:49:20 PM UTC 24 69538970 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3215166023 Sep 11 06:48:44 PM UTC 24 Sep 11 06:49:22 PM UTC 24 1312855142 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1550421892 Sep 11 06:49:07 PM UTC 24 Sep 11 06:49:22 PM UTC 24 420823471 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1461717532 Sep 11 06:49:18 PM UTC 24 Sep 11 06:49:22 PM UTC 24 96673957 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3593654353 Sep 11 06:49:07 PM UTC 24 Sep 11 06:49:22 PM UTC 24 3987255594 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2727159808 Sep 11 06:49:11 PM UTC 24 Sep 11 06:49:22 PM UTC 24 849324701 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1050957701 Sep 11 06:48:27 PM UTC 24 Sep 11 06:49:22 PM UTC 24 11601071003 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2954318176 Sep 11 06:49:20 PM UTC 24 Sep 11 06:49:23 PM UTC 24 20388111 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3488323328 Sep 11 06:49:20 PM UTC 24 Sep 11 06:49:23 PM UTC 24 14785344 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1162729624 Sep 11 06:49:17 PM UTC 24 Sep 11 06:49:25 PM UTC 24 1661419329 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3758724626 Sep 11 06:49:23 PM UTC 24 Sep 11 06:49:25 PM UTC 24 14498578 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.757934622 Sep 11 06:49:11 PM UTC 24 Sep 11 06:49:26 PM UTC 24 868836934 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3993291091 Sep 11 06:48:58 PM UTC 24 Sep 11 06:49:27 PM UTC 24 1183428245 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.264664044 Sep 11 06:49:09 PM UTC 24 Sep 11 06:49:27 PM UTC 24 903794052 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1929891531 Sep 11 06:49:23 PM UTC 24 Sep 11 06:49:28 PM UTC 24 286337014 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.1511011570 Sep 11 06:49:23 PM UTC 24 Sep 11 06:49:29 PM UTC 24 72608884 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2931271123 Sep 11 06:49:10 PM UTC 24 Sep 11 06:49:29 PM UTC 24 3561544393 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.612110468 Sep 11 06:48:41 PM UTC 24 Sep 11 06:49:29 PM UTC 24 1504851547 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.1565819541 Sep 11 06:49:18 PM UTC 24 Sep 11 06:49:30 PM UTC 24 906309605 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2593021585 Sep 11 06:49:18 PM UTC 24 Sep 11 06:49:30 PM UTC 24 835059534 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1026129958 Sep 11 06:49:19 PM UTC 24 Sep 11 06:49:30 PM UTC 24 178963835 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3909458279 Sep 11 06:48:22 PM UTC 24 Sep 11 06:49:31 PM UTC 24 2394076301 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.1005600064 Sep 11 06:49:28 PM UTC 24 Sep 11 06:49:32 PM UTC 24 45647873 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1377725949 Sep 11 06:49:24 PM UTC 24 Sep 11 06:49:32 PM UTC 24 677813074 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.2186569940 Sep 11 06:49:35 PM UTC 24 Sep 11 06:49:39 PM UTC 24 503824418 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.2474840598 Sep 11 06:48:53 PM UTC 24 Sep 11 06:49:33 PM UTC 24 783172635 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.4249512643 Sep 11 06:49:17 PM UTC 24 Sep 11 06:49:33 PM UTC 24 1742319419 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1719657700 Sep 11 06:48:38 PM UTC 24 Sep 11 06:49:33 PM UTC 24 1183619128 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.806426664 Sep 11 06:49:30 PM UTC 24 Sep 11 06:49:33 PM UTC 24 14625023 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1504896496 Sep 11 06:49:17 PM UTC 24 Sep 11 06:49:33 PM UTC 24 4207683765 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2626169980 Sep 11 06:49:14 PM UTC 24 Sep 11 06:49:33 PM UTC 24 301694231 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2234070486 Sep 11 06:49:17 PM UTC 24 Sep 11 06:49:33 PM UTC 24 496836568 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3939704785 Sep 11 06:49:32 PM UTC 24 Sep 11 06:49:34 PM UTC 24 19761000 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1332009921 Sep 11 06:49:15 PM UTC 24 Sep 11 06:49:34 PM UTC 24 694134169 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.1266289247 Sep 11 06:49:23 PM UTC 24 Sep 11 06:49:35 PM UTC 24 1142369132 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.2154707586 Sep 11 06:49:27 PM UTC 24 Sep 11 06:49:36 PM UTC 24 1113128759 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1202665576 Sep 11 06:49:32 PM UTC 24 Sep 11 06:49:36 PM UTC 24 382341944 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3792176537 Sep 11 06:48:58 PM UTC 24 Sep 11 06:49:37 PM UTC 24 2008273345 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.1221305961 Sep 11 06:48:47 PM UTC 24 Sep 11 06:49:37 PM UTC 24 1251536678 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3368038850 Sep 11 06:49:11 PM UTC 24 Sep 11 06:49:39 PM UTC 24 3467146278 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3084422679 Sep 11 06:49:06 PM UTC 24 Sep 11 06:49:40 PM UTC 24 164952711 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2799116680 Sep 11 06:48:06 PM UTC 24 Sep 11 06:49:40 PM UTC 24 10308913002 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.268447587 Sep 11 06:49:24 PM UTC 24 Sep 11 06:49:40 PM UTC 24 10054234443 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.381911676 Sep 11 06:49:39 PM UTC 24 Sep 11 06:49:41 PM UTC 24 17721856 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.454625893 Sep 11 06:49:39 PM UTC 24 Sep 11 06:49:41 PM UTC 24 129047207 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2441590335 Sep 11 06:49:27 PM UTC 24 Sep 11 06:49:41 PM UTC 24 3815269045 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.505376421 Sep 11 06:48:44 PM UTC 24 Sep 11 06:49:42 PM UTC 24 1720231779 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3400601287 Sep 11 06:49:29 PM UTC 24 Sep 11 06:49:42 PM UTC 24 1654453110 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.3364534723 Sep 11 06:49:29 PM UTC 24 Sep 11 06:49:42 PM UTC 24 1091988108 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.3660424280 Sep 11 06:49:39 PM UTC 24 Sep 11 06:49:43 PM UTC 24 41021624 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.516725184 Sep 11 06:49:33 PM UTC 24 Sep 11 06:49:43 PM UTC 24 458382682 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.535046429 Sep 11 06:50:14 PM UTC 24 Sep 11 06:50:16 PM UTC 24 32837922 ps