Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59932585

1

T1

1339

T2

3290

T3

6803

auto[1]

1118917

1

T3

396

T4

396

T6

98

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59928633

1

T1

1339

T2

3290

T3

6407

auto[1]

1122869

1

T3

792

T4

198

T6

491

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5417165	1			T1	110		T2	1285		T3	1227
auto[IdleSt]	16562597	1			T1	162		T2	378		T3	1544
auto[ClkMuxSt]	28253	1			T1	1		T2	15		T3	12
auto[CntIncrSt]	28058	1			T1	1		T2	15		T3	12
auto[CntProgSt]	1324706	1			T1	7		T2	239		T3	1860
auto[TransCheckSt]	22219	1			T1	1		T2	15		T4	7
auto[TokenHashSt]	16356235	1			T1	52		T2	262		T4	132
auto[FlashRmaSt]	29195	1			T1	1		T2	15		T4	41
auto[TokenCheck0St]	10100	1			T1	1		T2	15		T4	7
auto[TokenCheck1St]	7355	1			T1	1		T2	15		T4	7
auto[TransProgSt]	288155	1			T1	20		T2	285		T4	14
auto[PostTransSt]	9086929	1			T1	982		T2	751		T3	839
auto[ScrapSt]	229366	1			T54	16		T55	38		T56	10
auto[EscalateSt]	4615609	1			T3	1705		T4	1611		T6	4224
auto[InvalidSt]	7044220	1			T4	1076		T13	172		T17	9584

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1340	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7044220	1			T4	1076		T13	172		T17	9584
EscalateSt	4615609	1			T3	1705		T4	1611		T6	4224
ScrapSt	229366	1			T54	16		T55	38		T56	10
PostTransSt	9086929	1			T1	982		T2	751		T3	839
TransProgSt	288155	1			T1	20		T2	285		T4	14
TokenCheck1St	7355	1			T1	1		T2	15		T4	7
TokenCheck0St	10100	1			T1	1		T2	15		T4	7
FlashRmaSt	29195	1			T1	1		T2	15		T4	41
TokenHashSt	16356235	1			T1	52		T2	262		T4	132
TransCheckSt	22219	1			T1	1		T2	15		T4	7
CntProgSt	1324706	1			T1	7		T2	239		T3	1860
CntIncrSt	28058	1			T1	1		T2	15		T3	12
ClkMuxSt	28253	1			T1	1		T2	15		T3	12
IdleSt	16562597	1			T1	162		T2	378		T3	1544
ResetSt	5417165	1			T1	110		T2	1285		T3	1227
arcs[ResetSt=>IdleSt]	41632	1			T1	1		T2	15		T3	13
arcs[IdleSt=>ScrapSt]	217	1			T54	4		T55	1		T56	1
arcs[IdleSt=>ClkMuxSt]	28083	1			T1	1		T2	15		T3	12
arcs[ClkMuxSt=>CntIncrSt]	28058	1			T1	1		T2	15		T3	12
arcs[CntIncrSt=>PostTransSt]	1257	1			T16	5		T41	9		T50	5
arcs[CntIncrSt=>CntProgSt]	26719	1			T1	1		T2	15		T3	12
arcs[CntProgSt=>PostTransSt]	3412	1			T3	12		T6	6		T14	5
arcs[CntProgSt=>TransCheckSt]	22219	1			T1	1		T2	15		T4	7
arcs[TransCheckSt=>PostTransSt]	3059	1			T16	14		T40	43		T41	6
arcs[TransCheckSt=>TokenHashSt]	19058	1			T1	1		T2	15		T4	7
arcs[TokenHashSt=>PostTransSt]	8137	1			T16	43		T40	10		T48	7
arcs[TokenHashSt=>FlashRmaSt]	10147	1			T1	1		T2	15		T4	7
arcs[FlashRmaSt=>TokenCheck0St]	10100	1			T1	1		T2	15		T4	7
arcs[TokenCheck0St=>PostTransSt]	2687	1			T16	7		T40	14		T48	13
arcs[TokenCheck0St=>TokenCheck1St]	7355	1			T1	1		T2	15		T4	7
arcs[TokenCheck1St=>PostTransSt]	623	1			T16	2		T40	4		T41	1
arcs[TransProgSt=>PostTransSt]	5931	1			T1	1		T2	15		T4	7
arcs[IdleSt=>EscalateSt]	177	1			T54	9		T49	10		T45	5
arcs[ClkMuxSt=>EscalateSt]	25	1			T49	2		T70	3		T71	4
arcs[CntIncrSt=>EscalateSt]	82	1			T15	1		T54	6		T45	2
arcs[CntProgSt=>EscalateSt]	1088	1			T15	45		T54	24		T49	26
arcs[TransCheckSt=>EscalateSt]	102	1			T75	7		T76	5		T70	5
arcs[TokenHashSt=>EscalateSt]	774	1			T15	10		T54	7		T49	9
arcs[FlashRmaSt=>EscalateSt]	47	1			T15	3		T54	2		T45	1
arcs[TokenCheck0St=>EscalateSt]	58	1			T15	2		T49	3		T45	2
arcs[TokenCheck1St=>EscalateSt]	25	1			T75	1		T76	2		T77	2
arcs[TransProgSt=>EscalateSt]	776	1			T15	21		T54	20		T49	20
arcs[PostTransSt=>EscalateSt]	3764	1			T3	12		T6	6		T14	5
arcs[InvalidSt=>EscalateSt]	9883	1			T4	6		T13	3		T17	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5416979	1			T1	110		T2	1285		T3	1227
auto[0]	auto[IdleSt]	16562471	1			T1	162		T2	378		T3	1544
auto[0]	auto[ClkMuxSt]	28238	1			T1	1		T2	15		T3	12
auto[0]	auto[CntIncrSt]	28004	1			T1	1		T2	15		T3	12
auto[0]	auto[CntProgSt]	1323977	1			T1	7		T2	239		T3	1860
auto[0]	auto[TransCheckSt]	22151	1			T1	1		T2	15		T4	7
auto[0]	auto[TokenHashSt]	16355717	1			T1	52		T2	262		T4	132
auto[0]	auto[FlashRmaSt]	29164	1			T1	1		T2	15		T4	41
auto[0]	auto[TokenCheck0St]	10060	1			T1	1		T2	15		T4	7
auto[0]	auto[TokenCheck1St]	7338	1			T1	1		T2	15		T4	7
auto[0]	auto[TransProgSt]	287646	1			T1	20		T2	285		T4	14
auto[0]	auto[PostTransSt]	9084959	1			T1	982		T2	751		T3	835
auto[0]	auto[ScrapSt]	229320	1			T54	13		T55	38		T56	10
auto[0]	auto[EscalateSt]	3505832	1			T3	1313		T4	1219		T6	4127
auto[0]	auto[InvalidSt]	7039389	1			T4	1072		T13	170		T17	9580
auto[1]	auto[ResetSt]	186	1			T15	6		T54	6		T49	3
auto[1]	auto[IdleSt]	126	1			T54	8		T49	7		T45	5
auto[1]	auto[ClkMuxSt]	15	1			T49	1		T70	2		T71	1
auto[1]	auto[CntIncrSt]	54	1			T54	3		T45	2		T75	1
auto[1]	auto[CntProgSt]	729	1			T15	26		T54	13		T49	19
auto[1]	auto[TransCheckSt]	68	1			T75	5		T76	5		T70	4
auto[1]	auto[TokenHashSt]	518	1			T15	6		T54	3		T49	5
auto[1]	auto[FlashRmaSt]	31	1			T15	1		T54	1		T75	1
auto[1]	auto[TokenCheck0St]	40	1			T15	1		T49	2		T45	2
auto[1]	auto[TokenCheck1St]	17	1			T76	2		T77	2		T246	1
auto[1]	auto[TransProgSt]	509	1			T15	14		T54	13		T49	10
auto[1]	auto[PostTransSt]	1970	1			T3	4		T6	1		T14	4
auto[1]	auto[ScrapSt]	46	1			T54	3		T49	1		T76	2
auto[1]	auto[EscalateSt]	1109777	1			T3	392		T4	392		T6	97
auto[1]	auto[InvalidSt]	4831	1			T4	4		T13	2		T17	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5416993	1			T1	110		T2	1285		T3	1227
auto[0]	auto[IdleSt]	16562494	1			T1	162		T2	378		T3	1544
auto[0]	auto[ClkMuxSt]	28233	1			T1	1		T2	15		T3	12
auto[0]	auto[CntIncrSt]	27998	1			T1	1		T2	15		T3	12
auto[0]	auto[CntProgSt]	1323984	1			T1	7		T2	239		T3	1860
auto[0]	auto[TransCheckSt]	22154	1			T1	1		T2	15		T4	7
auto[0]	auto[TokenHashSt]	16355742	1			T1	52		T2	262		T4	132
auto[0]	auto[FlashRmaSt]	29159	1			T1	1		T2	15		T4	41
auto[0]	auto[TokenCheck0St]	10064	1			T1	1		T2	15		T4	7
auto[0]	auto[TokenCheck1St]	7339	1			T1	1		T2	15		T4	7
auto[0]	auto[TransProgSt]	287641	1			T1	20		T2	285		T4	14
auto[0]	auto[PostTransSt]	9085032	1			T1	982		T2	751		T3	831
auto[0]	auto[ScrapSt]	229330	1			T54	14		T55	38		T56	10
auto[0]	auto[EscalateSt]	3501962	1			T3	921		T4	1415		T6	3738
auto[0]	auto[InvalidSt]	7039168	1			T4	1074		T13	171		T17	9583
auto[1]	auto[ResetSt]	172	1			T15	3		T54	4		T49	1
auto[1]	auto[IdleSt]	103	1			T54	4		T49	5		T45	1
auto[1]	auto[ClkMuxSt]	20	1			T49	2		T70	2		T71	4
auto[1]	auto[CntIncrSt]	60	1			T15	1		T54	4		T45	2
auto[1]	auto[CntProgSt]	722	1			T15	33		T54	15		T49	12
auto[1]	auto[TransCheckSt]	65	1			T75	6		T76	2		T70	4
auto[1]	auto[TokenHashSt]	493	1			T15	7		T54	6		T49	5
auto[1]	auto[FlashRmaSt]	36	1			T15	2		T54	2		T45	1
auto[1]	auto[TokenCheck0St]	36	1			T15	1		T49	2		T45	2
auto[1]	auto[TokenCheck1St]	16	1			T75	1		T76	1		T77	1
auto[1]	auto[TransProgSt]	514	1			T15	14		T54	11		T49	12
auto[1]	auto[PostTransSt]	1897	1			T3	8		T6	5		T14	1
auto[1]	auto[ScrapSt]	36	1			T54	2		T45	1		T75	1
auto[1]	auto[EscalateSt]	1113647	1			T3	784		T4	196		T6	486
auto[1]	auto[InvalidSt]	5052	1			T4	2		T13	1		T17	1