Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.27 97.97 96.04 93.40 100.00 98.53 99.00 95.94


Total tests in report: 1006
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
66.33 66.33 81.04 81.04 44.10 44.10 56.29 56.29 55.81 55.81 81.05 81.05 91.79 91.79 54.24 54.24 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.185883360
76.41 10.08 87.79 6.74 71.02 26.91 72.50 16.21 60.47 4.65 86.53 5.47 94.03 2.24 62.54 8.30 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3780123639
81.39 4.98 88.55 0.76 80.02 9.00 76.29 3.79 74.42 13.95 89.26 2.74 94.03 0.00 67.14 4.59 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3017353850
83.43 2.05 94.98 6.44 80.02 0.00 77.12 0.83 74.42 0.00 91.37 2.11 94.03 0.00 72.08 4.95 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2566196398
85.42 1.99 95.03 0.05 80.20 0.18 87.55 10.43 74.42 0.00 91.79 0.42 94.03 0.00 74.91 2.83 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3839174835
87.20 1.78 95.13 0.10 80.29 0.09 87.55 0.00 83.72 9.30 92.42 0.63 94.28 0.25 77.03 2.12 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1706010323
88.61 1.41 96.10 0.96 82.36 2.07 87.91 0.35 88.37 4.65 93.89 1.47 94.28 0.00 77.39 0.35 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1274211490
89.90 1.28 96.10 0.00 83.89 1.53 88.15 0.24 88.37 0.00 94.11 0.21 95.27 1.00 83.39 6.01 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.4281868328
91.07 1.17 96.65 0.56 86.68 2.79 88.32 0.17 88.37 0.00 94.95 0.84 96.27 1.00 86.22 2.83 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3280109454
91.98 0.92 96.65 0.00 87.04 0.36 88.32 0.00 93.02 4.65 94.95 0.00 96.27 0.00 87.63 1.41 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.4081967253
92.86 0.87 96.76 0.10 87.85 0.81 88.67 0.34 95.35 2.33 96.00 1.05 96.52 0.25 88.87 1.24 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.669365531
93.49 0.64 96.96 0.20 89.56 1.71 88.67 0.00 95.35 0.00 96.42 0.42 96.52 0.00 90.99 2.12 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4276465575
94.02 0.53 97.01 0.05 89.74 0.18 91.05 2.39 95.35 0.00 96.42 0.00 96.52 0.00 92.05 1.06 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.808944231
94.39 0.37 97.01 0.00 90.01 0.27 91.05 0.00 97.67 2.33 96.42 0.00 96.52 0.00 92.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2804363376
94.74 0.35 97.06 0.05 91.00 0.99 91.05 0.00 97.67 0.00 96.84 0.42 96.77 0.25 92.76 0.71 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2713553216
95.07 0.34 97.16 0.10 91.00 0.00 91.31 0.25 97.67 0.00 97.26 0.42 96.77 0.00 94.35 1.59 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1160589270
95.41 0.33 97.16 0.00 91.00 0.00 91.31 0.00 100.00 2.33 97.26 0.00 96.77 0.00 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2823311542
95.62 0.21 97.16 0.00 91.00 0.00 91.31 0.00 100.00 0.00 97.26 0.00 98.26 1.49 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.562302893
95.82 0.20 97.52 0.35 91.90 0.90 91.46 0.15 100.00 0.00 97.26 0.00 98.26 0.00 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2730112450
95.99 0.17 97.72 0.20 92.26 0.36 91.46 0.00 100.00 0.00 97.68 0.42 98.26 0.00 94.52 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3649129911
96.14 0.16 97.72 0.00 92.26 0.00 92.56 1.10 100.00 0.00 97.68 0.00 98.26 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.494388188
96.30 0.15 97.72 0.00 93.16 0.90 92.56 0.00 100.00 0.00 97.68 0.00 98.26 0.00 94.70 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1149368022
96.41 0.11 97.72 0.00 93.61 0.45 92.56 0.00 100.00 0.00 97.68 0.00 98.26 0.00 95.05 0.35 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1898297007
96.53 0.11 97.87 0.15 93.61 0.00 92.81 0.25 100.00 0.00 97.89 0.21 98.26 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1462435091
96.62 0.09 97.87 0.00 94.24 0.63 92.81 0.00 100.00 0.00 97.89 0.00 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.335960053
96.69 0.08 97.97 0.10 94.24 0.00 92.85 0.04 100.00 0.00 98.11 0.21 98.26 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3279873745
96.77 0.08 97.97 0.00 94.24 0.00 93.38 0.53 100.00 0.00 98.11 0.00 98.26 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3538249262
96.84 0.07 97.97 0.00 94.24 0.00 93.38 0.00 100.00 0.00 98.11 0.00 98.76 0.50 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2726212825
96.89 0.05 97.97 0.00 94.60 0.36 93.38 0.00 100.00 0.00 98.11 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1478259770
96.93 0.04 97.97 0.00 94.69 0.09 93.38 0.00 100.00 0.00 98.32 0.21 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.527930335
96.97 0.04 97.97 0.00 94.96 0.27 93.38 0.00 100.00 0.00 98.32 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2240265190
97.01 0.04 97.97 0.00 95.05 0.09 93.38 0.00 100.00 0.00 98.32 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1087070888
97.04 0.04 97.97 0.00 95.05 0.00 93.38 0.00 100.00 0.00 98.32 0.00 99.00 0.25 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1491949801
97.07 0.03 97.97 0.00 95.05 0.00 93.38 0.00 100.00 0.00 98.53 0.21 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.147849529
97.10 0.03 97.97 0.00 95.05 0.00 93.39 0.01 100.00 0.00 98.53 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3920829799
97.13 0.03 97.97 0.00 95.23 0.18 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3483680673
97.15 0.03 97.97 0.00 95.41 0.18 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.76 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.425015505
97.18 0.03 97.97 0.00 95.41 0.00 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2448014791
97.19 0.01 97.97 0.00 95.50 0.09 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4130201355
97.20 0.01 97.97 0.00 95.59 0.09 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2312770733
97.22 0.01 97.97 0.00 95.68 0.09 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3948470582
97.23 0.01 97.97 0.00 95.77 0.09 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2628208469
97.24 0.01 97.97 0.00 95.86 0.09 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2133834983
97.25 0.01 97.97 0.00 95.95 0.09 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3365272291
97.27 0.01 97.97 0.00 96.04 0.09 93.39 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3690867922
97.27 0.01 97.97 0.00 96.04 0.00 93.40 0.01 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3925785183

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1649770131
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3209792025
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.68842702
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.22153424
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2221801067
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.802841656
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.940307491
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1508256943
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4033595176
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1828826664
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4001267789
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1939792411
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3584163969
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1145642514
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3727201681
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2106935050
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1067675216
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.938962974
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1547576021
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2975048376
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3891593040
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3901553276
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3245071491
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3417370470
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1274740128
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3622147219
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1363498576
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1580461291
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2509499449
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1123051272
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2649581542
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1451581474
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3908415507
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.16643105
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2093756541
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3098881076
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2856951710
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4285844763
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3594574244
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3942232502
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.881754834
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.70006946
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2532050855
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.29153460
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/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.975826547
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3246984029
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/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2013662498



Total test records in report: 1006
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.222885580 Sep 18 09:19:11 PM UTC 24 Sep 18 09:19:14 PM UTC 24 13974702 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.3896218105 Sep 18 09:19:10 PM UTC 24 Sep 18 09:19:15 PM UTC 24 113548036 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3279873745 Sep 18 09:19:14 PM UTC 24 Sep 18 09:19:20 PM UTC 24 654584291 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3920829799 Sep 18 09:19:18 PM UTC 24 Sep 18 09:19:21 PM UTC 24 32384574 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3750377607 Sep 18 09:19:12 PM UTC 24 Sep 18 09:19:24 PM UTC 24 167528477 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3259397536 Sep 18 09:19:19 PM UTC 24 Sep 18 09:19:25 PM UTC 24 350648577 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.4288308844 Sep 18 09:19:21 PM UTC 24 Sep 18 09:19:29 PM UTC 24 1185776766 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1315388296 Sep 18 09:20:21 PM UTC 24 Sep 18 09:20:33 PM UTC 24 234357624 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.3480799593 Sep 18 09:20:40 PM UTC 24 Sep 18 09:20:44 PM UTC 24 101086871 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.185883360 Sep 18 09:19:15 PM UTC 24 Sep 18 09:19:31 PM UTC 24 1873719098 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3280109454 Sep 18 09:19:22 PM UTC 24 Sep 18 09:19:33 PM UTC 24 7988344115 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3017353850 Sep 18 09:19:14 PM UTC 24 Sep 18 09:19:33 PM UTC 24 439243786 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2730112450 Sep 18 09:19:31 PM UTC 24 Sep 18 09:19:34 PM UTC 24 22503342 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3780123639 Sep 18 09:19:21 PM UTC 24 Sep 18 09:19:36 PM UTC 24 1899775626 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1274211490 Sep 18 09:19:34 PM UTC 24 Sep 18 09:19:36 PM UTC 24 18170951 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1462435091 Sep 18 09:19:33 PM UTC 24 Sep 18 09:19:38 PM UTC 24 52381350 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3925785183 Sep 18 09:19:16 PM UTC 24 Sep 18 09:19:39 PM UTC 24 276454993 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.608038172 Sep 18 09:19:35 PM UTC 24 Sep 18 09:19:40 PM UTC 24 119828616 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2925857282 Sep 18 09:19:39 PM UTC 24 Sep 18 09:19:41 PM UTC 24 17886179 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.2758268580 Sep 18 09:19:24 PM UTC 24 Sep 18 09:19:42 PM UTC 24 509969389 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1160589270 Sep 18 09:19:27 PM UTC 24 Sep 18 09:19:43 PM UTC 24 4870636199 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.2474966061 Sep 18 09:19:35 PM UTC 24 Sep 18 09:19:46 PM UTC 24 325991922 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3336586783 Sep 18 09:19:43 PM UTC 24 Sep 18 09:19:47 PM UTC 24 72749439 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2566196398 Sep 18 09:19:25 PM UTC 24 Sep 18 09:19:48 PM UTC 24 571258623 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2296449326 Sep 18 09:19:37 PM UTC 24 Sep 18 09:19:49 PM UTC 24 1577288954 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2950187131 Sep 18 09:19:46 PM UTC 24 Sep 18 09:19:52 PM UTC 24 713664620 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.2267766326 Sep 18 09:19:37 PM UTC 24 Sep 18 09:19:53 PM UTC 24 236461738 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3039773015 Sep 18 09:19:40 PM UTC 24 Sep 18 09:19:53 PM UTC 24 1272079012 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.369303017 Sep 18 09:19:29 PM UTC 24 Sep 18 09:19:55 PM UTC 24 214479984 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.1982402504 Sep 18 09:19:27 PM UTC 24 Sep 18 09:19:56 PM UTC 24 3186631413 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.1030050734 Sep 18 09:19:47 PM UTC 24 Sep 18 09:19:57 PM UTC 24 779184586 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3887223796 Sep 18 09:19:54 PM UTC 24 Sep 18 09:19:57 PM UTC 24 32419178 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1587145473 Sep 18 09:19:11 PM UTC 24 Sep 18 09:19:57 PM UTC 24 264808016 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.448471932 Sep 18 09:19:58 PM UTC 24 Sep 18 09:20:00 PM UTC 24 108498769 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1221356836 Sep 18 09:19:35 PM UTC 24 Sep 18 09:20:00 PM UTC 24 625500865 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1265323572 Sep 18 09:19:57 PM UTC 24 Sep 18 09:20:02 PM UTC 24 60945121 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.740234361 Sep 18 09:19:59 PM UTC 24 Sep 18 09:20:03 PM UTC 24 224713781 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1087070888 Sep 18 09:19:50 PM UTC 24 Sep 18 09:20:03 PM UTC 24 243042570 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2132812907 Sep 18 09:19:58 PM UTC 24 Sep 18 09:20:04 PM UTC 24 141589665 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2551466729 Sep 18 09:19:51 PM UTC 24 Sep 18 09:20:04 PM UTC 24 262850408 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2448014791 Sep 18 09:20:02 PM UTC 24 Sep 18 09:20:05 PM UTC 24 34339366 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.2521844994 Sep 18 09:19:42 PM UTC 24 Sep 18 09:20:05 PM UTC 24 334060733 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.2135429260 Sep 18 09:19:52 PM UTC 24 Sep 18 09:20:06 PM UTC 24 907501889 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.3639462565 Sep 18 09:19:39 PM UTC 24 Sep 18 09:20:09 PM UTC 24 633852803 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4180571415 Sep 18 09:20:05 PM UTC 24 Sep 18 09:20:09 PM UTC 24 206120322 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.808944231 Sep 18 09:19:20 PM UTC 24 Sep 18 09:20:15 PM UTC 24 3306352985 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1791093888 Sep 18 09:20:00 PM UTC 24 Sep 18 09:20:15 PM UTC 24 346860629 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3790753028 Sep 18 09:19:25 PM UTC 24 Sep 18 09:20:16 PM UTC 24 4616760304 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.631685771 Sep 18 09:20:04 PM UTC 24 Sep 18 09:20:16 PM UTC 24 1738941676 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1706010323 Sep 18 09:20:01 PM UTC 24 Sep 18 09:20:16 PM UTC 24 1910018659 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.3549774727 Sep 18 09:20:07 PM UTC 24 Sep 18 09:20:19 PM UTC 24 367328863 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1278689497 Sep 18 09:20:17 PM UTC 24 Sep 18 09:20:20 PM UTC 24 22269003 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.276035821 Sep 18 09:19:50 PM UTC 24 Sep 18 09:20:20 PM UTC 24 889320511 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1738731658 Sep 18 09:20:19 PM UTC 24 Sep 18 09:20:21 PM UTC 24 41666170 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4227542101 Sep 18 09:19:22 PM UTC 24 Sep 18 09:20:21 PM UTC 24 3042838348 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.3043129787 Sep 18 09:20:10 PM UTC 24 Sep 18 09:20:21 PM UTC 24 475178617 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1158806779 Sep 18 09:20:05 PM UTC 24 Sep 18 09:20:22 PM UTC 24 5761523706 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2637567698 Sep 18 09:20:18 PM UTC 24 Sep 18 09:20:22 PM UTC 24 455092149 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2221084673 Sep 18 09:20:06 PM UTC 24 Sep 18 09:20:35 PM UTC 24 1795335303 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1469483104 Sep 18 09:20:11 PM UTC 24 Sep 18 09:20:23 PM UTC 24 307237379 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.669365531 Sep 18 09:19:54 PM UTC 24 Sep 18 09:20:24 PM UTC 24 504917153 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3124087736 Sep 18 09:20:22 PM UTC 24 Sep 18 09:20:25 PM UTC 24 12863485 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2760788067 Sep 18 09:20:01 PM UTC 24 Sep 18 09:20:26 PM UTC 24 273141374 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.99164015 Sep 18 09:20:21 PM UTC 24 Sep 18 09:20:27 PM UTC 24 100307302 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.2937738076 Sep 18 09:20:16 PM UTC 24 Sep 18 09:20:27 PM UTC 24 269205816 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.4264847149 Sep 18 09:19:58 PM UTC 24 Sep 18 09:20:32 PM UTC 24 312816506 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.1049426830 Sep 18 09:20:23 PM UTC 24 Sep 18 09:20:33 PM UTC 24 1567848435 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.26708472 Sep 18 09:20:22 PM UTC 24 Sep 18 09:20:35 PM UTC 24 383845404 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.2014477085 Sep 18 09:20:25 PM UTC 24 Sep 18 09:20:37 PM UTC 24 1619691755 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1112719060 Sep 18 09:20:22 PM UTC 24 Sep 18 09:20:37 PM UTC 24 429466012 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2119766611 Sep 18 09:20:35 PM UTC 24 Sep 18 09:20:38 PM UTC 24 31504896 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.1333184382 Sep 18 09:19:41 PM UTC 24 Sep 18 09:20:39 PM UTC 24 1695153855 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1119496316 Sep 18 09:20:38 PM UTC 24 Sep 18 09:20:40 PM UTC 24 44166715 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1867602424 Sep 18 09:20:32 PM UTC 24 Sep 18 09:20:40 PM UTC 24 809276202 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3400029175 Sep 18 09:20:22 PM UTC 24 Sep 18 09:20:40 PM UTC 24 654865953 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.68005066 Sep 18 09:20:35 PM UTC 24 Sep 18 09:20:41 PM UTC 24 58631170 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.478481742 Sep 18 09:20:27 PM UTC 24 Sep 18 09:20:42 PM UTC 24 775521833 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3141242078 Sep 18 09:20:07 PM UTC 24 Sep 18 09:20:42 PM UTC 24 1003340891 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.3194342601 Sep 18 09:20:20 PM UTC 24 Sep 18 09:20:43 PM UTC 24 671366598 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.1053656973 Sep 18 09:20:28 PM UTC 24 Sep 18 09:20:44 PM UTC 24 1651568135 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.332871684 Sep 18 09:20:39 PM UTC 24 Sep 18 09:20:44 PM UTC 24 249729686 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1220615517 Sep 18 09:21:28 PM UTC 24 Sep 18 09:21:38 PM UTC 24 709280635 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1797879228 Sep 18 09:21:00 PM UTC 24 Sep 18 09:21:39 PM UTC 24 8571245809 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3598996317 Sep 18 09:20:17 PM UTC 24 Sep 18 09:20:44 PM UTC 24 144854629 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1244777122 Sep 18 09:20:42 PM UTC 24 Sep 18 09:20:45 PM UTC 24 19345126 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.425141744 Sep 18 09:20:43 PM UTC 24 Sep 18 09:20:48 PM UTC 24 223438400 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.524286481 Sep 18 09:20:25 PM UTC 24 Sep 18 09:20:49 PM UTC 24 966890568 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.4281318670 Sep 18 09:20:33 PM UTC 24 Sep 18 09:20:50 PM UTC 24 1381914514 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.405986810 Sep 18 09:20:41 PM UTC 24 Sep 18 09:20:51 PM UTC 24 776652272 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.494388188 Sep 18 09:20:04 PM UTC 24 Sep 18 09:20:52 PM UTC 24 996348660 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.203551350 Sep 18 09:21:21 PM UTC 24 Sep 18 09:21:40 PM UTC 24 4919919710 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.3221520606 Sep 18 09:20:41 PM UTC 24 Sep 18 09:20:52 PM UTC 24 510378788 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1401485009 Sep 18 09:20:45 PM UTC 24 Sep 18 09:20:53 PM UTC 24 2154988927 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1659715695 Sep 18 09:20:24 PM UTC 24 Sep 18 09:20:55 PM UTC 24 7872032610 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1802423423 Sep 18 09:20:29 PM UTC 24 Sep 18 09:20:55 PM UTC 24 866779709 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.738840143 Sep 18 09:20:53 PM UTC 24 Sep 18 09:20:56 PM UTC 24 43228520 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.644637841 Sep 18 09:20:44 PM UTC 24 Sep 18 09:20:56 PM UTC 24 587417271 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2204965589 Sep 18 09:20:41 PM UTC 24 Sep 18 09:20:56 PM UTC 24 388581816 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.986708106 Sep 18 09:20:53 PM UTC 24 Sep 18 09:20:56 PM UTC 24 83327070 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.197774439 Sep 18 09:20:53 PM UTC 24 Sep 18 09:20:57 PM UTC 24 34947325 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1391675608 Sep 18 09:20:44 PM UTC 24 Sep 18 09:20:58 PM UTC 24 445658505 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.725683670 Sep 18 09:20:49 PM UTC 24 Sep 18 09:20:59 PM UTC 24 341641553 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.442496383 Sep 18 09:20:57 PM UTC 24 Sep 18 09:21:00 PM UTC 24 13358997 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.3051112865 Sep 18 09:20:45 PM UTC 24 Sep 18 09:21:00 PM UTC 24 541101426 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.3754181995 Sep 18 09:20:56 PM UTC 24 Sep 18 09:21:00 PM UTC 24 43238648 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.3696887754 Sep 18 09:20:51 PM UTC 24 Sep 18 09:21:03 PM UTC 24 916003252 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3839174835 Sep 18 09:19:28 PM UTC 24 Sep 18 09:21:03 PM UTC 24 11335461971 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2888912286 Sep 18 09:20:29 PM UTC 24 Sep 18 09:21:04 PM UTC 24 1872603710 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.1210773634 Sep 18 09:20:57 PM UTC 24 Sep 18 09:21:05 PM UTC 24 1582179950 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.4122850597 Sep 18 09:20:56 PM UTC 24 Sep 18 09:21:05 PM UTC 24 190509794 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.3117668363 Sep 18 09:20:39 PM UTC 24 Sep 18 09:21:06 PM UTC 24 1542304922 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.4095919364 Sep 18 09:20:26 PM UTC 24 Sep 18 09:21:06 PM UTC 24 3212768031 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3699790675 Sep 18 09:20:46 PM UTC 24 Sep 18 09:21:07 PM UTC 24 998201212 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.3009684897 Sep 18 09:21:00 PM UTC 24 Sep 18 09:21:07 PM UTC 24 480259964 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.1718527054 Sep 18 09:21:07 PM UTC 24 Sep 18 09:21:10 PM UTC 24 16210115 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.719187337 Sep 18 09:21:01 PM UTC 24 Sep 18 09:21:10 PM UTC 24 1536020984 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.1938964766 Sep 18 09:20:57 PM UTC 24 Sep 18 09:21:10 PM UTC 24 270831765 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2150713703 Sep 18 09:21:08 PM UTC 24 Sep 18 09:21:10 PM UTC 24 11151905 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.1127374095 Sep 18 09:21:01 PM UTC 24 Sep 18 09:21:13 PM UTC 24 406397885 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3408509816 Sep 18 09:20:05 PM UTC 24 Sep 18 09:21:14 PM UTC 24 2204714527 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.133090662 Sep 18 09:20:57 PM UTC 24 Sep 18 09:21:14 PM UTC 24 622872210 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2508718587 Sep 18 09:20:53 PM UTC 24 Sep 18 09:21:15 PM UTC 24 462012271 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.39036503 Sep 18 09:21:11 PM UTC 24 Sep 18 09:21:16 PM UTC 24 268458197 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2861141134 Sep 18 09:21:08 PM UTC 24 Sep 18 09:21:17 PM UTC 24 104248849 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.4078647038 Sep 18 09:21:05 PM UTC 24 Sep 18 09:21:17 PM UTC 24 486149999 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3558553489 Sep 18 09:21:15 PM UTC 24 Sep 18 09:21:18 PM UTC 24 13953552 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.55433455 Sep 18 09:20:56 PM UTC 24 Sep 18 09:21:18 PM UTC 24 581428965 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3865559614 Sep 18 09:21:04 PM UTC 24 Sep 18 09:21:19 PM UTC 24 3911305622 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.2602134025 Sep 18 09:21:06 PM UTC 24 Sep 18 09:21:19 PM UTC 24 626612365 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.833298039 Sep 18 09:21:05 PM UTC 24 Sep 18 09:21:20 PM UTC 24 1042565527 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3275587110 Sep 18 09:20:45 PM UTC 24 Sep 18 09:21:21 PM UTC 24 4755805276 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1402977099 Sep 18 09:20:59 PM UTC 24 Sep 18 09:21:21 PM UTC 24 807577747 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2860515825 Sep 18 09:20:34 PM UTC 24 Sep 18 09:21:22 PM UTC 24 822455479 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.2862506709 Sep 18 09:21:11 PM UTC 24 Sep 18 09:21:23 PM UTC 24 76475748 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.780856341 Sep 18 09:20:55 PM UTC 24 Sep 18 09:21:23 PM UTC 24 645840005 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1208807668 Sep 18 09:21:15 PM UTC 24 Sep 18 09:21:25 PM UTC 24 497635111 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.461144229 Sep 18 09:21:14 PM UTC 24 Sep 18 09:21:26 PM UTC 24 519072909 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1003127100 Sep 18 09:21:24 PM UTC 24 Sep 18 09:21:27 PM UTC 24 45915278 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2809671373 Sep 18 09:21:20 PM UTC 24 Sep 18 09:21:27 PM UTC 24 672589377 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1314417289 Sep 18 09:21:16 PM UTC 24 Sep 18 09:21:27 PM UTC 24 298646639 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3735852205 Sep 18 09:21:24 PM UTC 24 Sep 18 09:21:29 PM UTC 24 203650831 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.2969675168 Sep 18 09:21:19 PM UTC 24 Sep 18 09:21:29 PM UTC 24 1343630698 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.988211719 Sep 18 09:21:26 PM UTC 24 Sep 18 09:21:29 PM UTC 24 33362915 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.4284508989 Sep 18 09:20:45 PM UTC 24 Sep 18 09:21:30 PM UTC 24 13956203718 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3538249262 Sep 18 09:19:53 PM UTC 24 Sep 18 09:21:30 PM UTC 24 20345046568 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.1029531486 Sep 18 09:21:12 PM UTC 24 Sep 18 09:21:30 PM UTC 24 328080518 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.147849529 Sep 18 09:19:52 PM UTC 24 Sep 18 09:21:31 PM UTC 24 12232442162 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.4181614836 Sep 18 09:21:22 PM UTC 24 Sep 18 09:21:32 PM UTC 24 189775929 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.2234119521 Sep 18 09:21:29 PM UTC 24 Sep 18 09:21:32 PM UTC 24 12018827 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2527612346 Sep 18 09:21:28 PM UTC 24 Sep 18 09:21:33 PM UTC 24 98861469 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.459611312 Sep 18 09:21:18 PM UTC 24 Sep 18 09:21:33 PM UTC 24 1906530790 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.4047071217 Sep 18 09:21:24 PM UTC 24 Sep 18 09:21:33 PM UTC 24 256648573 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3130291862 Sep 18 09:21:21 PM UTC 24 Sep 18 09:21:34 PM UTC 24 278754298 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.1811868850 Sep 18 09:21:22 PM UTC 24 Sep 18 09:21:34 PM UTC 24 456339370 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1108185411 Sep 18 09:21:31 PM UTC 24 Sep 18 09:21:36 PM UTC 24 63446399 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.1781152175 Sep 18 09:21:27 PM UTC 24 Sep 18 09:21:37 PM UTC 24 52975801 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1902342309 Sep 18 09:21:34 PM UTC 24 Sep 18 09:21:37 PM UTC 24 32714678 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3649129911 Sep 18 09:20:34 PM UTC 24 Sep 18 09:21:39 PM UTC 24 8364653962 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3715207781 Sep 18 09:21:37 PM UTC 24 Sep 18 09:21:40 PM UTC 24 15575429 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3209669925 Sep 18 09:21:19 PM UTC 24 Sep 18 09:21:40 PM UTC 24 2625431956 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1451177709 Sep 18 09:20:44 PM UTC 24 Sep 18 09:21:40 PM UTC 24 7201173837 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.4252227915 Sep 18 09:21:34 PM UTC 24 Sep 18 09:21:41 PM UTC 24 909624919 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.3572667264 Sep 18 09:21:38 PM UTC 24 Sep 18 09:21:42 PM UTC 24 55551957 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1057308621 Sep 18 09:21:29 PM UTC 24 Sep 18 09:21:42 PM UTC 24 1194695895 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.232565327 Sep 18 09:21:40 PM UTC 24 Sep 18 09:21:43 PM UTC 24 11667126 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.4281868328 Sep 18 09:19:29 PM UTC 24 Sep 18 09:21:43 PM UTC 24 31385470900 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.3568541152 Sep 18 09:21:29 PM UTC 24 Sep 18 09:21:44 PM UTC 24 791972101 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1016602091 Sep 18 09:21:32 PM UTC 24 Sep 18 09:21:45 PM UTC 24 367378657 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.2179408166 Sep 18 09:21:11 PM UTC 24 Sep 18 09:21:45 PM UTC 24 1242883847 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2449607017 Sep 18 09:21:43 PM UTC 24 Sep 18 09:21:45 PM UTC 24 12991244 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3445972551 Sep 18 09:21:41 PM UTC 24 Sep 18 09:21:46 PM UTC 24 26125744 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.484377753 Sep 18 09:21:43 PM UTC 24 Sep 18 09:21:48 PM UTC 24 488992854 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.2174555025 Sep 18 09:21:40 PM UTC 24 Sep 18 09:21:49 PM UTC 24 648792296 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2350624924 Sep 18 09:21:19 PM UTC 24 Sep 18 09:21:49 PM UTC 24 1319686755 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.673299521 Sep 18 09:21:34 PM UTC 24 Sep 18 09:21:49 PM UTC 24 2256610891 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3791381915 Sep 18 09:21:44 PM UTC 24 Sep 18 09:21:49 PM UTC 24 291590408 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.466133104 Sep 18 09:21:27 PM UTC 24 Sep 18 09:21:50 PM UTC 24 970539022 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.4130009658 Sep 18 09:21:35 PM UTC 24 Sep 18 09:21:51 PM UTC 24 285347633 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.862082148 Sep 18 09:21:50 PM UTC 24 Sep 18 09:21:53 PM UTC 24 16966765 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3210299113 Sep 18 09:19:44 PM UTC 24 Sep 18 09:21:53 PM UTC 24 32652583041 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2013662498 Sep 18 09:21:51 PM UTC 24 Sep 18 09:21:53 PM UTC 24 13400003 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.1435046322 Sep 18 09:21:32 PM UTC 24 Sep 18 09:21:54 PM UTC 24 456328357 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3129308464 Sep 18 09:21:41 PM UTC 24 Sep 18 09:21:54 PM UTC 24 277642982 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1324673077 Sep 18 09:21:51 PM UTC 24 Sep 18 09:21:55 PM UTC 24 113821683 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3211703839 Sep 18 09:21:46 PM UTC 24 Sep 18 09:21:56 PM UTC 24 1092902862 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.2003421169 Sep 18 09:21:46 PM UTC 24 Sep 18 09:21:56 PM UTC 24 3902628968 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.3799578267 Sep 18 09:21:41 PM UTC 24 Sep 18 09:21:57 PM UTC 24 693065823 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.925519719 Sep 18 09:21:24 PM UTC 24 Sep 18 09:21:57 PM UTC 24 581497466 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.550464834 Sep 18 09:21:49 PM UTC 24 Sep 18 09:21:58 PM UTC 24 535281043 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.2007376009 Sep 18 09:21:44 PM UTC 24 Sep 18 09:21:58 PM UTC 24 401919917 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.1418003148 Sep 18 09:21:57 PM UTC 24 Sep 18 09:21:59 PM UTC 24 52840937 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2941030251 Sep 18 09:21:46 PM UTC 24 Sep 18 09:22:00 PM UTC 24 1378534897 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3246984029 Sep 18 09:21:50 PM UTC 24 Sep 18 09:22:01 PM UTC 24 307789340 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1038334086 Sep 18 09:21:55 PM UTC 24 Sep 18 09:22:02 PM UTC 24 205061135 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.975826547 Sep 18 09:21:46 PM UTC 24 Sep 18 09:22:02 PM UTC 24 3022284790 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2530979948 Sep 18 09:21:34 PM UTC 24 Sep 18 09:22:02 PM UTC 24 658287284 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.1570425121 Sep 18 09:21:55 PM UTC 24 Sep 18 09:22:02 PM UTC 24 131391099 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3920720096 Sep 18 09:21:35 PM UTC 24 Sep 18 09:22:03 PM UTC 24 807697842 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3112957526 Sep 18 09:21:40 PM UTC 24 Sep 18 09:22:07 PM UTC 24 240087959 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3657226258 Sep 18 09:22:06 PM UTC 24 Sep 18 09:22:08 PM UTC 24 68990986 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2222045834 Sep 18 09:21:56 PM UTC 24 Sep 18 09:22:08 PM UTC 24 479160052 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1293233990 Sep 18 09:22:08 PM UTC 24 Sep 18 09:22:11 PM UTC 24 33669596 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.64348207 Sep 18 09:22:00 PM UTC 24 Sep 18 09:22:11 PM UTC 24 4733746186 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2652670471 Sep 18 09:22:03 PM UTC 24 Sep 18 09:22:11 PM UTC 24 1169331201 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2528934763 Sep 18 09:22:07 PM UTC 24 Sep 18 09:22:12 PM UTC 24 43938436 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3911300879 Sep 18 09:22:02 PM UTC 24 Sep 18 09:22:12 PM UTC 24 1019704672 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.4039640538 Sep 18 09:21:57 PM UTC 24 Sep 18 09:22:12 PM UTC 24 679522573 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1107971003 Sep 18 09:21:55 PM UTC 24 Sep 18 09:22:12 PM UTC 24 998856430 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2630653900 Sep 18 09:20:16 PM UTC 24 Sep 18 09:22:13 PM UTC 24 3231184836 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3846965868 Sep 18 09:21:41 PM UTC 24 Sep 18 09:22:13 PM UTC 24 397823701 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2577609146 Sep 18 09:21:58 PM UTC 24 Sep 18 09:22:15 PM UTC 24 596676329 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.3977832537 Sep 18 09:22:12 PM UTC 24 Sep 18 09:22:16 PM UTC 24 47459033 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1629351637 Sep 18 09:22:03 PM UTC 24 Sep 18 09:22:16 PM UTC 24 1557587988 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3913269032 Sep 18 09:22:13 PM UTC 24 Sep 18 09:22:17 PM UTC 24 128031388 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.4237568990 Sep 18 09:21:56 PM UTC 24 Sep 18 09:22:18 PM UTC 24 324530736 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1947042662 Sep 18 09:22:03 PM UTC 24 Sep 18 09:22:20 PM UTC 24 1265569910 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3210789959 Sep 18 09:21:53 PM UTC 24 Sep 18 09:22:20 PM UTC 24 811739562 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.2659890588 Sep 18 09:22:14 PM UTC 24 Sep 18 09:22:20 PM UTC 24 849743144 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2209882386 Sep 18 09:22:09 PM UTC 24 Sep 18 09:22:21 PM UTC 24 99375665 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3148851494 Sep 18 09:22:19 PM UTC 24 Sep 18 09:22:22 PM UTC 24 68232790 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3972575257 Sep 18 09:21:16 PM UTC 24 Sep 18 09:22:22 PM UTC 24 8543704248 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.1207240345 Sep 18 09:21:33 PM UTC 24 Sep 18 09:22:23 PM UTC 24 5719473955 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4029462835 Sep 18 09:22:20 PM UTC 24 Sep 18 09:22:23 PM UTC 24 18477522 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.4217313306 Sep 18 09:21:50 PM UTC 24 Sep 18 09:22:24 PM UTC 24 3447451878 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.4081967253 Sep 18 09:22:13 PM UTC 24 Sep 18 09:22:24 PM UTC 24 1240222806 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.4175000063 Sep 18 09:22:14 PM UTC 24 Sep 18 09:22:24 PM UTC 24 757883647 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.127856773 Sep 18 09:22:23 PM UTC 24 Sep 18 09:22:26 PM UTC 24 25440585 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1697455483 Sep 18 09:22:17 PM UTC 24 Sep 18 09:22:26 PM UTC 24 330928732 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.905333881 Sep 18 09:22:24 PM UTC 24 Sep 18 09:22:28 PM UTC 24 554775556 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1654636877 Sep 18 09:22:20 PM UTC 24 Sep 18 09:22:28 PM UTC 24 139385934 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2668793373 Sep 18 09:20:59 PM UTC 24 Sep 18 09:22:28 PM UTC 24 7931585016 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3267490515 Sep 18 09:22:15 PM UTC 24 Sep 18 09:22:29 PM UTC 24 391525372 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.4045073107 Sep 18 09:22:12 PM UTC 24 Sep 18 09:22:29 PM UTC 24 1238539524 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2534348983 Sep 18 09:22:02 PM UTC 24 Sep 18 09:22:31 PM UTC 24 1343089284 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.1846508456 Sep 18 09:22:30 PM UTC 24 Sep 18 09:22:32 PM UTC 24 61883196 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3007671918 Sep 18 09:22:23 PM UTC 24 Sep 18 09:22:33 PM UTC 24 54420536 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1058960179 Sep 18 09:21:58 PM UTC 24 Sep 18 09:22:33 PM UTC 24 855200617 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.244613823 Sep 18 09:21:32 PM UTC 24 Sep 18 09:22:34 PM UTC 24 11346236284 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4254966246 Sep 18 09:22:32 PM UTC 24 Sep 18 09:22:34 PM UTC 24 24705196 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.216466598 Sep 18 09:22:18 PM UTC 24 Sep 18 09:22:35 PM UTC 24 564816293 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.4168806426 Sep 18 09:22:30 PM UTC 24 Sep 18 09:22:35 PM UTC 24 48669332 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2840881327 Sep 18 09:22:24 PM UTC 24 Sep 18 09:22:35 PM UTC 24 678056378 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.3927303468 Sep 18 09:22:23 PM UTC 24 Sep 18 09:22:37 PM UTC 24 2380874462 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.1069412897 Sep 18 09:22:26 PM UTC 24 Sep 18 09:22:38 PM UTC 24 452997264 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.18175489 Sep 18 09:22:13 PM UTC 24 Sep 18 09:22:38 PM UTC 24 5200367622 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.3882717428 Sep 18 09:21:36 PM UTC 24 Sep 18 09:22:39 PM UTC 24 12397414608 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.698804057 Sep 18 09:22:29 PM UTC 24 Sep 18 09:22:39 PM UTC 24 766279110 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.3607247887 Sep 18 09:22:34 PM UTC 24 Sep 18 09:22:39 PM UTC 24 125357629 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.3817137422 Sep 18 09:22:27 PM UTC 24 Sep 18 09:22:41 PM UTC 24 2379218285 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.944013205 Sep 18 09:21:37 PM UTC 24 Sep 18 09:22:43 PM UTC 24 10726426009 ps
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