Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67759913

1

T1

1346

T2

20004

T3

5715

auto[1]

1170676

1

T4

495

T13

297

T14

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67768536

1

T1

1346

T2

20004

T3

5715

auto[1]

1162053

1

T4

891

T13

891

T14

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5499965	1			T1	82		T2	11417		T3	1628
auto[IdleSt]	17124969	1			T1	162		T2	3883		T3	1444
auto[ClkMuxSt]	29197	1			T3	17		T4	14		T6	5
auto[CntIncrSt]	29079	1			T3	17		T4	14		T6	5
auto[CntProgSt]	1212894	1			T3	762		T4	28		T6	10
auto[TransCheckSt]	22970	1			T3	17		T6	5		T13	42
auto[TokenHashSt]	22440713	1			T3	355		T6	121		T13	3303
auto[FlashRmaSt]	30072	1			T3	17		T6	17		T13	57
auto[TokenCheck0St]	10195	1			T3	17		T6	5		T13	14
auto[TokenCheck1St]	7373	1			T3	17		T6	5		T13	7
auto[TransProgSt]	279628	1			T3	787		T6	10		T13	12
auto[PostTransSt]	9396929	1			T1	1102		T3	601		T4	1177
auto[ScrapSt]	85954	1			T2	11		T3	36		T16	8
auto[EscalateSt]	4932680	1			T4	2057		T13	1744		T14	992
auto[InvalidSt]	7826506	1			T2	4673		T14	600		T11	7087

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1465	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7826506	1			T2	4673		T14	600		T11	7087
EscalateSt	4932680	1			T4	2057		T13	1744		T14	992
ScrapSt	85954	1			T2	11		T3	36		T16	8
PostTransSt	9396929	1			T1	1102		T3	601		T4	1177
TransProgSt	279628	1			T3	787		T6	10		T13	12
TokenCheck1St	7373	1			T3	17		T6	5		T13	7
TokenCheck0St	10195	1			T3	17		T6	5		T13	14
FlashRmaSt	30072	1			T3	17		T6	17		T13	57
TokenHashSt	22440713	1			T3	355		T6	121		T13	3303
TransCheckSt	22970	1			T3	17		T6	5		T13	42
CntProgSt	1212894	1			T3	762		T4	28		T6	10
CntIncrSt	29079	1			T3	17		T4	14		T6	5
ClkMuxSt	29197	1			T3	17		T4	14		T6	5
IdleSt	17124969	1			T1	162		T2	3883		T3	1444
ResetSt	5499965	1			T1	82		T2	11417		T3	1628
arcs[ResetSt=>IdleSt]	43266	1			T1	1		T2	121		T3	18
arcs[IdleSt=>ScrapSt]	228	1			T2	4		T3	1		T16	2
arcs[IdleSt=>ClkMuxSt]	29113	1			T3	17		T4	14		T6	5
arcs[ClkMuxSt=>CntIncrSt]	29079	1			T3	17		T4	14		T6	5
arcs[CntIncrSt=>PostTransSt]	1279	1			T13	7		T40	11		T38	7
arcs[CntIncrSt=>CntProgSt]	27741	1			T3	17		T4	14		T6	5
arcs[CntProgSt=>PostTransSt]	3754	1			T4	14		T13	12		T19	17
arcs[CntProgSt=>TransCheckSt]	22970	1			T3	17		T6	5		T13	42
arcs[TransCheckSt=>PostTransSt]	3151	1			T13	9		T15	29		T40	9
arcs[TransCheckSt=>TokenHashSt]	19687	1			T3	17		T6	5		T13	33
arcs[TokenHashSt=>PostTransSt]	8550	1			T13	19		T15	9		T17	61
arcs[TokenHashSt=>FlashRmaSt]	10234	1			T3	17		T6	5		T13	14
arcs[FlashRmaSt=>TokenCheck0St]	10195	1			T3	17		T6	5		T13	14
arcs[TokenCheck0St=>PostTransSt]	2762	1			T13	7		T15	22		T37	14
arcs[TokenCheck0St=>TokenCheck1St]	7373	1			T3	17		T6	5		T13	7
arcs[TokenCheck1St=>PostTransSt]	593	1			T13	1		T15	7		T37	1
arcs[TransProgSt=>PostTransSt]	6022	1			T3	17		T6	5		T13	6
arcs[IdleSt=>EscalateSt]	131	1			T16	6		T36	2		T65	5
arcs[ClkMuxSt=>EscalateSt]	34	1			T16	5		T65	2		T66	2
arcs[CntIncrSt=>EscalateSt]	59	1			T67	2		T36	1		T65	5
arcs[CntProgSt=>EscalateSt]	1017	1			T16	15		T67	31		T36	18
arcs[TransCheckSt=>EscalateSt]	132	1			T16	2		T67	1		T65	5
arcs[TokenHashSt=>EscalateSt]	903	1			T16	12		T67	8		T36	4
arcs[FlashRmaSt=>EscalateSt]	39	1			T67	2		T68	1		T69	2
arcs[TokenCheck0St=>EscalateSt]	60	1			T16	3		T67	1		T36	1
arcs[TokenCheck1St=>EscalateSt]	27	1			T16	1		T36	1		T66	2
arcs[TransProgSt=>EscalateSt]	731	1			T16	8		T67	21		T36	11
arcs[PostTransSt=>EscalateSt]	4169	1			T4	14		T13	12		T16	8
arcs[InvalidSt=>EscalateSt]	10323	1			T14	4		T11	3		T37	19

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5499802	1			T1	82		T2	11417		T3	1628
auto[0]	auto[IdleSt]	17124877	1			T1	162		T2	3883		T3	1444
auto[0]	auto[ClkMuxSt]	29176	1			T3	17		T4	14		T6	5
auto[0]	auto[CntIncrSt]	29044	1			T3	17		T4	14		T6	5
auto[0]	auto[CntProgSt]	1212212	1			T3	762		T4	28		T6	10
auto[0]	auto[TransCheckSt]	22889	1			T3	17		T6	5		T13	42
auto[0]	auto[TokenHashSt]	22440074	1			T3	355		T6	121		T13	3303
auto[0]	auto[FlashRmaSt]	30044	1			T3	17		T6	17		T13	57
auto[0]	auto[TokenCheck0St]	10154	1			T3	17		T6	5		T13	14
auto[0]	auto[TokenCheck1St]	7355	1			T3	17		T6	5		T13	7
auto[0]	auto[TransProgSt]	279131	1			T3	787		T6	10		T13	12
auto[0]	auto[PostTransSt]	9394794	1			T1	1102		T3	601		T4	1172
auto[0]	auto[ScrapSt]	85909	1			T2	11		T3	36		T16	6
auto[0]	auto[EscalateSt]	3771649	1			T4	1567		T13	1450		T14	796
auto[0]	auto[InvalidSt]	7821338	1			T2	4673		T14	598		T11	7085
auto[1]	auto[ResetSt]	163	1			T16	5		T67	5		T36	5
auto[1]	auto[IdleSt]	92	1			T16	4		T36	1		T65	4
auto[1]	auto[ClkMuxSt]	21	1			T16	3		T65	1		T66	2
auto[1]	auto[CntIncrSt]	35	1			T67	1		T65	3		T111	1
auto[1]	auto[CntProgSt]	682	1			T16	10		T67	24		T36	15
auto[1]	auto[TransCheckSt]	81	1			T16	2		T67	1		T65	5
auto[1]	auto[TokenHashSt]	639	1			T16	8		T67	4		T36	3
auto[1]	auto[FlashRmaSt]	28	1			T67	1		T68	1		T69	2
auto[1]	auto[TokenCheck0St]	41	1			T16	2		T67	1		T36	1
auto[1]	auto[TokenCheck1St]	18	1			T66	2		T111	1		T223	1
auto[1]	auto[TransProgSt]	497	1			T16	2		T67	15		T36	5
auto[1]	auto[PostTransSt]	2135	1			T4	5		T13	3		T16	4
auto[1]	auto[ScrapSt]	45	1			T16	2		T36	1		T65	1
auto[1]	auto[EscalateSt]	1161031	1			T4	490		T13	294		T14	196
auto[1]	auto[InvalidSt]	5168	1			T14	2		T11	2		T37	14

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5499786	1			T1	82		T2	11417		T3	1628
auto[0]	auto[IdleSt]	17124888	1			T1	162		T2	3883		T3	1444
auto[0]	auto[ClkMuxSt]	29170	1			T3	17		T4	14		T6	5
auto[0]	auto[CntIncrSt]	29043	1			T3	17		T4	14		T6	5
auto[0]	auto[CntProgSt]	1212212	1			T3	762		T4	28		T6	10
auto[0]	auto[TransCheckSt]	22881	1			T3	17		T6	5		T13	42
auto[0]	auto[TokenHashSt]	22440123	1			T3	355		T6	121		T13	3303
auto[0]	auto[FlashRmaSt]	30047	1			T3	17		T6	17		T13	57
auto[0]	auto[TokenCheck0St]	10157	1			T3	17		T6	5		T13	14
auto[0]	auto[TokenCheck1St]	7354	1			T3	17		T6	5		T13	7
auto[0]	auto[TransProgSt]	279155	1			T3	787		T6	10		T13	12
auto[0]	auto[PostTransSt]	9394778	1			T1	1102		T3	601		T4	1168
auto[0]	auto[ScrapSt]	85905	1			T2	11		T3	36		T16	6
auto[0]	auto[EscalateSt]	3780221	1			T4	1175		T13	862		T14	796
auto[0]	auto[InvalidSt]	7821351	1			T2	4673		T14	598		T11	7086
auto[1]	auto[ResetSt]	179	1			T16	3		T67	4		T36	4
auto[1]	auto[IdleSt]	81	1			T16	6		T36	1		T65	3
auto[1]	auto[ClkMuxSt]	27	1			T16	3		T65	1		T66	2
auto[1]	auto[CntIncrSt]	36	1			T67	1		T36	1		T65	2
auto[1]	auto[CntProgSt]	682	1			T16	6		T67	26		T36	11
auto[1]	auto[TransCheckSt]	89	1			T16	1		T65	3		T66	1
auto[1]	auto[TokenHashSt]	590	1			T16	9		T67	6		T36	1
auto[1]	auto[FlashRmaSt]	25	1			T67	2		T68	1		T69	2
auto[1]	auto[TokenCheck0St]	38	1			T16	2		T67	1		T36	1
auto[1]	auto[TokenCheck1St]	19	1			T16	1		T36	1		T66	1
auto[1]	auto[TransProgSt]	473	1			T16	8		T67	15		T36	11
auto[1]	auto[PostTransSt]	2151	1			T4	9		T13	9		T16	6
auto[1]	auto[ScrapSt]	49	1			T16	2		T67	1		T36	1
auto[1]	auto[EscalateSt]	1152459	1			T4	882		T13	882		T14	196
auto[1]	auto[InvalidSt]	5155	1			T14	2		T11	1		T37	5