Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 97.97 95.59 93.40 100.00 98.53 98.76 96.11


Total tests in report: 1001
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
66.36 66.36 81.60 81.60 46.62 46.62 56.17 56.17 51.16 51.16 82.53 82.53 92.04 92.04 54.42 54.42 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2580073690
76.38 10.02 88.44 6.84 73.72 27.09 72.08 15.91 55.81 4.65 88.63 6.11 93.78 1.74 62.19 7.77 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.775679558
81.76 5.39 88.65 0.20 76.06 2.34 73.85 1.77 81.40 25.58 90.11 1.47 94.28 0.50 68.02 5.83 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2116780352
83.97 2.21 94.93 6.28 76.06 0.00 74.09 0.24 83.72 2.33 91.58 1.47 94.28 0.00 73.14 5.12 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.207386922
86.17 2.20 94.93 0.00 77.59 1.53 84.53 10.43 83.72 0.00 92.00 0.42 94.28 0.00 76.15 3.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.703303526
87.90 1.73 95.03 0.10 81.55 3.96 87.80 3.28 86.05 2.33 92.42 0.42 94.53 0.25 77.92 1.77 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1442317432
89.31 1.41 96.05 1.01 84.70 3.15 88.05 0.24 86.05 0.00 93.68 1.26 95.52 1.00 81.10 3.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3865787754
90.54 1.23 96.15 0.10 87.49 2.79 88.09 0.04 86.05 0.00 94.32 0.63 96.52 1.00 85.16 4.06 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3242643563
91.43 0.90 96.20 0.05 87.49 0.00 88.22 0.13 90.70 4.65 94.53 0.21 96.52 0.00 86.40 1.24 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.530862905
92.28 0.85 96.71 0.51 89.20 1.71 88.39 0.17 93.02 2.33 95.58 1.05 96.52 0.00 86.57 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1107955851
92.85 0.57 96.76 0.05 90.10 0.90 88.86 0.47 93.02 0.00 95.79 0.21 96.77 0.25 88.69 2.12 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1700703563
93.37 0.51 96.91 0.15 91.09 0.99 88.86 0.00 93.02 0.00 96.21 0.42 97.01 0.25 90.46 1.77 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3315508851
93.78 0.41 97.06 0.15 91.18 0.09 89.11 0.25 93.02 0.00 96.84 0.63 97.01 0.00 92.23 1.77 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.331728532
94.17 0.39 97.06 0.00 91.18 0.00 91.52 2.41 93.02 0.00 96.84 0.00 97.01 0.00 92.58 0.35 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.2913758263
94.55 0.38 97.06 0.00 91.27 0.09 91.52 0.00 95.35 2.33 97.05 0.21 97.01 0.00 92.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3358045310
94.88 0.33 97.06 0.00 91.27 0.00 91.52 0.00 97.67 2.33 97.05 0.00 97.01 0.00 92.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.4017944236
95.21 0.33 97.06 0.00 91.27 0.00 91.52 0.00 100.00 2.33 97.05 0.00 97.01 0.00 92.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.3335470314
95.49 0.27 97.16 0.10 91.63 0.36 91.52 0.00 100.00 0.00 97.26 0.21 97.01 0.00 93.82 1.24 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.43927372
95.70 0.21 97.16 0.00 91.63 0.00 91.52 0.00 100.00 0.00 97.26 0.00 98.51 1.49 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1940984144
95.89 0.19 97.52 0.35 92.53 0.90 91.60 0.08 100.00 0.00 97.26 0.00 98.51 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.3547753929
96.05 0.16 97.57 0.05 92.53 0.00 92.27 0.67 100.00 0.00 97.47 0.21 98.51 0.00 93.99 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3026925347
96.19 0.14 97.57 0.00 93.16 0.63 92.27 0.00 100.00 0.00 97.47 0.00 98.51 0.00 94.35 0.35 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3593146134
96.31 0.12 97.72 0.15 93.25 0.09 92.33 0.06 100.00 0.00 97.68 0.21 98.51 0.00 94.70 0.35 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.3457868352
96.42 0.11 97.87 0.15 93.25 0.00 92.34 0.01 100.00 0.00 98.11 0.42 98.51 0.00 94.88 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.4287954858
96.53 0.11 97.87 0.00 93.25 0.00 92.91 0.57 100.00 0.00 98.11 0.00 98.51 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.3086602359
96.59 0.06 97.87 0.00 93.52 0.27 92.91 0.00 100.00 0.00 98.11 0.00 98.51 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1059503197
96.65 0.06 97.97 0.10 93.61 0.09 92.91 0.00 100.00 0.00 98.32 0.21 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1858134991
96.70 0.06 97.97 0.00 93.79 0.18 92.91 0.00 100.00 0.00 98.53 0.21 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.406803464
96.76 0.05 97.97 0.00 94.15 0.36 92.91 0.00 100.00 0.00 98.53 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1082118234
96.80 0.05 97.97 0.00 94.15 0.00 93.23 0.32 100.00 0.00 98.53 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.4165556406
96.84 0.04 97.97 0.00 94.42 0.27 93.23 0.00 100.00 0.00 98.53 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.189120711
96.88 0.04 97.97 0.00 94.69 0.27 93.23 0.00 100.00 0.00 98.53 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2065935097
96.92 0.04 97.97 0.00 94.96 0.27 93.23 0.00 100.00 0.00 98.53 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1021741260
96.95 0.04 97.97 0.00 94.96 0.00 93.23 0.00 100.00 0.00 98.53 0.00 98.76 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4171589794
96.98 0.03 97.97 0.00 94.96 0.00 93.26 0.03 100.00 0.00 98.53 0.00 98.76 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.1941512774
97.01 0.03 97.97 0.00 95.14 0.18 93.26 0.00 100.00 0.00 98.53 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.737016335
97.03 0.03 97.97 0.00 95.32 0.18 93.26 0.00 100.00 0.00 98.53 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.75024150
97.06 0.03 97.97 0.00 95.32 0.00 93.26 0.00 100.00 0.00 98.53 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.767001479
97.08 0.03 97.97 0.00 95.32 0.00 93.26 0.00 100.00 0.00 98.53 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2262345773
97.11 0.03 97.97 0.00 95.32 0.00 93.26 0.00 100.00 0.00 98.53 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1981134748
97.14 0.03 97.97 0.00 95.32 0.00 93.26 0.00 100.00 0.00 98.53 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.668691859
97.16 0.02 97.97 0.00 95.32 0.00 93.40 0.14 100.00 0.00 98.53 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2211626512
97.17 0.01 97.97 0.00 95.41 0.09 93.40 0.00 100.00 0.00 98.53 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2707318500
97.18 0.01 97.97 0.00 95.50 0.09 93.40 0.00 100.00 0.00 98.53 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4044957992
97.19 0.01 97.97 0.00 95.59 0.09 93.40 0.00 100.00 0.00 98.53 0.00 98.76 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.352195378

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4212410920
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1877490107
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2158834105
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.942040607
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2954278266
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3088914498
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.716200288
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1842858616
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3764618770
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3865870993
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.674893182
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2671745188
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.755992743
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.544860374
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.713996516
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.746934793
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1057407457
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.567497099
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2589725070
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4102444375
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3733787785
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.318256837
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.389002762
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1898111306
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4150842853
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4153600945
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1633245370
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.325572974
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1367283725
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1908704027
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2510372586
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3766949802
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2004782296
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2041587484
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2384322260
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3498746292
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2537648115
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1368555576
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.763321297
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.51926420
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3405260972
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.837438613
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.459506265
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2815896432
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.42451517
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.107698323
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Total test records in report: 1001
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3295895970 Sep 24 10:59:06 PM UTC 24 Sep 24 10:59:08 PM UTC 24 14052497 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1442317432 Sep 24 10:59:46 PM UTC 24 Sep 24 11:00:35 PM UTC 24 206244931 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1827573238 Sep 24 10:59:05 PM UTC 24 Sep 24 10:59:10 PM UTC 24 228626060 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.767001479 Sep 24 10:59:08 PM UTC 24 Sep 24 10:59:10 PM UTC 24 35882453 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.248205832 Sep 24 10:59:07 PM UTC 24 Sep 24 10:59:12 PM UTC 24 85968174 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.1187948921 Sep 24 10:59:09 PM UTC 24 Sep 24 10:59:14 PM UTC 24 3018874610 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1945758020 Sep 24 10:59:08 PM UTC 24 Sep 24 10:59:17 PM UTC 24 1010269556 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2580073690 Sep 24 10:59:07 PM UTC 24 Sep 24 10:59:18 PM UTC 24 305064679 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.2132627015 Sep 24 10:59:09 PM UTC 24 Sep 24 10:59:18 PM UTC 24 1004530269 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.1941512774 Sep 24 10:59:06 PM UTC 24 Sep 24 10:59:20 PM UTC 24 142246589 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.3547753929 Sep 24 10:59:19 PM UTC 24 Sep 24 10:59:21 PM UTC 24 20108629 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.331728532 Sep 24 10:59:12 PM UTC 24 Sep 24 10:59:23 PM UTC 24 1202559632 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1107955851 Sep 24 10:59:22 PM UTC 24 Sep 24 10:59:24 PM UTC 24 38917716 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2116780352 Sep 24 10:59:08 PM UTC 24 Sep 24 10:59:24 PM UTC 24 280714533 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.1372536515 Sep 24 10:59:13 PM UTC 24 Sep 24 10:59:25 PM UTC 24 500644625 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1612536608 Sep 24 10:59:20 PM UTC 24 Sep 24 10:59:25 PM UTC 24 193280135 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.2972821898 Sep 24 10:59:08 PM UTC 24 Sep 24 10:59:30 PM UTC 24 377980248 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2797266904 Sep 24 10:59:11 PM UTC 24 Sep 24 10:59:30 PM UTC 24 708525105 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.775679558 Sep 24 10:59:08 PM UTC 24 Sep 24 10:59:31 PM UTC 24 2759703854 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.4287954858 Sep 24 10:59:08 PM UTC 24 Sep 24 10:59:31 PM UTC 24 9807984488 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1955344640 Sep 24 10:59:26 PM UTC 24 Sep 24 10:59:33 PM UTC 24 395127383 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2262345773 Sep 24 10:59:31 PM UTC 24 Sep 24 10:59:33 PM UTC 24 11094314 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3531009740 Sep 24 10:59:11 PM UTC 24 Sep 24 10:59:34 PM UTC 24 1671024405 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1011034647 Sep 24 10:59:06 PM UTC 24 Sep 24 10:59:35 PM UTC 24 964615594 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1869730943 Sep 24 10:59:31 PM UTC 24 Sep 24 10:59:35 PM UTC 24 320447216 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.2865997346 Sep 24 10:59:26 PM UTC 24 Sep 24 10:59:38 PM UTC 24 74222406 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.1139785093 Sep 24 10:59:35 PM UTC 24 Sep 24 10:59:39 PM UTC 24 97348483 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.3457868352 Sep 24 10:59:30 PM UTC 24 Sep 24 10:59:40 PM UTC 24 789438607 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.530862905 Sep 24 10:59:26 PM UTC 24 Sep 24 10:59:42 PM UTC 24 507303669 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.4066956981 Sep 24 10:59:26 PM UTC 24 Sep 24 10:59:45 PM UTC 24 2338178164 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.712483625 Sep 24 10:59:35 PM UTC 24 Sep 24 10:59:47 PM UTC 24 3656561031 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3771640760 Sep 24 10:59:48 PM UTC 24 Sep 24 10:59:51 PM UTC 24 26374683 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.3982370070 Sep 24 10:59:48 PM UTC 24 Sep 24 10:59:51 PM UTC 24 25499259 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2494790366 Sep 24 10:59:49 PM UTC 24 Sep 24 10:59:52 PM UTC 24 14908305 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.118184636 Sep 24 10:59:39 PM UTC 24 Sep 24 10:59:54 PM UTC 24 5288380865 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3865787754 Sep 24 10:59:35 PM UTC 24 Sep 24 10:59:54 PM UTC 24 636492847 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.147475002 Sep 24 10:59:32 PM UTC 24 Sep 24 10:59:55 PM UTC 24 371221140 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1094812687 Sep 24 10:59:36 PM UTC 24 Sep 24 10:59:55 PM UTC 24 2295931207 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2594044968 Sep 24 10:59:19 PM UTC 24 Sep 24 10:59:57 PM UTC 24 846004082 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2837118946 Sep 24 10:59:56 PM UTC 24 Sep 24 10:59:59 PM UTC 24 13802727 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.861433294 Sep 24 10:59:09 PM UTC 24 Sep 24 10:59:59 PM UTC 24 2159647820 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1613085554 Sep 24 10:59:54 PM UTC 24 Sep 24 11:00:02 PM UTC 24 503807603 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.703303526 Sep 24 10:59:23 PM UTC 24 Sep 24 11:00:03 PM UTC 24 327466644 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.156094126 Sep 24 10:59:36 PM UTC 24 Sep 24 11:00:05 PM UTC 24 10496216434 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.426927188 Sep 24 10:59:58 PM UTC 24 Sep 24 11:00:05 PM UTC 24 270868838 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3376308624 Sep 24 10:59:52 PM UTC 24 Sep 24 11:00:06 PM UTC 24 73439563 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1267207898 Sep 24 10:59:40 PM UTC 24 Sep 24 11:00:07 PM UTC 24 3010697633 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.4123364345 Sep 24 11:00:23 PM UTC 24 Sep 24 11:00:45 PM UTC 24 1481906079 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.4221266947 Sep 24 10:59:55 PM UTC 24 Sep 24 11:00:07 PM UTC 24 335059838 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.43927372 Sep 24 10:59:35 PM UTC 24 Sep 24 11:00:08 PM UTC 24 2902666625 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2604394166 Sep 24 10:59:55 PM UTC 24 Sep 24 11:00:10 PM UTC 24 1793112992 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2219317690 Sep 24 10:59:56 PM UTC 24 Sep 24 11:00:15 PM UTC 24 231513045 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.559815591 Sep 24 11:00:08 PM UTC 24 Sep 24 11:00:19 PM UTC 24 628793662 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1986499811 Sep 24 11:00:16 PM UTC 24 Sep 24 11:00:19 PM UTC 24 69410514 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.2340482786 Sep 24 11:00:08 PM UTC 24 Sep 24 11:00:20 PM UTC 24 1949734480 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3498087821 Sep 24 11:00:00 PM UTC 24 Sep 24 11:00:20 PM UTC 24 765063729 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.162366556 Sep 24 11:00:19 PM UTC 24 Sep 24 11:00:22 PM UTC 24 20126439 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1947755502 Sep 24 11:00:20 PM UTC 24 Sep 24 11:00:22 PM UTC 24 38399338 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2707497358 Sep 24 11:00:08 PM UTC 24 Sep 24 11:00:23 PM UTC 24 2742006169 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.2298403037 Sep 24 11:00:10 PM UTC 24 Sep 24 11:00:24 PM UTC 24 626442967 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3715638792 Sep 24 10:59:08 PM UTC 24 Sep 24 11:00:25 PM UTC 24 10555042794 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.2333270931 Sep 24 11:00:20 PM UTC 24 Sep 24 11:00:26 PM UTC 24 85814036 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.131038593 Sep 24 11:00:25 PM UTC 24 Sep 24 11:00:27 PM UTC 24 35623844 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.392502737 Sep 24 11:00:32 PM UTC 24 Sep 24 11:00:47 PM UTC 24 2710837561 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.4144177559 Sep 24 11:00:23 PM UTC 24 Sep 24 11:00:30 PM UTC 24 591976115 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.207386922 Sep 24 11:00:08 PM UTC 24 Sep 24 11:00:31 PM UTC 24 314172600 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.524518255 Sep 24 11:00:26 PM UTC 24 Sep 24 11:00:34 PM UTC 24 202651423 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.651010176 Sep 24 10:59:52 PM UTC 24 Sep 24 11:00:35 PM UTC 24 1302734706 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1797819480 Sep 24 11:00:08 PM UTC 24 Sep 24 11:00:35 PM UTC 24 1723870191 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.2058702474 Sep 24 10:59:59 PM UTC 24 Sep 24 11:00:36 PM UTC 24 1634624117 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2855086040 Sep 24 11:00:08 PM UTC 24 Sep 24 11:00:36 PM UTC 24 1676773797 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.912268607 Sep 24 11:00:24 PM UTC 24 Sep 24 11:00:36 PM UTC 24 378468434 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.1338736624 Sep 24 11:00:24 PM UTC 24 Sep 24 11:00:37 PM UTC 24 328900890 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1817969692 Sep 24 11:00:29 PM UTC 24 Sep 24 11:00:38 PM UTC 24 330250879 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1841744270 Sep 24 11:00:38 PM UTC 24 Sep 24 11:00:41 PM UTC 24 36049139 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3486670876 Sep 24 11:00:11 PM UTC 24 Sep 24 11:00:43 PM UTC 24 115828096 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.4162591708 Sep 24 11:00:39 PM UTC 24 Sep 24 11:00:44 PM UTC 24 171685159 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.935385616 Sep 24 11:00:42 PM UTC 24 Sep 24 11:00:44 PM UTC 24 15669897 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2141871056 Sep 24 11:00:37 PM UTC 24 Sep 24 11:01:07 PM UTC 24 3275469730 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.616481410 Sep 24 11:00:45 PM UTC 24 Sep 24 11:00:48 PM UTC 24 28773996 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.986223021 Sep 24 11:00:37 PM UTC 24 Sep 24 11:00:49 PM UTC 24 166177233 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.813460429 Sep 24 11:00:50 PM UTC 24 Sep 24 11:00:52 PM UTC 24 13485957 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2082907933 Sep 24 11:00:32 PM UTC 24 Sep 24 11:00:53 PM UTC 24 2250515886 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.560881713 Sep 24 11:00:37 PM UTC 24 Sep 24 11:00:54 PM UTC 24 327764270 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.1277123873 Sep 24 11:00:20 PM UTC 24 Sep 24 11:00:55 PM UTC 24 1488551348 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.4112105039 Sep 24 11:00:37 PM UTC 24 Sep 24 11:00:58 PM UTC 24 317433888 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.761173373 Sep 24 11:00:35 PM UTC 24 Sep 24 11:00:58 PM UTC 24 910539914 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.262818820 Sep 24 11:00:54 PM UTC 24 Sep 24 11:00:59 PM UTC 24 852515012 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.3811670519 Sep 24 11:00:45 PM UTC 24 Sep 24 11:00:59 PM UTC 24 101762043 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.314231277 Sep 24 11:00:50 PM UTC 24 Sep 24 11:01:00 PM UTC 24 587301785 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.3086602359 Sep 24 10:59:32 PM UTC 24 Sep 24 11:01:01 PM UTC 24 1904650561 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.4055340628 Sep 24 11:00:29 PM UTC 24 Sep 24 11:01:04 PM UTC 24 3166650643 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.2558135024 Sep 24 11:00:48 PM UTC 24 Sep 24 11:01:04 PM UTC 24 3742255315 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.1467492955 Sep 24 11:00:56 PM UTC 24 Sep 24 11:01:06 PM UTC 24 1889986433 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1167274845 Sep 24 11:00:44 PM UTC 24 Sep 24 11:01:06 PM UTC 24 296250917 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.1565990368 Sep 24 11:01:05 PM UTC 24 Sep 24 11:01:08 PM UTC 24 19544954 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2491581032 Sep 24 11:00:48 PM UTC 24 Sep 24 11:01:09 PM UTC 24 3962799612 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.2185594572 Sep 24 11:00:54 PM UTC 24 Sep 24 11:01:10 PM UTC 24 1127185249 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.584095091 Sep 24 11:01:08 PM UTC 24 Sep 24 11:01:10 PM UTC 24 24093593 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.4293614372 Sep 24 11:01:08 PM UTC 24 Sep 24 11:01:10 PM UTC 24 33423500 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.4187986863 Sep 24 11:01:00 PM UTC 24 Sep 24 11:01:11 PM UTC 24 4613747728 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2610506493 Sep 24 11:01:00 PM UTC 24 Sep 24 11:01:12 PM UTC 24 299195173 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3604666582 Sep 24 11:00:08 PM UTC 24 Sep 24 11:01:14 PM UTC 24 3539335192 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3609942018 Sep 24 11:01:13 PM UTC 24 Sep 24 11:01:15 PM UTC 24 35301791 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.3326720279 Sep 24 11:00:30 PM UTC 24 Sep 24 11:01:17 PM UTC 24 11116707634 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.3279011017 Sep 24 11:01:09 PM UTC 24 Sep 24 11:01:17 PM UTC 24 258700590 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.1864077468 Sep 24 11:02:17 PM UTC 24 Sep 24 11:02:23 PM UTC 24 321712489 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.1085188333 Sep 24 11:01:13 PM UTC 24 Sep 24 11:01:18 PM UTC 24 509008131 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.3756542872 Sep 24 11:01:10 PM UTC 24 Sep 24 11:01:18 PM UTC 24 98572245 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.911613052 Sep 24 11:01:01 PM UTC 24 Sep 24 11:01:20 PM UTC 24 782421157 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.2857683000 Sep 24 11:00:27 PM UTC 24 Sep 24 11:01:21 PM UTC 24 2121299999 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2729729259 Sep 24 11:01:11 PM UTC 24 Sep 24 11:01:24 PM UTC 24 244183518 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2094447213 Sep 24 11:01:18 PM UTC 24 Sep 24 11:01:26 PM UTC 24 284387238 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.1727082590 Sep 24 11:01:11 PM UTC 24 Sep 24 11:01:26 PM UTC 24 356884442 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.650569011 Sep 24 11:01:11 PM UTC 24 Sep 24 11:01:30 PM UTC 24 352827977 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2119493767 Sep 24 11:01:18 PM UTC 24 Sep 24 11:01:34 PM UTC 24 2352230669 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1113646306 Sep 24 11:01:08 PM UTC 24 Sep 24 11:01:34 PM UTC 24 2633018989 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2070823059 Sep 24 11:01:00 PM UTC 24 Sep 24 11:01:35 PM UTC 24 1422948192 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1700703563 Sep 24 11:00:37 PM UTC 24 Sep 24 11:01:35 PM UTC 24 1045195359 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2800616958 Sep 24 11:01:34 PM UTC 24 Sep 24 11:01:37 PM UTC 24 21678893 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2146860867 Sep 24 11:01:36 PM UTC 24 Sep 24 11:01:38 PM UTC 24 14094452 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.3829415054 Sep 24 11:01:36 PM UTC 24 Sep 24 11:01:39 PM UTC 24 38126718 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.3543458365 Sep 24 11:01:26 PM UTC 24 Sep 24 11:01:40 PM UTC 24 1707146124 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.571498242 Sep 24 11:01:23 PM UTC 24 Sep 24 11:01:42 PM UTC 24 679260529 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3867732838 Sep 24 11:01:22 PM UTC 24 Sep 24 11:01:43 PM UTC 24 6605155266 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.376811715 Sep 24 11:01:27 PM UTC 24 Sep 24 11:01:44 PM UTC 24 1478214507 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1088099587 Sep 24 11:01:39 PM UTC 24 Sep 24 11:01:45 PM UTC 24 95376534 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.4228926803 Sep 24 11:00:53 PM UTC 24 Sep 24 11:01:45 PM UTC 24 2226257839 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.1696722017 Sep 24 11:01:45 PM UTC 24 Sep 24 11:01:47 PM UTC 24 13590306 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3915069784 Sep 24 11:01:38 PM UTC 24 Sep 24 11:01:47 PM UTC 24 67211751 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.197147290 Sep 24 11:01:45 PM UTC 24 Sep 24 11:01:53 PM UTC 24 875046067 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.373500656 Sep 24 11:01:16 PM UTC 24 Sep 24 11:01:54 PM UTC 24 1984539225 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1164581402 Sep 24 11:01:40 PM UTC 24 Sep 24 11:01:54 PM UTC 24 2641779465 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.3098000486 Sep 24 11:01:05 PM UTC 24 Sep 24 11:01:56 PM UTC 24 2097335189 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1073733277 Sep 24 11:00:59 PM UTC 24 Sep 24 11:01:58 PM UTC 24 6527679820 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3942140628 Sep 24 11:01:48 PM UTC 24 Sep 24 11:01:58 PM UTC 24 1421240649 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.814151336 Sep 24 11:01:39 PM UTC 24 Sep 24 11:01:58 PM UTC 24 640775431 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3693066187 Sep 24 11:01:18 PM UTC 24 Sep 24 11:01:59 PM UTC 24 6872428189 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.1014620071 Sep 24 11:01:46 PM UTC 24 Sep 24 11:02:02 PM UTC 24 1313272107 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3756806593 Sep 24 11:01:54 PM UTC 24 Sep 24 11:02:03 PM UTC 24 886860521 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.2430024968 Sep 24 11:02:01 PM UTC 24 Sep 24 11:02:03 PM UTC 24 25857006 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2182684441 Sep 24 11:01:18 PM UTC 24 Sep 24 11:02:06 PM UTC 24 1745919780 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.260233692 Sep 24 11:01:42 PM UTC 24 Sep 24 11:02:06 PM UTC 24 295294193 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1418621648 Sep 24 11:02:04 PM UTC 24 Sep 24 11:02:06 PM UTC 24 19357182 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3736464568 Sep 24 11:02:03 PM UTC 24 Sep 24 11:02:09 PM UTC 24 266096823 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3289949602 Sep 24 11:01:30 PM UTC 24 Sep 24 11:02:10 PM UTC 24 1158575131 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.174661099 Sep 24 11:02:07 PM UTC 24 Sep 24 11:02:10 PM UTC 24 90812031 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3214738189 Sep 24 11:01:55 PM UTC 24 Sep 24 11:02:11 PM UTC 24 966580978 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2603673095 Sep 24 11:01:57 PM UTC 24 Sep 24 11:02:12 PM UTC 24 389162112 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.887516591 Sep 24 11:01:54 PM UTC 24 Sep 24 11:02:14 PM UTC 24 715800050 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.2668493701 Sep 24 11:02:12 PM UTC 24 Sep 24 11:02:14 PM UTC 24 48064895 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.2892865663 Sep 24 11:01:37 PM UTC 24 Sep 24 11:02:14 PM UTC 24 1047272550 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2395901702 Sep 24 11:02:12 PM UTC 24 Sep 24 11:02:16 PM UTC 24 591886257 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.924844982 Sep 24 11:01:59 PM UTC 24 Sep 24 11:02:19 PM UTC 24 1497867968 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2807361251 Sep 24 11:01:55 PM UTC 24 Sep 24 11:02:19 PM UTC 24 1270937758 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.1298565273 Sep 24 11:02:07 PM UTC 24 Sep 24 11:02:21 PM UTC 24 106489793 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.2190309869 Sep 24 11:02:09 PM UTC 24 Sep 24 11:02:22 PM UTC 24 198376924 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.3726085016 Sep 24 11:02:14 PM UTC 24 Sep 24 11:02:24 PM UTC 24 2979544885 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.245032611 Sep 24 11:02:13 PM UTC 24 Sep 24 11:02:26 PM UTC 24 460904910 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.3371244277 Sep 24 11:02:07 PM UTC 24 Sep 24 11:02:27 PM UTC 24 396759338 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.392532053 Sep 24 11:01:15 PM UTC 24 Sep 24 11:02:29 PM UTC 24 6453611403 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.399593148 Sep 24 11:02:27 PM UTC 24 Sep 24 11:02:30 PM UTC 24 242302219 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2470795936 Sep 24 11:02:27 PM UTC 24 Sep 24 11:02:30 PM UTC 24 17751978 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1623981525 Sep 24 11:02:28 PM UTC 24 Sep 24 11:02:30 PM UTC 24 13718729 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2342489182 Sep 24 11:00:55 PM UTC 24 Sep 24 11:02:32 PM UTC 24 12755444768 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.2132322746 Sep 24 11:02:10 PM UTC 24 Sep 24 11:02:33 PM UTC 24 1073613884 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.2896517771 Sep 24 11:02:16 PM UTC 24 Sep 24 11:02:35 PM UTC 24 714896698 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2441668123 Sep 24 11:02:20 PM UTC 24 Sep 24 11:02:36 PM UTC 24 1256168039 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1527483960 Sep 24 11:02:30 PM UTC 24 Sep 24 11:02:36 PM UTC 24 89521532 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.666191115 Sep 24 11:02:35 PM UTC 24 Sep 24 11:02:37 PM UTC 24 10908653 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.982566023 Sep 24 11:02:22 PM UTC 24 Sep 24 11:02:38 PM UTC 24 4799839791 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2370209039 Sep 24 11:02:23 PM UTC 24 Sep 24 11:02:38 PM UTC 24 248019188 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.396042752 Sep 24 11:02:36 PM UTC 24 Sep 24 11:02:40 PM UTC 24 76556109 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.1733848953 Sep 24 11:02:20 PM UTC 24 Sep 24 11:02:40 PM UTC 24 423637900 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.624531352 Sep 24 11:02:30 PM UTC 24 Sep 24 11:02:42 PM UTC 24 819509542 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.357118889 Sep 24 11:02:39 PM UTC 24 Sep 24 11:02:42 PM UTC 24 45880905 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.770165819 Sep 24 11:02:04 PM UTC 24 Sep 24 11:02:43 PM UTC 24 664335053 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3623000091 Sep 24 11:02:34 PM UTC 24 Sep 24 11:02:43 PM UTC 24 220820224 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.88108026 Sep 24 11:02:40 PM UTC 24 Sep 24 11:02:44 PM UTC 24 411635079 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1951204738 Sep 24 11:02:33 PM UTC 24 Sep 24 11:02:46 PM UTC 24 402394814 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1944174869 Sep 24 11:02:45 PM UTC 24 Sep 24 11:02:47 PM UTC 24 67124244 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1721008928 Sep 24 11:02:37 PM UTC 24 Sep 24 11:02:48 PM UTC 24 303975320 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.2913758263 Sep 24 11:01:46 PM UTC 24 Sep 24 11:02:49 PM UTC 24 1741189762 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3026925347 Sep 24 10:59:15 PM UTC 24 Sep 24 11:02:50 PM UTC 24 8347437407 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1672517824 Sep 24 11:02:37 PM UTC 24 Sep 24 11:02:50 PM UTC 24 310918630 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1080270708 Sep 24 11:02:48 PM UTC 24 Sep 24 11:02:50 PM UTC 24 50366099 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.4084116495 Sep 24 11:02:31 PM UTC 24 Sep 24 11:02:53 PM UTC 24 955527680 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.3868816182 Sep 24 11:02:47 PM UTC 24 Sep 24 11:02:53 PM UTC 24 160875236 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1599779986 Sep 24 11:02:24 PM UTC 24 Sep 24 11:02:53 PM UTC 24 29524982999 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1143832211 Sep 24 11:02:51 PM UTC 24 Sep 24 11:02:56 PM UTC 24 122803916 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.668691859 Sep 24 11:02:54 PM UTC 24 Sep 24 11:02:56 PM UTC 24 10457297 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2964284945 Sep 24 11:02:49 PM UTC 24 Sep 24 11:03:01 PM UTC 24 84792323 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.3416101940 Sep 24 11:02:53 PM UTC 24 Sep 24 11:03:01 PM UTC 24 777711196 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1049199371 Sep 24 11:02:42 PM UTC 24 Sep 24 11:03:01 PM UTC 24 849901536 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1795765767 Sep 24 11:02:42 PM UTC 24 Sep 24 11:03:01 PM UTC 24 655941983 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.3836799917 Sep 24 11:02:41 PM UTC 24 Sep 24 11:03:01 PM UTC 24 1347289304 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2452335680 Sep 24 11:01:27 PM UTC 24 Sep 24 11:03:05 PM UTC 24 4221169034 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.3100144611 Sep 24 11:02:51 PM UTC 24 Sep 24 11:03:07 PM UTC 24 1719768873 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.1100099844 Sep 24 11:02:54 PM UTC 24 Sep 24 11:03:07 PM UTC 24 1118886233 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.3509821053 Sep 24 11:03:02 PM UTC 24 Sep 24 11:03:08 PM UTC 24 563047069 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.970912221 Sep 24 11:03:02 PM UTC 24 Sep 24 11:03:10 PM UTC 24 661660648 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3231518542 Sep 24 11:02:51 PM UTC 24 Sep 24 11:03:10 PM UTC 24 1988849802 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3240948328 Sep 24 11:03:03 PM UTC 24 Sep 24 11:03:11 PM UTC 24 272847089 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.1592344713 Sep 24 11:03:11 PM UTC 24 Sep 24 11:03:13 PM UTC 24 39077499 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.454707421 Sep 24 11:02:30 PM UTC 24 Sep 24 11:03:14 PM UTC 24 1024639718 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.2881966341 Sep 24 11:02:57 PM UTC 24 Sep 24 11:03:14 PM UTC 24 380728633 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3388855304 Sep 24 11:03:14 PM UTC 24 Sep 24 11:03:16 PM UTC 24 11542968 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2216536923 Sep 24 11:03:12 PM UTC 24 Sep 24 11:03:17 PM UTC 24 103518836 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.1247981818 Sep 24 11:02:24 PM UTC 24 Sep 24 11:03:19 PM UTC 24 5957456771 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.2194263369 Sep 24 11:02:12 PM UTC 24 Sep 24 11:03:21 PM UTC 24 2295537533 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3837077385 Sep 24 11:02:41 PM UTC 24 Sep 24 11:03:22 PM UTC 24 1170583573 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.4145058160 Sep 24 11:03:05 PM UTC 24 Sep 24 11:03:22 PM UTC 24 1110363467 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2379827581 Sep 24 11:03:08 PM UTC 24 Sep 24 11:03:24 PM UTC 24 1982461444 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.2598240828 Sep 24 11:03:18 PM UTC 24 Sep 24 11:03:24 PM UTC 24 312684365 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.208763344 Sep 24 11:03:08 PM UTC 24 Sep 24 11:03:24 PM UTC 24 1658079588 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.1431299379 Sep 24 11:01:48 PM UTC 24 Sep 24 11:03:25 PM UTC 24 6425288493 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2778668741 Sep 24 11:03:16 PM UTC 24 Sep 24 11:03:27 PM UTC 24 137512194 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1743926750 Sep 24 11:03:21 PM UTC 24 Sep 24 11:03:28 PM UTC 24 327085939 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.3616216027 Sep 24 11:03:25 PM UTC 24 Sep 24 11:03:29 PM UTC 24 493966000 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.100139845 Sep 24 11:02:49 PM UTC 24 Sep 24 11:03:30 PM UTC 24 323786923 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2686473150 Sep 24 11:03:25 PM UTC 24 Sep 24 11:03:32 PM UTC 24 283573267 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2252260467 Sep 24 11:03:32 PM UTC 24 Sep 24 11:03:34 PM UTC 24 501523254 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.1198044989 Sep 24 10:59:41 PM UTC 24 Sep 24 11:03:35 PM UTC 24 10883192641 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1858134991 Sep 24 11:03:18 PM UTC 24 Sep 24 11:03:35 PM UTC 24 365550383 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4206050097 Sep 24 11:03:33 PM UTC 24 Sep 24 11:03:35 PM UTC 24 13111254 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.4046054915 Sep 24 11:03:02 PM UTC 24 Sep 24 11:03:36 PM UTC 24 5925471258 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.2303971856 Sep 24 11:03:33 PM UTC 24 Sep 24 11:03:37 PM UTC 24 33200772 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.116136278 Sep 24 11:03:20 PM UTC 24 Sep 24 11:03:38 PM UTC 24 2168622816 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2668313396 Sep 24 11:03:28 PM UTC 24 Sep 24 11:03:42 PM UTC 24 599341248 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.3069195829 Sep 24 11:03:37 PM UTC 24 Sep 24 11:03:42 PM UTC 24 87629550 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.4240463212 Sep 24 11:03:26 PM UTC 24 Sep 24 11:03:43 PM UTC 24 1336613512 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3056530058 Sep 24 11:03:03 PM UTC 24 Sep 24 11:03:45 PM UTC 24 4718399856 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.3073427429 Sep 24 11:03:16 PM UTC 24 Sep 24 11:03:46 PM UTC 24 1641527300 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1940962496 Sep 24 11:03:29 PM UTC 24 Sep 24 11:03:48 PM UTC 24 448899112 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1981134748 Sep 24 11:03:37 PM UTC 24 Sep 24 11:03:48 PM UTC 24 1796603491 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2211626512 Sep 24 11:03:35 PM UTC 24 Sep 24 11:03:48 PM UTC 24 58845106 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.3485796200 Sep 24 11:03:22 PM UTC 24 Sep 24 11:03:49 PM UTC 24 5803096016 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.4062890002 Sep 24 11:02:39 PM UTC 24 Sep 24 11:03:50 PM UTC 24 1788423804 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.3198722484 Sep 24 11:05:04 PM UTC 24 Sep 24 11:05:19 PM UTC 24 1050567365 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.5750520 Sep 24 11:05:08 PM UTC 24 Sep 24 11:05:20 PM UTC 24 1138054603 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.3402222815 Sep 24 11:03:44 PM UTC 24 Sep 24 11:03:51 PM UTC 24 685960880 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.2126139753 Sep 24 11:05:00 PM UTC 24 Sep 24 11:05:20 PM UTC 24 1415828478 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.1737444092 Sep 24 11:03:50 PM UTC 24 Sep 24 11:03:53 PM UTC 24 58795944 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3466640697 Sep 24 11:03:51 PM UTC 24 Sep 24 11:03:54 PM UTC 24 13485795 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.2286514714 Sep 24 11:02:57 PM UTC 24 Sep 24 11:03:54 PM UTC 24 3242439909 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.2899468129 Sep 24 11:03:38 PM UTC 24 Sep 24 11:03:54 PM UTC 24 5058535371 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.702189426 Sep 24 11:03:39 PM UTC 24 Sep 24 11:03:55 PM UTC 24 898553624 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.3855555608 Sep 24 11:03:51 PM UTC 24 Sep 24 11:03:55 PM UTC 24 121573182 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.3732177578 Sep 24 11:03:55 PM UTC 24 Sep 24 11:03:58 PM UTC 24 22717154 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.939984199 Sep 24 11:03:53 PM UTC 24 Sep 24 11:04:00 PM UTC 24 58029720 ps