Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65078105

1

T1

933

T2

6411

T3

7466

auto[1]

1122637

1

T3

990

T4

6861

T15

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65076213

1

T1

933

T2

6411

T3

7862

auto[1]

1124529

1

T3

594

T4

4698

T15

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5271381	1			T1	69		T2	703		T3	1611
auto[IdleSt]	16865878	1			T1	227		T2	1111		T3	2656
auto[ClkMuxSt]	29507	1			T2	8		T3	16		T13	1
auto[CntIncrSt]	29311	1			T2	8		T3	16		T13	1
auto[CntProgSt]	1481536	1			T2	30		T3	437		T13	2
auto[TransCheckSt]	23260	1			T2	8		T13	1		T4	25
auto[TokenHashSt]	20919930	1			T2	3321		T13	115		T4	741
auto[FlashRmaSt]	29630	1			T2	8		T13	1		T4	42
auto[TokenCheck0St]	10308	1			T2	8		T13	1		T4	17
auto[TokenCheck1St]	7434	1			T2	8		T13	1		T4	16
auto[TransProgSt]	361211	1			T2	35		T13	2		T4	40
auto[PostTransSt]	9856426	1			T1	637		T2	99		T3	1396
auto[ScrapSt]	188718	1			T2	1064		T14	23		T5	315
auto[EscalateSt]	4525887	1			T3	2324		T4	8668		T15	1893
auto[InvalidSt]	6598944	1			T15	1083		T20	340		T34	4928

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1381	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6598944	1			T15	1083		T20	340		T34	4928
EscalateSt	4525887	1			T3	2324		T4	8668		T15	1893
ScrapSt	188718	1			T2	1064		T14	23		T5	315
PostTransSt	9856426	1			T1	637		T2	99		T3	1396
TransProgSt	361211	1			T2	35		T13	2		T4	40
TokenCheck1St	7434	1			T2	8		T13	1		T4	16
TokenCheck0St	10308	1			T2	8		T13	1		T4	17
FlashRmaSt	29630	1			T2	8		T13	1		T4	42
TokenHashSt	20919930	1			T2	3321		T13	115		T4	741
TransCheckSt	23260	1			T2	8		T13	1		T4	25
CntProgSt	1481536	1			T2	30		T3	437		T13	2
CntIncrSt	29311	1			T2	8		T3	16		T13	1
ClkMuxSt	29507	1			T2	8		T3	16		T13	1
IdleSt	16865878	1			T1	227		T2	1111		T3	2656
ResetSt	5271381	1			T1	69		T2	703		T3	1611
arcs[ResetSt=>IdleSt]	42753	1			T1	1		T2	9		T3	17
arcs[IdleSt=>ScrapSt]	262	1			T2	1		T14	1		T5	1
arcs[IdleSt=>ClkMuxSt]	29346	1			T2	8		T3	16		T13	1
arcs[ClkMuxSt=>CntIncrSt]	29311	1			T2	8		T3	16		T13	1
arcs[CntIncrSt=>PostTransSt]	1325	1			T19	13		T44	18		T45	11
arcs[CntIncrSt=>CntProgSt]	27909	1			T2	8		T3	16		T13	1
arcs[CntProgSt=>PostTransSt]	3596	1			T3	16		T18	19		T19	12
arcs[CntProgSt=>TransCheckSt]	23260	1			T2	8		T13	1		T4	25
arcs[TransCheckSt=>PostTransSt]	3248	1			T19	11		T41	38		T44	13
arcs[TransCheckSt=>TokenHashSt]	19912	1			T2	8		T13	1		T4	25
arcs[TokenHashSt=>PostTransSt]	8769	1			T19	45		T43	9		T39	7
arcs[TokenHashSt=>FlashRmaSt]	10357	1			T2	8		T13	1		T4	18
arcs[FlashRmaSt=>TokenCheck0St]	10308	1			T2	8		T13	1		T4	17
arcs[TokenCheck0St=>PostTransSt]	2818	1			T19	10		T43	17		T39	22
arcs[TokenCheck0St=>TokenCheck1St]	7434	1			T2	8		T13	1		T4	16
arcs[TokenCheck1St=>PostTransSt]	624	1			T43	1		T41	7		T44	2
arcs[TransProgSt=>PostTransSt]	5957	1			T2	8		T13	1		T14	14
arcs[IdleSt=>EscalateSt]	150	1			T60	8		T61	4		T62	6
arcs[ClkMuxSt=>EscalateSt]	35	1			T60	3		T61	2		T62	1
arcs[CntIncrSt=>EscalateSt]	77	1			T4	2		T63	1		T64	3
arcs[CntProgSt=>EscalateSt]	1053	1			T4	22		T33	17		T63	7
arcs[TransCheckSt=>EscalateSt]	100	1			T33	1		T63	5		T64	4
arcs[TokenHashSt=>EscalateSt]	786	1			T4	7		T33	11		T63	23
arcs[FlashRmaSt=>EscalateSt]	49	1			T4	1		T44	1		T63	2
arcs[TokenCheck0St=>EscalateSt]	56	1			T4	1		T33	1		T63	3
arcs[TokenCheck1St=>EscalateSt]	40	1			T64	1		T61	1		T68	2
arcs[TransProgSt=>EscalateSt]	813	1			T4	16		T33	19		T63	6
arcs[PostTransSt=>EscalateSt]	3909	1			T3	16		T18	19		T19	12
arcs[InvalidSt=>EscalateSt]	9713	1			T15	7		T20	5		T34	65

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5271212	1			T1	69		T2	703		T3	1611
auto[0]	auto[IdleSt]	16865783	1			T1	227		T2	1111		T3	2656
auto[0]	auto[ClkMuxSt]	29489	1			T2	8		T3	16		T13	1
auto[0]	auto[CntIncrSt]	29254	1			T2	8		T3	16		T13	1
auto[0]	auto[CntProgSt]	1480834	1			T2	30		T3	437		T13	2
auto[0]	auto[TransCheckSt]	23193	1			T2	8		T13	1		T4	25
auto[0]	auto[TokenHashSt]	20919383	1			T2	3321		T13	115		T4	734
auto[0]	auto[FlashRmaSt]	29602	1			T2	8		T13	1		T4	41
auto[0]	auto[TokenCheck0St]	10262	1			T2	8		T13	1		T4	16
auto[0]	auto[TokenCheck1St]	7407	1			T2	8		T13	1		T4	16
auto[0]	auto[TransProgSt]	360665	1			T2	35		T13	2		T4	28
auto[0]	auto[PostTransSt]	9854446	1			T1	637		T2	99		T3	1386
auto[0]	auto[ScrapSt]	188664	1			T2	1064		T14	23		T5	315
auto[0]	auto[EscalateSt]	3412459	1			T3	1344		T4	1848		T15	1501
auto[0]	auto[InvalidSt]	6594071	1			T15	1079		T20	338		T34	4904
auto[1]	auto[ResetSt]	169	1			T4	1		T33	4		T63	3
auto[1]	auto[IdleSt]	95	1			T60	4		T61	3		T62	4
auto[1]	auto[ClkMuxSt]	18	1			T60	1		T61	2		T165	2
auto[1]	auto[CntIncrSt]	57	1			T4	1		T63	1		T64	3
auto[1]	auto[CntProgSt]	702	1			T4	18		T33	13		T63	4
auto[1]	auto[TransCheckSt]	67	1			T33	1		T63	2		T64	2
auto[1]	auto[TokenHashSt]	547	1			T4	7		T33	6		T63	17
auto[1]	auto[FlashRmaSt]	28	1			T4	1		T63	1		T60	1
auto[1]	auto[TokenCheck0St]	46	1			T4	1		T33	1		T63	3
auto[1]	auto[TokenCheck1St]	27	1			T64	1		T61	1		T68	1
auto[1]	auto[TransProgSt]	546	1			T4	12		T33	14		T63	5
auto[1]	auto[PostTransSt]	1980	1			T3	10		T18	9		T19	6
auto[1]	auto[ScrapSt]	54	1			T63	1		T64	1		T61	1
auto[1]	auto[EscalateSt]	1113428	1			T3	980		T4	6820		T15	392
auto[1]	auto[InvalidSt]	4873	1			T15	4		T20	2		T34	24

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5271203	1			T1	69		T2	703		T3	1611
auto[0]	auto[IdleSt]	16865779	1			T1	227		T2	1111		T3	2656
auto[0]	auto[ClkMuxSt]	29483	1			T2	8		T3	16		T13	1
auto[0]	auto[CntIncrSt]	29262	1			T2	8		T3	16		T13	1
auto[0]	auto[CntProgSt]	1480813	1			T2	30		T3	437		T13	2
auto[0]	auto[TransCheckSt]	23195	1			T2	8		T13	1		T4	25
auto[0]	auto[TokenHashSt]	20919421	1			T2	3321		T13	115		T4	740
auto[0]	auto[FlashRmaSt]	29592	1			T2	8		T13	1		T4	41
auto[0]	auto[TokenCheck0St]	10281	1			T2	8		T13	1		T4	16
auto[0]	auto[TokenCheck1St]	7408	1			T2	8		T13	1		T4	16
auto[0]	auto[TransProgSt]	360653	1			T2	35		T13	2		T4	30
auto[0]	auto[PostTransSt]	9854402	1			T1	637		T2	99		T3	1390
auto[0]	auto[ScrapSt]	188663	1			T2	1064		T14	23		T5	315
auto[0]	auto[EscalateSt]	3410573	1			T3	1736		T4	3998		T15	1599
auto[0]	auto[InvalidSt]	6594104	1			T15	1080		T20	337		T34	4887
auto[1]	auto[ResetSt]	178	1			T4	3		T33	4		T63	3
auto[1]	auto[IdleSt]	99	1			T60	5		T61	2		T62	3
auto[1]	auto[ClkMuxSt]	24	1			T60	2		T61	1		T62	1
auto[1]	auto[CntIncrSt]	49	1			T4	1		T64	1		T60	1
auto[1]	auto[CntProgSt]	723	1			T4	11		T33	11		T63	6
auto[1]	auto[TransCheckSt]	65	1			T63	3		T64	2		T241	5
auto[1]	auto[TokenHashSt]	509	1			T4	1		T33	8		T63	17
auto[1]	auto[FlashRmaSt]	38	1			T4	1		T44	1		T63	1
auto[1]	auto[TokenCheck0St]	27	1			T4	1		T33	1		T241	1
auto[1]	auto[TokenCheck1St]	26	1			T61	1		T68	2		T242	1
auto[1]	auto[TransProgSt]	558	1			T4	10		T33	10		T63	2
auto[1]	auto[PostTransSt]	2024	1			T3	6		T18	10		T19	6
auto[1]	auto[ScrapSt]	55	1			T63	1		T60	2		T61	1
auto[1]	auto[EscalateSt]	1115314	1			T3	588		T4	4670		T15	294
auto[1]	auto[InvalidSt]	4840	1			T15	3		T20	3		T34	41