Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.60 97.97 95.68 93.40 95.35 98.53 99.00 96.29


Total tests in report: 997
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.37 64.37 80.49 80.49 45.18 45.18 55.32 55.32 48.84 48.84 78.32 78.32 91.54 91.54 50.88 50.88 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2697992810
74.62 10.25 87.33 6.84 73.00 27.81 73.05 17.73 53.49 4.65 84.21 5.89 93.28 1.74 57.95 7.07 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2670886883
80.28 5.66 94.32 6.99 75.16 2.16 80.79 7.74 62.79 9.30 88.63 4.42 93.28 0.00 66.96 9.01 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2745442916
82.99 2.71 95.39 1.06 79.75 4.59 82.75 1.96 67.44 4.65 91.79 3.16 94.53 1.24 69.26 2.30 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.582427222
84.93 1.94 95.84 0.46 80.92 1.17 82.87 0.11 74.42 6.98 93.47 1.68 94.53 0.00 72.44 3.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.51535088
86.53 1.61 95.84 0.00 80.92 0.00 82.87 0.00 83.72 9.30 93.47 0.00 94.53 0.00 74.38 1.94 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3161304287
87.94 1.41 95.89 0.05 81.10 0.18 85.97 3.11 86.05 2.33 94.32 0.84 94.53 0.00 77.74 3.36 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1090798628
89.13 1.19 96.05 0.15 82.99 1.89 86.01 0.04 86.05 0.00 94.53 0.21 95.77 1.24 82.51 4.77 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3341928176
90.29 1.16 96.65 0.61 86.14 3.15 86.23 0.21 86.05 0.00 95.16 0.63 96.27 0.50 85.51 3.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1773305729
91.16 0.87 97.16 0.51 87.76 1.62 86.63 0.40 88.37 2.33 96.21 1.05 96.27 0.00 85.69 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.965671139
92.01 0.85 97.26 0.10 88.57 0.81 87.26 0.63 90.70 2.33 96.84 0.63 96.52 0.25 86.93 1.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3560468826
92.71 0.70 97.26 0.00 89.65 1.08 89.38 2.13 90.70 0.00 96.84 0.00 96.77 0.25 88.34 1.41 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3939093329
93.16 0.45 97.31 0.05 91.09 1.44 89.38 0.00 90.70 0.00 97.26 0.42 96.77 0.00 89.58 1.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.871045147
93.58 0.42 97.42 0.10 91.18 0.09 90.69 1.31 90.70 0.00 97.47 0.21 96.77 0.00 90.81 1.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.568509474
93.98 0.41 97.42 0.00 91.18 0.00 90.69 0.00 93.02 2.33 97.47 0.00 96.77 0.00 91.34 0.53 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3561151148
94.32 0.33 97.42 0.00 91.18 0.00 90.69 0.00 95.35 2.33 97.47 0.00 96.77 0.00 91.34 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2787462002
94.59 0.28 97.47 0.05 91.18 0.00 90.78 0.09 95.35 0.00 97.68 0.21 96.77 0.00 92.93 1.59 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.2412593179
94.82 0.22 97.57 0.10 91.54 0.36 90.78 0.00 95.35 0.00 97.89 0.21 96.77 0.00 93.82 0.88 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2725133368
95.03 0.22 97.92 0.35 92.44 0.90 91.03 0.25 95.35 0.00 97.89 0.00 96.77 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2145076514
95.24 0.21 97.92 0.00 92.44 0.00 91.03 0.00 95.35 0.00 97.89 0.00 98.26 1.49 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2575077577
95.46 0.21 97.92 0.00 92.44 0.00 92.51 1.48 95.35 0.00 97.89 0.00 98.26 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3777351465
95.66 0.21 97.97 0.05 93.43 0.99 92.51 0.00 95.35 0.00 98.32 0.42 98.26 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1701081478
95.82 0.15 97.97 0.00 93.43 0.00 92.52 0.01 95.35 0.00 98.32 0.00 98.26 0.00 94.88 1.06 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1231792315
95.91 0.09 97.97 0.00 93.43 0.00 92.52 0.00 95.35 0.00 98.53 0.21 98.51 0.25 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3023942147
96.00 0.09 97.97 0.00 93.70 0.27 92.52 0.00 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.35 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1156364686
96.08 0.08 97.97 0.00 93.70 0.00 93.07 0.55 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.3053565295
96.14 0.06 97.97 0.00 94.15 0.45 93.07 0.00 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3073945274
96.19 0.05 97.97 0.00 94.51 0.36 93.07 0.00 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2715882530
96.24 0.05 97.97 0.00 94.87 0.36 93.07 0.00 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.241930116
96.29 0.04 97.97 0.00 94.87 0.00 93.19 0.12 95.35 0.00 98.53 0.00 98.51 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3958671912
96.32 0.04 97.97 0.00 94.87 0.00 93.19 0.00 95.35 0.00 98.53 0.00 98.76 0.25 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2200840119
96.36 0.04 97.97 0.00 94.87 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.25 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2860549862
96.38 0.03 97.97 0.00 95.05 0.18 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2607405755
96.41 0.03 97.97 0.00 95.23 0.18 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1371104598
96.43 0.03 97.97 0.00 95.41 0.18 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.397188162
96.46 0.03 97.97 0.00 95.41 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2234745555
96.48 0.03 97.97 0.00 95.41 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.912132272
96.51 0.03 97.97 0.00 95.41 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2241051149
96.53 0.03 97.97 0.00 95.41 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.738402085
96.55 0.01 97.97 0.00 95.41 0.00 93.29 0.10 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3544611768
96.56 0.01 97.97 0.00 95.41 0.00 93.39 0.10 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.2282272657
96.58 0.01 97.97 0.00 95.50 0.09 93.39 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2689579428
96.59 0.01 97.97 0.00 95.59 0.09 93.39 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2371803859
96.60 0.01 97.97 0.00 95.68 0.09 93.39 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1680291881
96.60 0.01 97.97 0.00 95.68 0.00 93.40 0.01 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.325228007

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3481318379
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2903952386
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1695402606
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3974190815
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3935036039
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3789555184
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1604864986
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2779228491
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3356124739
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.398169264
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1306737761
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4018496835
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4207837896
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.4191135979
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2590558365
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1792419648
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3056674882
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2433102547
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2974459733
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3618733513
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2232163920
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1964620262
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3629848400
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3743908952
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1740917988
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.346292751
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2502613758
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.766597486
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3157239930
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1890180250
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.777642645
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3617356063
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3531626975
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.299383404
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.722144940
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3044818854
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4180729105
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.532942064
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1524659564
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3433298552
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3614723922
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3389949514
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2837014409
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3341631965
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2738425944
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1262331200
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/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.1503373157
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/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3475553635
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3428805183
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.1350183576
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1515929777
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.3509268696
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.4142005786
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/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.845012180
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3196504017
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2441694631
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.615876938
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1749072266
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3394204043
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/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.196340763
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/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3794173293
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/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.171273582
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1674913767
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/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1756456261
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3491780725
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2273553262
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1231666676
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1000341475
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.2672801493
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.659479567
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4081881916
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.1305123267
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/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2982241866
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/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2667152287
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.148429372
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.202338225
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.742500090
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.212593229
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.2611724235
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.521915090
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2492995348
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.492155978
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1297955555
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.2371437152
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3644348730
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.1943698194
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3257883821
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.971321543
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3605329421



Total test records in report: 997
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.965671139 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:43 AM UTC 24 71845676 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.3319926185 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:45 AM UTC 24 66817285 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.215232538 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:46 AM UTC 24 845729353 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2145076514 Oct 03 11:36:44 AM UTC 24 Oct 03 11:36:48 AM UTC 24 34881804 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1132738978 Oct 03 11:36:45 AM UTC 24 Oct 03 11:36:48 AM UTC 24 20195971 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2697992810 Oct 03 11:36:42 AM UTC 24 Oct 03 11:36:49 AM UTC 24 251324793 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.582427222 Oct 03 11:36:44 AM UTC 24 Oct 03 11:36:49 AM UTC 24 151368816 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.849621462 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:51 AM UTC 24 85572771 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.2386972655 Oct 03 11:36:43 AM UTC 24 Oct 03 11:36:52 AM UTC 24 14636669 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1116647582 Oct 03 11:36:43 AM UTC 24 Oct 03 11:36:53 AM UTC 24 515703147 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1093147100 Oct 03 11:36:42 AM UTC 24 Oct 03 11:36:56 AM UTC 24 1584431661 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2573122454 Oct 03 11:36:53 AM UTC 24 Oct 03 11:36:59 AM UTC 24 189482037 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2080445916 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:00 AM UTC 24 37317673 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2401801523 Oct 03 11:36:52 AM UTC 24 Oct 03 11:37:02 AM UTC 24 151117132 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3038849326 Oct 03 11:36:46 AM UTC 24 Oct 03 11:37:02 AM UTC 24 342256078 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3544611768 Oct 03 11:36:41 AM UTC 24 Oct 03 11:37:03 AM UTC 24 687339912 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1966641008 Oct 03 11:36:45 AM UTC 24 Oct 03 11:37:04 AM UTC 24 196358185 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.514641132 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:05 AM UTC 24 215109673 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.325228007 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:06 AM UTC 24 935766279 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.522282431 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:06 AM UTC 24 2788649905 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1090798628 Oct 03 11:36:41 AM UTC 24 Oct 03 11:37:06 AM UTC 24 432922914 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2754185619 Oct 03 11:36:55 AM UTC 24 Oct 03 11:37:07 AM UTC 24 2694605897 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.4241727819 Oct 03 11:37:05 AM UTC 24 Oct 03 11:37:08 AM UTC 24 83220546 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.905290829 Oct 03 11:37:05 AM UTC 24 Oct 03 11:37:08 AM UTC 24 99866896 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1773305729 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:08 AM UTC 24 2487171836 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2670886883 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:09 AM UTC 24 499260439 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2412364040 Oct 03 11:36:55 AM UTC 24 Oct 03 11:37:10 AM UTC 24 289396650 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2745442916 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:11 AM UTC 24 1370965189 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1172683504 Oct 03 11:37:05 AM UTC 24 Oct 03 11:37:11 AM UTC 24 73518657 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.3053565295 Oct 03 11:36:45 AM UTC 24 Oct 03 11:37:12 AM UTC 24 1370338788 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2810196477 Oct 03 11:37:10 AM UTC 24 Oct 03 11:37:12 AM UTC 24 11645149 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.1667177167 Oct 03 11:36:50 AM UTC 24 Oct 03 11:37:13 AM UTC 24 1806300563 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.2412593179 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:13 AM UTC 24 685797650 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2806500351 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:13 AM UTC 24 2133714043 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1231792315 Oct 03 11:37:11 AM UTC 24 Oct 03 11:37:33 AM UTC 24 885845614 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1915357827 Oct 03 11:37:08 AM UTC 24 Oct 03 11:37:13 AM UTC 24 393384493 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1076173009 Oct 03 11:37:01 AM UTC 24 Oct 03 11:37:14 AM UTC 24 989513176 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.51535088 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:14 AM UTC 24 889453752 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.891412754 Oct 03 11:36:57 AM UTC 24 Oct 03 11:37:14 AM UTC 24 1801088031 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1690483425 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:18 AM UTC 24 387010023 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.300422445 Oct 03 11:37:11 AM UTC 24 Oct 03 11:37:19 AM UTC 24 1998412084 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1144465099 Oct 03 11:37:10 AM UTC 24 Oct 03 11:37:19 AM UTC 24 238129569 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1305557981 Oct 03 11:36:48 AM UTC 24 Oct 03 11:37:20 AM UTC 24 709998352 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.3640652396 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:21 AM UTC 24 566605025 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3560468826 Oct 03 11:36:44 AM UTC 24 Oct 03 11:37:21 AM UTC 24 413491186 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.843466448 Oct 03 11:37:18 AM UTC 24 Oct 03 11:37:22 AM UTC 24 26098213 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.1814891369 Oct 03 11:37:19 AM UTC 24 Oct 03 11:37:23 AM UTC 24 48660012 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.424022231 Oct 03 11:37:21 AM UTC 24 Oct 03 11:37:23 AM UTC 24 39734964 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.928879968 Oct 03 11:37:08 AM UTC 24 Oct 03 11:37:23 AM UTC 24 386088069 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1530371147 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:24 AM UTC 24 2571296188 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3776866762 Oct 03 11:37:10 AM UTC 24 Oct 03 11:37:25 AM UTC 24 274873200 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.568509474 Oct 03 11:36:44 AM UTC 24 Oct 03 11:37:26 AM UTC 24 1252134171 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1232397217 Oct 03 11:37:22 AM UTC 24 Oct 03 11:37:27 AM UTC 24 33585434 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3904217962 Oct 03 11:37:16 AM UTC 24 Oct 03 11:37:27 AM UTC 24 224751096 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4019393040 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:27 AM UTC 24 758645868 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2234745555 Oct 03 11:37:25 AM UTC 24 Oct 03 11:37:27 AM UTC 24 17067914 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1240827429 Oct 03 11:37:08 AM UTC 24 Oct 03 11:37:28 AM UTC 24 828863858 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3053777529 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:29 AM UTC 24 9693967219 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2387297365 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:29 AM UTC 24 1108815119 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3924739380 Oct 03 11:37:21 AM UTC 24 Oct 03 11:37:30 AM UTC 24 664902577 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.2282272657 Oct 03 11:36:48 AM UTC 24 Oct 03 11:37:30 AM UTC 24 5072585280 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2542517593 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:31 AM UTC 24 2130267659 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2708839869 Oct 03 11:37:03 AM UTC 24 Oct 03 11:37:31 AM UTC 24 219767131 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1255320846 Oct 03 11:37:23 AM UTC 24 Oct 03 11:37:32 AM UTC 24 215701081 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3219960079 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:32 AM UTC 24 2140078866 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2627410095 Oct 03 11:37:25 AM UTC 24 Oct 03 11:37:32 AM UTC 24 745472842 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.430630469 Oct 03 11:36:50 AM UTC 24 Oct 03 11:37:33 AM UTC 24 7267582122 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.441055132 Oct 03 11:37:08 AM UTC 24 Oct 03 11:37:33 AM UTC 24 429467617 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.708396958 Oct 03 11:37:32 AM UTC 24 Oct 03 11:37:35 AM UTC 24 41205973 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1386728744 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:35 AM UTC 24 1348938583 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4196664470 Oct 03 11:37:33 AM UTC 24 Oct 03 11:37:35 AM UTC 24 12264182 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.1821850163 Oct 03 11:37:32 AM UTC 24 Oct 03 11:37:36 AM UTC 24 44593819 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3306469560 Oct 03 11:37:01 AM UTC 24 Oct 03 11:37:37 AM UTC 24 321490551 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.912132272 Oct 03 11:37:36 AM UTC 24 Oct 03 11:37:38 AM UTC 24 22708687 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1106729119 Oct 03 11:37:34 AM UTC 24 Oct 03 11:37:39 AM UTC 24 126106730 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.779360676 Oct 03 11:37:29 AM UTC 24 Oct 03 11:37:39 AM UTC 24 626840875 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.393491486 Oct 03 11:37:23 AM UTC 24 Oct 03 11:37:39 AM UTC 24 1526824873 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1191880301 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:39 AM UTC 24 5541652610 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.976806137 Oct 03 11:37:30 AM UTC 24 Oct 03 11:37:44 AM UTC 24 370320637 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.2768154017 Oct 03 11:37:33 AM UTC 24 Oct 03 11:37:46 AM UTC 24 278687869 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.599018493 Oct 03 11:37:37 AM UTC 24 Oct 03 11:37:46 AM UTC 24 1055764288 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.448556094 Oct 03 11:37:39 AM UTC 24 Oct 03 11:37:47 AM UTC 24 321773284 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1487899758 Oct 03 11:37:36 AM UTC 24 Oct 03 11:37:47 AM UTC 24 342244577 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.4091102229 Oct 03 11:37:25 AM UTC 24 Oct 03 11:37:48 AM UTC 24 550912043 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.676001392 Oct 03 11:37:21 AM UTC 24 Oct 03 11:37:48 AM UTC 24 4692940580 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.624487840 Oct 03 11:37:27 AM UTC 24 Oct 03 11:37:49 AM UTC 24 2028854316 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.292075708 Oct 03 11:37:30 AM UTC 24 Oct 03 11:37:49 AM UTC 24 1151062286 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3886823613 Oct 03 11:37:26 AM UTC 24 Oct 03 11:37:49 AM UTC 24 1400122735 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.714165451 Oct 03 11:37:29 AM UTC 24 Oct 03 11:37:49 AM UTC 24 2650225239 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.298917615 Oct 03 11:37:34 AM UTC 24 Oct 03 11:37:50 AM UTC 24 1694411217 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.2489214178 Oct 03 11:37:34 AM UTC 24 Oct 03 11:37:51 AM UTC 24 294805721 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1202077027 Oct 03 11:37:40 AM UTC 24 Oct 03 11:37:52 AM UTC 24 1013209013 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3441370086 Oct 03 11:37:50 AM UTC 24 Oct 03 11:37:52 AM UTC 24 41057736 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4234656145 Oct 03 11:37:50 AM UTC 24 Oct 03 11:37:52 AM UTC 24 34434570 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1315270219 Oct 03 11:37:29 AM UTC 24 Oct 03 11:37:52 AM UTC 24 1142304479 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.143794087 Oct 03 11:37:50 AM UTC 24 Oct 03 11:37:52 AM UTC 24 16071694 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.2916906703 Oct 03 11:37:45 AM UTC 24 Oct 03 11:37:54 AM UTC 24 219565643 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.4002683675 Oct 03 11:37:24 AM UTC 24 Oct 03 11:37:54 AM UTC 24 725977278 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.710266426 Oct 03 11:37:52 AM UTC 24 Oct 03 11:37:55 AM UTC 24 37927209 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.4055279308 Oct 03 11:37:40 AM UTC 24 Oct 03 11:37:56 AM UTC 24 3832001401 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.4169449504 Oct 03 11:37:51 AM UTC 24 Oct 03 11:37:57 AM UTC 24 409426250 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3719585663 Oct 03 11:37:16 AM UTC 24 Oct 03 11:37:57 AM UTC 24 273848673 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2725133368 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:57 AM UTC 24 4300745642 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.3893129390 Oct 03 11:37:38 AM UTC 24 Oct 03 11:37:57 AM UTC 24 407773887 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2798495247 Oct 03 11:37:44 AM UTC 24 Oct 03 11:37:58 AM UTC 24 249752973 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.114295100 Oct 03 11:37:47 AM UTC 24 Oct 03 11:37:58 AM UTC 24 554860177 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2553706621 Oct 03 11:37:50 AM UTC 24 Oct 03 11:37:58 AM UTC 24 139712275 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.3261699572 Oct 03 11:37:56 AM UTC 24 Oct 03 11:38:02 AM UTC 24 1234843286 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.2787210600 Oct 03 11:37:51 AM UTC 24 Oct 03 11:38:02 AM UTC 24 241392384 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.4227158310 Oct 03 11:38:00 AM UTC 24 Oct 03 11:38:02 AM UTC 24 18182120 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2345828088 Oct 03 11:37:53 AM UTC 24 Oct 03 11:38:03 AM UTC 24 370116453 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3561151148 Oct 03 11:37:52 AM UTC 24 Oct 03 11:38:04 AM UTC 24 687475143 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2982241866 Oct 03 11:38:32 AM UTC 24 Oct 03 11:38:34 AM UTC 24 43589449 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2389236237 Oct 03 11:38:03 AM UTC 24 Oct 03 11:38:05 AM UTC 24 15803313 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3023942147 Oct 03 11:37:52 AM UTC 24 Oct 03 11:38:07 AM UTC 24 205858343 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1534908725 Oct 03 11:37:11 AM UTC 24 Oct 03 11:38:07 AM UTC 24 4308190260 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.3509268696 Oct 03 11:38:03 AM UTC 24 Oct 03 11:38:08 AM UTC 24 77482279 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.614291823 Oct 03 11:37:32 AM UTC 24 Oct 03 11:38:09 AM UTC 24 834237039 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2241051149 Oct 03 11:38:08 AM UTC 24 Oct 03 11:38:10 AM UTC 24 22739684 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1331565303 Oct 03 11:38:04 AM UTC 24 Oct 03 11:38:10 AM UTC 24 267099967 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.2575726480 Oct 03 11:37:58 AM UTC 24 Oct 03 11:38:11 AM UTC 24 770288255 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.872334889 Oct 03 11:37:59 AM UTC 24 Oct 03 11:38:13 AM UTC 24 295554948 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1861355111 Oct 03 11:37:33 AM UTC 24 Oct 03 11:38:14 AM UTC 24 738265623 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.4177715319 Oct 03 11:37:40 AM UTC 24 Oct 03 11:38:14 AM UTC 24 1119507624 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1220191142 Oct 03 11:38:09 AM UTC 24 Oct 03 11:38:15 AM UTC 24 646021035 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2974739916 Oct 03 11:37:58 AM UTC 24 Oct 03 11:38:15 AM UTC 24 670473653 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.897951589 Oct 03 11:38:04 AM UTC 24 Oct 03 11:38:15 AM UTC 24 44781100 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1906523728 Oct 03 11:37:50 AM UTC 24 Oct 03 11:38:16 AM UTC 24 481736214 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.155615831 Oct 03 11:37:54 AM UTC 24 Oct 03 11:38:16 AM UTC 24 600320558 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2067230858 Oct 03 11:37:57 AM UTC 24 Oct 03 11:38:17 AM UTC 24 4216259030 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2171552995 Oct 03 11:37:48 AM UTC 24 Oct 03 11:38:17 AM UTC 24 645424647 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.4165468081 Oct 03 11:38:08 AM UTC 24 Oct 03 11:38:17 AM UTC 24 241748284 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3416433826 Oct 03 11:38:11 AM UTC 24 Oct 03 11:38:19 AM UTC 24 569153904 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3271846891 Oct 03 11:37:40 AM UTC 24 Oct 03 11:38:19 AM UTC 24 7101831550 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.191412667 Oct 03 11:38:14 AM UTC 24 Oct 03 11:38:20 AM UTC 24 227131219 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.2411120859 Oct 03 11:38:06 AM UTC 24 Oct 03 11:38:20 AM UTC 24 678256992 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.3247794570 Oct 03 11:38:17 AM UTC 24 Oct 03 11:38:20 AM UTC 24 127278776 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1411744763 Oct 03 11:38:18 AM UTC 24 Oct 03 11:38:20 AM UTC 24 14613028 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.1503373157 Oct 03 11:38:11 AM UTC 24 Oct 03 11:38:21 AM UTC 24 408082658 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1515929777 Oct 03 11:38:07 AM UTC 24 Oct 03 11:38:21 AM UTC 24 2022595641 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2449930827 Oct 03 11:37:37 AM UTC 24 Oct 03 11:38:22 AM UTC 24 6586669191 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1749072266 Oct 03 11:38:18 AM UTC 24 Oct 03 11:38:22 AM UTC 24 57807996 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1676016203 Oct 03 11:38:21 AM UTC 24 Oct 03 11:38:23 AM UTC 24 14059540 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2850929096 Oct 03 11:38:20 AM UTC 24 Oct 03 11:38:24 AM UTC 24 36376622 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3475553635 Oct 03 11:38:16 AM UTC 24 Oct 03 11:38:35 AM UTC 24 448502641 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2995365578 Oct 03 11:37:55 AM UTC 24 Oct 03 11:38:24 AM UTC 24 1811867981 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.2352426300 Oct 03 11:37:25 AM UTC 24 Oct 03 11:38:27 AM UTC 24 2560188690 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.1350183576 Oct 03 11:38:16 AM UTC 24 Oct 03 11:38:27 AM UTC 24 229839675 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2763105989 Oct 03 11:38:22 AM UTC 24 Oct 03 11:38:28 AM UTC 24 266031662 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.902512440 Oct 03 11:38:25 AM UTC 24 Oct 03 11:38:29 AM UTC 24 134156663 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2762718808 Oct 03 11:37:58 AM UTC 24 Oct 03 11:38:29 AM UTC 24 4703462711 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3958671912 Oct 03 11:38:20 AM UTC 24 Oct 03 11:38:30 AM UTC 24 81481202 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3428805183 Oct 03 11:38:16 AM UTC 24 Oct 03 11:38:30 AM UTC 24 720134983 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.4142005786 Oct 03 11:38:03 AM UTC 24 Oct 03 11:38:31 AM UTC 24 2783472899 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.615876938 Oct 03 11:38:21 AM UTC 24 Oct 03 11:38:32 AM UTC 24 1190116403 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3236262341 Oct 03 11:37:55 AM UTC 24 Oct 03 11:38:33 AM UTC 24 11541840177 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.408644106 Oct 03 11:38:31 AM UTC 24 Oct 03 11:38:33 AM UTC 24 27149045 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.4273983697 Oct 03 11:38:21 AM UTC 24 Oct 03 11:38:33 AM UTC 24 1165602721 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4081881916 Oct 03 11:38:31 AM UTC 24 Oct 03 11:38:35 AM UTC 24 25359499 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.2767708569 Oct 03 11:38:24 AM UTC 24 Oct 03 11:38:35 AM UTC 24 1208349615 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1788969958 Oct 03 11:37:54 AM UTC 24 Oct 03 11:38:36 AM UTC 24 1585689649 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.589664331 Oct 03 11:38:21 AM UTC 24 Oct 03 11:38:38 AM UTC 24 545450283 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.1594031306 Oct 03 11:36:43 AM UTC 24 Oct 03 11:38:38 AM UTC 24 6115829795 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.738402085 Oct 03 11:38:36 AM UTC 24 Oct 03 11:38:38 AM UTC 24 35684134 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3394204043 Oct 03 11:38:19 AM UTC 24 Oct 03 11:38:39 AM UTC 24 360055198 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.2546997125 Oct 03 11:38:25 AM UTC 24 Oct 03 11:38:40 AM UTC 24 595686023 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1582768724 Oct 03 11:38:24 AM UTC 24 Oct 03 11:38:40 AM UTC 24 1433340936 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3491780725 Oct 03 11:38:35 AM UTC 24 Oct 03 11:38:40 AM UTC 24 86071100 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.529274862 Oct 03 11:37:27 AM UTC 24 Oct 03 11:38:42 AM UTC 24 2366306788 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.845012180 Oct 03 11:38:27 AM UTC 24 Oct 03 11:38:42 AM UTC 24 1609762795 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2342863007 Oct 03 11:38:15 AM UTC 24 Oct 03 11:38:42 AM UTC 24 4548591361 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2441694631 Oct 03 11:38:28 AM UTC 24 Oct 03 11:38:42 AM UTC 24 294634906 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3381287862 Oct 03 11:39:06 AM UTC 24 Oct 03 11:39:23 AM UTC 24 473575392 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3196504017 Oct 03 11:38:29 AM UTC 24 Oct 03 11:38:44 AM UTC 24 1176907776 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1674913767 Oct 03 11:38:36 AM UTC 24 Oct 03 11:38:44 AM UTC 24 999380899 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.761081910 Oct 03 11:38:44 AM UTC 24 Oct 03 11:38:46 AM UTC 24 81598808 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.659479567 Oct 03 11:38:36 AM UTC 24 Oct 03 11:38:47 AM UTC 24 811972881 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.1305123267 Oct 03 11:38:35 AM UTC 24 Oct 03 11:38:47 AM UTC 24 104300866 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3794173293 Oct 03 11:38:41 AM UTC 24 Oct 03 11:38:47 AM UTC 24 241024694 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3763827671 Oct 03 11:38:12 AM UTC 24 Oct 03 11:38:47 AM UTC 24 4040565468 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2273553262 Oct 03 11:38:36 AM UTC 24 Oct 03 11:38:47 AM UTC 24 685627940 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.237682238 Oct 03 11:38:15 AM UTC 24 Oct 03 11:38:48 AM UTC 24 1459019422 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3605329421 Oct 03 11:38:45 AM UTC 24 Oct 03 11:38:49 AM UTC 24 13301525 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.965555094 Oct 03 11:38:49 AM UTC 24 Oct 03 11:38:51 AM UTC 24 17284291 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1756456261 Oct 03 11:38:38 AM UTC 24 Oct 03 11:38:52 AM UTC 24 654199532 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.546330898 Oct 03 11:39:22 AM UTC 24 Oct 03 11:39:24 AM UTC 24 194266551 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.148429372 Oct 03 11:38:49 AM UTC 24 Oct 03 11:38:53 AM UTC 24 65764821 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.2371437152 Oct 03 11:38:45 AM UTC 24 Oct 03 11:38:53 AM UTC 24 85279166 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2090540595 Oct 03 11:38:38 AM UTC 24 Oct 03 11:38:54 AM UTC 24 663740881 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.212593229 Oct 03 11:38:48 AM UTC 24 Oct 03 11:38:54 AM UTC 24 60956602 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.4131057012 Oct 03 11:37:30 AM UTC 24 Oct 03 11:38:54 AM UTC 24 9162499436 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2581727418 Oct 03 11:38:35 AM UTC 24 Oct 03 11:38:56 AM UTC 24 475203222 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.1943698194 Oct 03 11:38:47 AM UTC 24 Oct 03 11:38:56 AM UTC 24 121558312 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.171273582 Oct 03 11:38:41 AM UTC 24 Oct 03 11:38:58 AM UTC 24 6297185688 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.1277577277 Oct 03 11:38:53 AM UTC 24 Oct 03 11:38:59 AM UTC 24 1281104192 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.2672801493 Oct 03 11:38:43 AM UTC 24 Oct 03 11:39:00 AM UTC 24 778638800 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.554001340 Oct 03 11:38:25 AM UTC 24 Oct 03 11:39:00 AM UTC 24 1015120483 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.2350006692 Oct 03 11:38:54 AM UTC 24 Oct 03 11:39:00 AM UTC 24 283625621 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.196340763 Oct 03 11:38:40 AM UTC 24 Oct 03 11:39:01 AM UTC 24 12221833147 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3777351465 Oct 03 11:38:33 AM UTC 24 Oct 03 11:39:01 AM UTC 24 1910837514 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.2566007745 Oct 03 11:38:59 AM UTC 24 Oct 03 11:39:01 AM UTC 24 51758328 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.4280171287 Oct 03 11:38:10 AM UTC 24 Oct 03 11:39:02 AM UTC 24 6505787748 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.997871557 Oct 03 11:39:01 AM UTC 24 Oct 03 11:39:03 AM UTC 24 106106316 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3928000426 Oct 03 11:38:49 AM UTC 24 Oct 03 11:39:03 AM UTC 24 545733826 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2121031134 Oct 03 11:39:00 AM UTC 24 Oct 03 11:39:04 AM UTC 24 74800917 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1297955555 Oct 03 11:38:49 AM UTC 24 Oct 03 11:39:04 AM UTC 24 3415367455 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1231666676 Oct 03 11:38:41 AM UTC 24 Oct 03 11:39:04 AM UTC 24 2282293597 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.492155978 Oct 03 11:38:56 AM UTC 24 Oct 03 11:39:05 AM UTC 24 4393114610 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.521915090 Oct 03 11:38:55 AM UTC 24 Oct 03 11:39:08 AM UTC 24 936071148 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3721776529 Oct 03 11:38:54 AM UTC 24 Oct 03 11:39:08 AM UTC 24 716039182 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.2825860924 Oct 03 11:38:16 AM UTC 24 Oct 03 11:39:09 AM UTC 24 2653428305 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.2943298478 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:09 AM UTC 24 528549870 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.657388299 Oct 03 11:39:03 AM UTC 24 Oct 03 11:39:10 AM UTC 24 368735412 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3651739068 Oct 03 11:38:37 AM UTC 24 Oct 03 11:39:11 AM UTC 24 1333510407 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.799874579 Oct 03 11:38:22 AM UTC 24 Oct 03 11:39:12 AM UTC 24 1027702043 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.2611724235 Oct 03 11:38:49 AM UTC 24 Oct 03 11:39:13 AM UTC 24 308775631 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2454959065 Oct 03 11:38:40 AM UTC 24 Oct 03 11:39:14 AM UTC 24 1854917369 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.724776372 Oct 03 11:39:05 AM UTC 24 Oct 03 11:39:14 AM UTC 24 3559963495 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3428292024 Oct 03 11:39:12 AM UTC 24 Oct 03 11:39:14 AM UTC 24 39045104 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2492995348 Oct 03 11:38:57 AM UTC 24 Oct 03 11:39:14 AM UTC 24 1446109640 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.742500090 Oct 03 11:38:52 AM UTC 24 Oct 03 11:39:15 AM UTC 24 1168569289 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.67767321 Oct 03 11:39:13 AM UTC 24 Oct 03 11:39:15 AM UTC 24 31342412 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1744850096 Oct 03 11:39:06 AM UTC 24 Oct 03 11:39:25 AM UTC 24 568239625 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.3935231998 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:16 AM UTC 24 664934417 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.2267889991 Oct 03 11:39:12 AM UTC 24 Oct 03 11:39:16 AM UTC 24 69577566 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3990156982 Oct 03 11:38:25 AM UTC 24 Oct 03 11:39:18 AM UTC 24 3278672781 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1305087242 Oct 03 11:39:15 AM UTC 24 Oct 03 11:39:19 AM UTC 24 103403695 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.3293444525 Oct 03 11:39:05 AM UTC 24 Oct 03 11:39:19 AM UTC 24 727438656 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2294057746 Oct 03 11:39:08 AM UTC 24 Oct 03 11:39:19 AM UTC 24 1139118746 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2045230736 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:19 AM UTC 24 1309420574 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1000341475 Oct 03 11:38:44 AM UTC 24 Oct 03 11:39:20 AM UTC 24 12292521047 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1556242483 Oct 03 11:39:23 AM UTC 24 Oct 03 11:39:26 AM UTC 24 117616607 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2667152287 Oct 03 11:38:54 AM UTC 24 Oct 03 11:39:21 AM UTC 24 3737021623 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.929088441 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:21 AM UTC 24 607315343 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3644348730 Oct 03 11:38:45 AM UTC 24 Oct 03 11:39:22 AM UTC 24 233949067 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1444153304 Oct 03 11:39:08 AM UTC 24 Oct 03 11:39:22 AM UTC 24 806630761 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.4195574401 Oct 03 11:39:16 AM UTC 24 Oct 03 11:39:23 AM UTC 24 153190568 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3320481329 Oct 03 11:39:15 AM UTC 24 Oct 03 11:39:25 AM UTC 24 198224976 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4076292258 Oct 03 11:39:23 AM UTC 24 Oct 03 11:39:25 AM UTC 24 37576047 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3932699971 Oct 03 11:39:15 AM UTC 24 Oct 03 11:39:28 AM UTC 24 398708968 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2584153001 Oct 03 11:39:25 AM UTC 24 Oct 03 11:39:29 AM UTC 24 465704224 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.741450150 Oct 03 11:39:20 AM UTC 24 Oct 03 11:39:30 AM UTC 24 634546055 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.2062814935 Oct 03 11:39:15 AM UTC 24 Oct 03 11:39:31 AM UTC 24 730894322 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.643147402 Oct 03 11:40:14 AM UTC 24 Oct 03 11:40:23 AM UTC 24 262735064 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.526795358 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:32 AM UTC 24 1346668984 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.1021044749 Oct 03 11:39:18 AM UTC 24 Oct 03 11:39:32 AM UTC 24 472889868 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.238783812 Oct 03 11:39:20 AM UTC 24 Oct 03 11:39:33 AM UTC 24 1442239529 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2354567816 Oct 03 11:39:30 AM UTC 24 Oct 03 11:39:34 AM UTC 24 95866027 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.2826168782 Oct 03 11:39:20 AM UTC 24 Oct 03 11:39:35 AM UTC 24 255569048 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1984154501 Oct 03 11:39:24 AM UTC 24 Oct 03 11:39:35 AM UTC 24 159547469 ps