Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.60 97.97 95.68 93.40 95.35 98.53 99.00 96.29


Total tests in report: 997
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.37 64.37 80.49 80.49 45.18 45.18 55.32 55.32 48.84 48.84 78.32 78.32 91.54 91.54 50.88 50.88 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2697992810
74.62 10.25 87.33 6.84 73.00 27.81 73.05 17.73 53.49 4.65 84.21 5.89 93.28 1.74 57.95 7.07 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2670886883
80.28 5.66 94.32 6.99 75.16 2.16 80.79 7.74 62.79 9.30 88.63 4.42 93.28 0.00 66.96 9.01 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2745442916
82.99 2.71 95.39 1.06 79.75 4.59 82.75 1.96 67.44 4.65 91.79 3.16 94.53 1.24 69.26 2.30 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.582427222
84.93 1.94 95.84 0.46 80.92 1.17 82.87 0.11 74.42 6.98 93.47 1.68 94.53 0.00 72.44 3.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.51535088
86.53 1.61 95.84 0.00 80.92 0.00 82.87 0.00 83.72 9.30 93.47 0.00 94.53 0.00 74.38 1.94 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3161304287
87.94 1.41 95.89 0.05 81.10 0.18 85.97 3.11 86.05 2.33 94.32 0.84 94.53 0.00 77.74 3.36 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1090798628
89.13 1.19 96.05 0.15 82.99 1.89 86.01 0.04 86.05 0.00 94.53 0.21 95.77 1.24 82.51 4.77 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3341928176
90.29 1.16 96.65 0.61 86.14 3.15 86.23 0.21 86.05 0.00 95.16 0.63 96.27 0.50 85.51 3.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1773305729
91.16 0.87 97.16 0.51 87.76 1.62 86.63 0.40 88.37 2.33 96.21 1.05 96.27 0.00 85.69 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.965671139
92.01 0.85 97.26 0.10 88.57 0.81 87.26 0.63 90.70 2.33 96.84 0.63 96.52 0.25 86.93 1.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3560468826
92.71 0.70 97.26 0.00 89.65 1.08 89.38 2.13 90.70 0.00 96.84 0.00 96.77 0.25 88.34 1.41 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3939093329
93.16 0.45 97.31 0.05 91.09 1.44 89.38 0.00 90.70 0.00 97.26 0.42 96.77 0.00 89.58 1.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.871045147
93.58 0.42 97.42 0.10 91.18 0.09 90.69 1.31 90.70 0.00 97.47 0.21 96.77 0.00 90.81 1.24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.568509474
93.98 0.41 97.42 0.00 91.18 0.00 90.69 0.00 93.02 2.33 97.47 0.00 96.77 0.00 91.34 0.53 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3561151148
94.32 0.33 97.42 0.00 91.18 0.00 90.69 0.00 95.35 2.33 97.47 0.00 96.77 0.00 91.34 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2787462002
94.59 0.28 97.47 0.05 91.18 0.00 90.78 0.09 95.35 0.00 97.68 0.21 96.77 0.00 92.93 1.59 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.2412593179
94.82 0.22 97.57 0.10 91.54 0.36 90.78 0.00 95.35 0.00 97.89 0.21 96.77 0.00 93.82 0.88 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2725133368
95.03 0.22 97.92 0.35 92.44 0.90 91.03 0.25 95.35 0.00 97.89 0.00 96.77 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2145076514
95.24 0.21 97.92 0.00 92.44 0.00 91.03 0.00 95.35 0.00 97.89 0.00 98.26 1.49 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2575077577
95.46 0.21 97.92 0.00 92.44 0.00 92.51 1.48 95.35 0.00 97.89 0.00 98.26 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3777351465
95.66 0.21 97.97 0.05 93.43 0.99 92.51 0.00 95.35 0.00 98.32 0.42 98.26 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1701081478
95.82 0.15 97.97 0.00 93.43 0.00 92.52 0.01 95.35 0.00 98.32 0.00 98.26 0.00 94.88 1.06 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1231792315
95.91 0.09 97.97 0.00 93.43 0.00 92.52 0.00 95.35 0.00 98.53 0.21 98.51 0.25 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3023942147
96.00 0.09 97.97 0.00 93.70 0.27 92.52 0.00 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.35 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1156364686
96.08 0.08 97.97 0.00 93.70 0.00 93.07 0.55 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.3053565295
96.14 0.06 97.97 0.00 94.15 0.45 93.07 0.00 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3073945274
96.19 0.05 97.97 0.00 94.51 0.36 93.07 0.00 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2715882530
96.24 0.05 97.97 0.00 94.87 0.36 93.07 0.00 95.35 0.00 98.53 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.241930116
96.29 0.04 97.97 0.00 94.87 0.00 93.19 0.12 95.35 0.00 98.53 0.00 98.51 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3958671912
96.32 0.04 97.97 0.00 94.87 0.00 93.19 0.00 95.35 0.00 98.53 0.00 98.76 0.25 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2200840119
96.36 0.04 97.97 0.00 94.87 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.25 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2860549862
96.38 0.03 97.97 0.00 95.05 0.18 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2607405755
96.41 0.03 97.97 0.00 95.23 0.18 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1371104598
96.43 0.03 97.97 0.00 95.41 0.18 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.397188162
96.46 0.03 97.97 0.00 95.41 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2234745555
96.48 0.03 97.97 0.00 95.41 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.912132272
96.51 0.03 97.97 0.00 95.41 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2241051149
96.53 0.03 97.97 0.00 95.41 0.00 93.19 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.738402085
96.55 0.01 97.97 0.00 95.41 0.00 93.29 0.10 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3544611768
96.56 0.01 97.97 0.00 95.41 0.00 93.39 0.10 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.2282272657
96.58 0.01 97.97 0.00 95.50 0.09 93.39 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2689579428
96.59 0.01 97.97 0.00 95.59 0.09 93.39 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2371803859
96.60 0.01 97.97 0.00 95.68 0.09 93.39 0.00 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1680291881
96.60 0.01 97.97 0.00 95.68 0.00 93.40 0.01 95.35 0.00 98.53 0.00 99.00 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.325228007

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3481318379
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2903952386
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1695402606
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3974190815
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3935036039
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3789555184
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1604864986
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2779228491
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3356124739
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.398169264
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1306737761
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4018496835
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4207837896
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.4191135979
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2590558365
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1792419648
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3056674882
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2433102547
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2974459733
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3618733513
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2232163920
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1964620262
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3629848400
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3743908952
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1740917988
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.346292751
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2502613758
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.766597486
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3157239930
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1890180250
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.777642645
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3617356063
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3531626975
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.299383404
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.722144940
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3044818854
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4180729105
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.532942064
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1524659564
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3433298552
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3614723922
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3389949514
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2837014409
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3341631965
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2738425944
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1262331200
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1640076403
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1973425896
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.567601248
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1143946009
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2358628816
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2721033123
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1396478116
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1479057448
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4072608866
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1367174956
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4027081362
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4076473247
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.542437458
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3521238114
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1016091030
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1465824741
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1074690987
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1597361689
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2859846658
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2724378195
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3867016335
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1384305742
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3761488923
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2180360645
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1088557517
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1333897886
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3639333890
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1497454533
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3341722317
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4042365122
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4159272443
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2466208200
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3249847916
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3017363567
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3526438515
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1042594694
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2388231970
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2942609200
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3158193571
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2274013073
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2370440695
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3525093160
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1804772027
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2356573371
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3931508416
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4078143639
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.874968214
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3238337224
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2145571732
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3601499027
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1729556027
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1479603125
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2733576816
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1782532361
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1392150045
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2690062312
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3329281528
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1696109483
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.259594900
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1993681670
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2255006283
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3030183110
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2089605856
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.372450510
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1539001259
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2883471534
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2924649282
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1448428770
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2386495482
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3665573423
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4280357555
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1888992509
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.702134538
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3954834641
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2418312088
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1033377575
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3026669529
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3243988078
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.280258539
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1287475052
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3176609375
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.249694276
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.298994389
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2853853378
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2086954741
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3757578935
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.872000622
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2760082696
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1131936533
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3058364701
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3464562863
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3524236286
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1244917266
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1835188911
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3690739127
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.915424819
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1130035594
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.572642391
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.383743495
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.843729539
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3121647481
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1435810885
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1717114616
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.850565519
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3335834700
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1628766617
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.515005331
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2992307646
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1297395397
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2448283194
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.813990864
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3982024746
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1522640757
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2033484044
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4243561186
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1236544039
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.127461900
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1231629999
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1807647971
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1678138463
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4010016016
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1813944831
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2972950597
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2957296307
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4264585552
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2265283140
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.2386972655
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.1594031306
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3053777529
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1386728744
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1116647582
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3219960079
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.215232538
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1093147100
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2806500351
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.3319926185
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.849621462
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2571255756
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.4241727819
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2080445916
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2401801523
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.430630469
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2573122454
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.1667177167
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2754185619
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.514641132
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1305557981
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3038849326
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1690483425
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2708839869
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2412364040
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1076173009
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.891412754
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.522282431
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1966641008
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3306469560
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4179325758
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1132738978
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3428292024
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2045230736
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1744850096
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.819172273
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.724776372
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.657388299
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.2348458742
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.3293444525
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.2943298478
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3381287862
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1444153304
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2294057746
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.929088441
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2121031134
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.526795358
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.3935231998
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.2137727984
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.997871557
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.546330898
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.2062814935
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.741450150
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2704846404
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.1021044749
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.4195574401
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.235127933
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.422905868
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1305087242
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.2826168782
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.238783812
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2163100282
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3932699971
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.2267889991
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.18721471
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3320481329
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2468179242
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.67767321
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.4001926028
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.3585543
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.4276451683
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.3255518709
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2354567816
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.1765523462
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.327779391
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.2556369725
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2584153001
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.934247844
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.2533346445
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.2531916997
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.2904310041
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1556242483
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.2010075652
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1984154501
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2875431169
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4076292258
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.4218765612
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1249774800
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.3814136500
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.4111029146
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.2802668552
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.1818734128
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.3679392276
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.2475037971
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.286960333
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.1397235835
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3203625676
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3653966021
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2696479075
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.1775772310
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.2775622529
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.1241010211
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.3897326023
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.628561063
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.499771862
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.793985348
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.1976859566
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.3169357300
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.291485509
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.3275111044
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.802593955
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.4219280851
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.2354105136
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.1360032444
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.3101533191
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.2335066004
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.2968410079
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.3681481730
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.4188617978
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.2527124462
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1362210359
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2529550706
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.72378888
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3416035094
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.144952023
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.2153077574
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.2835536574
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.458313536
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.1865129954
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.133839036
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.3258430202
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.1277406170
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.643147402
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.1429874462
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.1261992645
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2433366183
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.705373156
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3481729358
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3925209158
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.3598793712
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.724625503
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.3990856279
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.872948398
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.967900803
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3959394980
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.1965583132
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.2595054270
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.1006981538
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.652688139
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.618384887
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3764662983
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.3608998665
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.3923746391
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3766648724
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.962292688
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3875794601
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2090617079
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.260146420
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.4135897355
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.3353228622
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.1388769096
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.1508740128
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.1056776236
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.273133103
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.3889212743
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.2175669691
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.1743471047
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.4039727518
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.110591220
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.713050030
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.1640224764
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.2543846816
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2523022291
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.3225927219
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.85816883
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.785904541
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3223665191
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.2001213756
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3765385282
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.3038156151
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.2220991457
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.2208739464
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.113271688
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.3424293752
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2808024946
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.2626360096
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.1906488864
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1927066435
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.2815964105
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.1974748427
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.482465545
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2752156778
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.1823527618
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.4272991506
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.3689024672
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.3497900248
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.411010508
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.468788060
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.877569546
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.4234419638
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.1675171708
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2271731999
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.2536447213
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.374889073
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.3057637567
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.4231116194
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.3248616838
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.2393744744
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.987845538
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2588436375
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.843466448
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2810196477
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1240827429
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.3640652396
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1530371147
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4019393040
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1191880301
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.300422445
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1534908725
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1915357827
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3776866762
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3719585663
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2542517593
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3904217962
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2387297365
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1144465099
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1172683504
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.441055132
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.928879968
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1366586194
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.905290829
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.1038797010
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3215258975
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.2133552421
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.2342514124
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1478238421
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.679591777
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.3429814175
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.6947204
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3260266376
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.164353901
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.1586628288
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.551487721
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2687279985
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1331583205
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.2231020293
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.2763040155
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2733844009
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2677985048
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.2812592021
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.225433034
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.3467679251
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.4096684304
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.2599106137
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.3715012167
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3455015385
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3278688110
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.4152689349
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3023050100
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.580042988
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.4173495804
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.3141364463
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2308815667
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.827045977
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.3991308827
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.920635679
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.2387868903
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.1262583695
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.507374512
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.2530194145
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2809450465
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1054668608
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.4029260876
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.4174863600
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3459214976
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1407905967
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.2403970731
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.262682909
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2344647109
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.692646584
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.2204491352
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.3040297059
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.3113212951
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.115453845
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.2519260957
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1677239364
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.2804294053
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.102053873
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.600174736
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.4268595519
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.3706424116
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.2524577867
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3723881737
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.389095532
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3591087266
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.3852025440
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.2376945750
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.2021932241
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2346241061
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1640270928
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.2477552608
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.2180268238
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.1679450035
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.374747508
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.3307559371
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.3018150908
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.1102335676
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.1103524904
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.2260744242
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3121302752
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.2424732064
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.250901739
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2131482880
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.1225210221
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1196802141
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.2236239816
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.1901904202
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.1006010872
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.704490636
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.3083030997
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.3213380876
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.465265133
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.965745470
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.57520279
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1465789335
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.447963578
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.431165202
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.3167496316
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.1728591470
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.1460887476
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1069152494
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.522088124
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2006389756
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3313244851
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.262619910
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.3048167472
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.4040433103
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2045926655
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2943719686
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.3748765528
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.3659180859
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3134316118
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.674896009
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.1139796691
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.4263742465
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.719590309
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.1324461175
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.1527127601
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.1583974314
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.3200649675
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.1355590607
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1142010948
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.1408796796
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.3675099696
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3904533434
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2301521487
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.2668251206
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.2416167174
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.3890166326
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1250396103
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.1617046949
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.8352110
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.1082359579
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2819372979
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3634521583
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.708396958
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.393491486
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.624487840
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.529274862
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.779360676
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3886823613
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1315270219
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2627410095
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.2352426300
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.4091102229
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1232397217
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.4002683675
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.614291823
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.714165451
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.292075708
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.976806137
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1255320846
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.1814891369
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.676001392
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3924739380
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.4131057012
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.224889592
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.424022231
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.172778864
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.2069320027
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.618601031
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.2900038361
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.2590627005
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.755354759
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3298933217
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2617592049
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.1336077664
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1376852673
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.3831302789
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3793578373
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.1442561161
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.1103601328
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.560125796
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1193511315
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.82880002
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.762781856
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.3785035160
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.3110632849
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.3411680091
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.340720114
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.3177223805
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.266337522
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.4216317894
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.3385498590
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.2902322719
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.4132451860
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.3508360029
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.3232446562
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.3097835699
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.901757419
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3517295699
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3877015795
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.2365323504
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.4131309086
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.4093642409
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.4251188815
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2013872535
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.995202878
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2351043263
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.553093847
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.3784384425
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1196968888
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2024102379
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.3710542267
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.293974231
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.99355757
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3638636354
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.2188476978
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3927534869
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3276581810
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3461258346
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.2993051531
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.2373290178
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3968240380
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3245280113
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.4079771667
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.1704848882
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.3371230439
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.2188896918
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.1328173347
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.4219142505
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.626036315
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.3220053824
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4146803947
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.935102751
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1261550893
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3682751062
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.2430717233
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.787581787
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.1458669137
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.580365030
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2010728732
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.3841459975
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.3682783953
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.33545164
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.4294713967
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1806149217
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.3088602839
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3964878874
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.1310844335
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.1476613363
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.129797616
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.546371447
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.957182330
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1974839445
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.527364005
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.1277473581
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.614162482
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.3361387476
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2160402082
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.1023342432
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.190010352
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.969908887
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.842850094
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2365932436
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3028544284
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.744900653
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.2958951952
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.2475306737
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.4272730171
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.3747590747
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.197855651
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.411265914
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3418655942
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.2292994134
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.852108928
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2501892937
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.1896166310
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2421357612
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.1976072730
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1686779734
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.3717592190
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.4114732949
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2281945224
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.1043728874
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.738584249
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3914299256
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3094309140
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.463306144
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.4079653110
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.2631479656
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.3533008816
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.464086400
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.3492116056
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.667407665
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2285328639
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.846450417
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.168322480
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.1726425150
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.4157846624
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.940954456
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3441370086
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.2489214178
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.4055279308
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3271846891
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1202077027
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.448556094
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.4177715319
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.599018493
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2449930827
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.3893129390
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1106729119
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1487899758
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2171552995
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2798495247
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.114295100
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.2916906703
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.298917615
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.1821850163
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1861355111
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.2768154017
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2704692025
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4196664470
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1241212970
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.3980119322
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.105977180
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2731172159
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.3700073023
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.3772493710
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.1379633805
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.760172689
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1804045479
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.1535707626
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2227269225
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.997918397
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3396440641
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.696106790
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.2819478778
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2982783129
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.4075708930
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.3107034048
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2407935694
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.739861016
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.482477517
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1751414154
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.1778262035
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.820025315
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.269261128
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1792707250
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3553005838
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.4190509336
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.334100634
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1877783702
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.2059179693
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3885910655
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3942945564
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.449125233
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.797702200
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2662473201
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2207933653
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.205772381
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.1569447513
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1648074043
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.1867780376
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.3965111554
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.3014631393
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.246091372
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1999393801
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1907455494
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.3852262877
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.497738367
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.2597460320
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.18905384
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3446635804
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1166916950
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3684455194
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.3601343656
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.2880781765
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.4175278777
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2657791054
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1467022353
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2384740240
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.4087142910
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.4269100846
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.1186117129
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.2580497761
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1889808536
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.1784085010
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.1498463216
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.3606336194
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1947851630
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.4061391794
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.146315833
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.2681485503
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.1256146919
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1409296601
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.426433252
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.150575686
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.2877842612
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.715560375
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.4084244154
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2566009925
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.1836761680
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.729135657
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.199250927
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.86581615
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.1703307456
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.1820388546
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.607900485
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.611723446
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2698151280
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.2813936264
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.2321231971
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.246135897
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3561202808
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1797468699
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.4225331301
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.1108209686
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.1473461601
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.3247046163
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.723888873
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.4043091198
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3157544791
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1993915051
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3885872428
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.2860621765
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1928529568
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.250970096
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.2228199332
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.880409498
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.1877947243
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.1103780787
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.1475697417
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2810313625
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.3311726375
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.2149133500
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3041397059
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.2827663996
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.3385076809
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1444542454
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.750442877
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3792448561
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1381132301
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.546871327
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1273120866
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1237595468
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.3041547615
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1309430281
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.2834836537
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2901417246
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.200769196
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.1928700287
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.280949740
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.91948418
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.4227158310
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.710266426
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.2787210600
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.3261699572
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3236262341
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2067230858
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2995365578
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2762718808
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2345828088
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1788969958
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.155615831
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.4169449504
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.2575726480
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.872334889
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2974739916
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.143794087
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1906523728
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2553706621
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.1936223187
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4234656145
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.3247794570
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.2411120859
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.191412667
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3763827671
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2342863007
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3416433826
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.237682238
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1220191142
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.4280171287
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.1503373157
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1331565303
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.4165468081
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3475553635
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3428805183
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.1350183576
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1515929777
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.3509268696
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.4142005786
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.897951589
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.2825860924
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2389236237
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.408644106
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1676016203
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.4273983697
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.902512440
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3990156982
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.2546997125
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1582768724
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.554001340
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2763105989
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.799874579
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.2767708569
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2850929096
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.589664331
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.845012180
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3196504017
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2441694631
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.615876938
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1749072266
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3394204043
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.549811950
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1411744763
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.761081910
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2581727418
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.196340763
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2454959065
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3794173293
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2090540595
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.171273582
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1674913767
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3651739068
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1756456261
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3491780725
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2273553262
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1231666676
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1000341475
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.2672801493
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.659479567
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4081881916
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.1305123267
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.2253158920
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1262891339
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2982241866
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.2566007745
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.965555094
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3928000426
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3721776529
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.2026640558
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.2350006692
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.1277577277
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2667152287
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.148429372
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.202338225
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.742500090
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.212593229
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.2611724235
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.521915090
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2492995348
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.492155978
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1297955555
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.2371437152
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3644348730
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.1943698194
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3257883821
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.971321543
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3605329421



Total test records in report: 997
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.965671139 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:43 AM UTC 24 71845676 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.3319926185 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:45 AM UTC 24 66817285 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.215232538 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:46 AM UTC 24 845729353 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2145076514 Oct 03 11:36:44 AM UTC 24 Oct 03 11:36:48 AM UTC 24 34881804 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1132738978 Oct 03 11:36:45 AM UTC 24 Oct 03 11:36:48 AM UTC 24 20195971 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2697992810 Oct 03 11:36:42 AM UTC 24 Oct 03 11:36:49 AM UTC 24 251324793 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.582427222 Oct 03 11:36:44 AM UTC 24 Oct 03 11:36:49 AM UTC 24 151368816 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.849621462 Oct 03 11:36:41 AM UTC 24 Oct 03 11:36:51 AM UTC 24 85572771 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.2386972655 Oct 03 11:36:43 AM UTC 24 Oct 03 11:36:52 AM UTC 24 14636669 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1116647582 Oct 03 11:36:43 AM UTC 24 Oct 03 11:36:53 AM UTC 24 515703147 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1093147100 Oct 03 11:36:42 AM UTC 24 Oct 03 11:36:56 AM UTC 24 1584431661 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2573122454 Oct 03 11:36:53 AM UTC 24 Oct 03 11:36:59 AM UTC 24 189482037 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2080445916 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:00 AM UTC 24 37317673 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2401801523 Oct 03 11:36:52 AM UTC 24 Oct 03 11:37:02 AM UTC 24 151117132 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3038849326 Oct 03 11:36:46 AM UTC 24 Oct 03 11:37:02 AM UTC 24 342256078 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3544611768 Oct 03 11:36:41 AM UTC 24 Oct 03 11:37:03 AM UTC 24 687339912 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1966641008 Oct 03 11:36:45 AM UTC 24 Oct 03 11:37:04 AM UTC 24 196358185 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.514641132 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:05 AM UTC 24 215109673 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.325228007 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:06 AM UTC 24 935766279 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.522282431 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:06 AM UTC 24 2788649905 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1090798628 Oct 03 11:36:41 AM UTC 24 Oct 03 11:37:06 AM UTC 24 432922914 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2754185619 Oct 03 11:36:55 AM UTC 24 Oct 03 11:37:07 AM UTC 24 2694605897 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.4241727819 Oct 03 11:37:05 AM UTC 24 Oct 03 11:37:08 AM UTC 24 83220546 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.905290829 Oct 03 11:37:05 AM UTC 24 Oct 03 11:37:08 AM UTC 24 99866896 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.1773305729 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:08 AM UTC 24 2487171836 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2670886883 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:09 AM UTC 24 499260439 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2412364040 Oct 03 11:36:55 AM UTC 24 Oct 03 11:37:10 AM UTC 24 289396650 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2745442916 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:11 AM UTC 24 1370965189 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1172683504 Oct 03 11:37:05 AM UTC 24 Oct 03 11:37:11 AM UTC 24 73518657 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.3053565295 Oct 03 11:36:45 AM UTC 24 Oct 03 11:37:12 AM UTC 24 1370338788 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2810196477 Oct 03 11:37:10 AM UTC 24 Oct 03 11:37:12 AM UTC 24 11645149 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.1667177167 Oct 03 11:36:50 AM UTC 24 Oct 03 11:37:13 AM UTC 24 1806300563 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.2412593179 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:13 AM UTC 24 685797650 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.2806500351 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:13 AM UTC 24 2133714043 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1231792315 Oct 03 11:37:11 AM UTC 24 Oct 03 11:37:33 AM UTC 24 885845614 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1915357827 Oct 03 11:37:08 AM UTC 24 Oct 03 11:37:13 AM UTC 24 393384493 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1076173009 Oct 03 11:37:01 AM UTC 24 Oct 03 11:37:14 AM UTC 24 989513176 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.51535088 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:14 AM UTC 24 889453752 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.891412754 Oct 03 11:36:57 AM UTC 24 Oct 03 11:37:14 AM UTC 24 1801088031 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1690483425 Oct 03 11:36:47 AM UTC 24 Oct 03 11:37:18 AM UTC 24 387010023 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.300422445 Oct 03 11:37:11 AM UTC 24 Oct 03 11:37:19 AM UTC 24 1998412084 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1144465099 Oct 03 11:37:10 AM UTC 24 Oct 03 11:37:19 AM UTC 24 238129569 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1305557981 Oct 03 11:36:48 AM UTC 24 Oct 03 11:37:20 AM UTC 24 709998352 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.3640652396 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:21 AM UTC 24 566605025 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3560468826 Oct 03 11:36:44 AM UTC 24 Oct 03 11:37:21 AM UTC 24 413491186 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.843466448 Oct 03 11:37:18 AM UTC 24 Oct 03 11:37:22 AM UTC 24 26098213 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.1814891369 Oct 03 11:37:19 AM UTC 24 Oct 03 11:37:23 AM UTC 24 48660012 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.424022231 Oct 03 11:37:21 AM UTC 24 Oct 03 11:37:23 AM UTC 24 39734964 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.928879968 Oct 03 11:37:08 AM UTC 24 Oct 03 11:37:23 AM UTC 24 386088069 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1530371147 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:24 AM UTC 24 2571296188 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3776866762 Oct 03 11:37:10 AM UTC 24 Oct 03 11:37:25 AM UTC 24 274873200 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.568509474 Oct 03 11:36:44 AM UTC 24 Oct 03 11:37:26 AM UTC 24 1252134171 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1232397217 Oct 03 11:37:22 AM UTC 24 Oct 03 11:37:27 AM UTC 24 33585434 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3904217962 Oct 03 11:37:16 AM UTC 24 Oct 03 11:37:27 AM UTC 24 224751096 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4019393040 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:27 AM UTC 24 758645868 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2234745555 Oct 03 11:37:25 AM UTC 24 Oct 03 11:37:27 AM UTC 24 17067914 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1240827429 Oct 03 11:37:08 AM UTC 24 Oct 03 11:37:28 AM UTC 24 828863858 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3053777529 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:29 AM UTC 24 9693967219 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2387297365 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:29 AM UTC 24 1108815119 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3924739380 Oct 03 11:37:21 AM UTC 24 Oct 03 11:37:30 AM UTC 24 664902577 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.2282272657 Oct 03 11:36:48 AM UTC 24 Oct 03 11:37:30 AM UTC 24 5072585280 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2542517593 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:31 AM UTC 24 2130267659 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2708839869 Oct 03 11:37:03 AM UTC 24 Oct 03 11:37:31 AM UTC 24 219767131 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1255320846 Oct 03 11:37:23 AM UTC 24 Oct 03 11:37:32 AM UTC 24 215701081 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3219960079 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:32 AM UTC 24 2140078866 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2627410095 Oct 03 11:37:25 AM UTC 24 Oct 03 11:37:32 AM UTC 24 745472842 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.430630469 Oct 03 11:36:50 AM UTC 24 Oct 03 11:37:33 AM UTC 24 7267582122 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.441055132 Oct 03 11:37:08 AM UTC 24 Oct 03 11:37:33 AM UTC 24 429467617 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.708396958 Oct 03 11:37:32 AM UTC 24 Oct 03 11:37:35 AM UTC 24 41205973 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1386728744 Oct 03 11:36:43 AM UTC 24 Oct 03 11:37:35 AM UTC 24 1348938583 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4196664470 Oct 03 11:37:33 AM UTC 24 Oct 03 11:37:35 AM UTC 24 12264182 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.1821850163 Oct 03 11:37:32 AM UTC 24 Oct 03 11:37:36 AM UTC 24 44593819 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3306469560 Oct 03 11:37:01 AM UTC 24 Oct 03 11:37:37 AM UTC 24 321490551 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.912132272 Oct 03 11:37:36 AM UTC 24 Oct 03 11:37:38 AM UTC 24 22708687 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1106729119 Oct 03 11:37:34 AM UTC 24 Oct 03 11:37:39 AM UTC 24 126106730 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.779360676 Oct 03 11:37:29 AM UTC 24 Oct 03 11:37:39 AM UTC 24 626840875 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.393491486 Oct 03 11:37:23 AM UTC 24 Oct 03 11:37:39 AM UTC 24 1526824873 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1191880301 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:39 AM UTC 24 5541652610 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.976806137 Oct 03 11:37:30 AM UTC 24 Oct 03 11:37:44 AM UTC 24 370320637 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.2768154017 Oct 03 11:37:33 AM UTC 24 Oct 03 11:37:46 AM UTC 24 278687869 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.599018493 Oct 03 11:37:37 AM UTC 24 Oct 03 11:37:46 AM UTC 24 1055764288 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.448556094 Oct 03 11:37:39 AM UTC 24 Oct 03 11:37:47 AM UTC 24 321773284 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1487899758 Oct 03 11:37:36 AM UTC 24 Oct 03 11:37:47 AM UTC 24 342244577 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.4091102229 Oct 03 11:37:25 AM UTC 24 Oct 03 11:37:48 AM UTC 24 550912043 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.676001392 Oct 03 11:37:21 AM UTC 24 Oct 03 11:37:48 AM UTC 24 4692940580 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.624487840 Oct 03 11:37:27 AM UTC 24 Oct 03 11:37:49 AM UTC 24 2028854316 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.292075708 Oct 03 11:37:30 AM UTC 24 Oct 03 11:37:49 AM UTC 24 1151062286 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3886823613 Oct 03 11:37:26 AM UTC 24 Oct 03 11:37:49 AM UTC 24 1400122735 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.714165451 Oct 03 11:37:29 AM UTC 24 Oct 03 11:37:49 AM UTC 24 2650225239 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.298917615 Oct 03 11:37:34 AM UTC 24 Oct 03 11:37:50 AM UTC 24 1694411217 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.2489214178 Oct 03 11:37:34 AM UTC 24 Oct 03 11:37:51 AM UTC 24 294805721 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1202077027 Oct 03 11:37:40 AM UTC 24 Oct 03 11:37:52 AM UTC 24 1013209013 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3441370086 Oct 03 11:37:50 AM UTC 24 Oct 03 11:37:52 AM UTC 24 41057736 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4234656145 Oct 03 11:37:50 AM UTC 24 Oct 03 11:37:52 AM UTC 24 34434570 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1315270219 Oct 03 11:37:29 AM UTC 24 Oct 03 11:37:52 AM UTC 24 1142304479 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.143794087 Oct 03 11:37:50 AM UTC 24 Oct 03 11:37:52 AM UTC 24 16071694 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.2916906703 Oct 03 11:37:45 AM UTC 24 Oct 03 11:37:54 AM UTC 24 219565643 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.4002683675 Oct 03 11:37:24 AM UTC 24 Oct 03 11:37:54 AM UTC 24 725977278 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.710266426 Oct 03 11:37:52 AM UTC 24 Oct 03 11:37:55 AM UTC 24 37927209 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.4055279308 Oct 03 11:37:40 AM UTC 24 Oct 03 11:37:56 AM UTC 24 3832001401 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.4169449504 Oct 03 11:37:51 AM UTC 24 Oct 03 11:37:57 AM UTC 24 409426250 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3719585663 Oct 03 11:37:16 AM UTC 24 Oct 03 11:37:57 AM UTC 24 273848673 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2725133368 Oct 03 11:37:14 AM UTC 24 Oct 03 11:37:57 AM UTC 24 4300745642 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.3893129390 Oct 03 11:37:38 AM UTC 24 Oct 03 11:37:57 AM UTC 24 407773887 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2798495247 Oct 03 11:37:44 AM UTC 24 Oct 03 11:37:58 AM UTC 24 249752973 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.114295100 Oct 03 11:37:47 AM UTC 24 Oct 03 11:37:58 AM UTC 24 554860177 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2553706621 Oct 03 11:37:50 AM UTC 24 Oct 03 11:37:58 AM UTC 24 139712275 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.3261699572 Oct 03 11:37:56 AM UTC 24 Oct 03 11:38:02 AM UTC 24 1234843286 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.2787210600 Oct 03 11:37:51 AM UTC 24 Oct 03 11:38:02 AM UTC 24 241392384 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.4227158310 Oct 03 11:38:00 AM UTC 24 Oct 03 11:38:02 AM UTC 24 18182120 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2345828088 Oct 03 11:37:53 AM UTC 24 Oct 03 11:38:03 AM UTC 24 370116453 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.3561151148 Oct 03 11:37:52 AM UTC 24 Oct 03 11:38:04 AM UTC 24 687475143 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2982241866 Oct 03 11:38:32 AM UTC 24 Oct 03 11:38:34 AM UTC 24 43589449 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2389236237 Oct 03 11:38:03 AM UTC 24 Oct 03 11:38:05 AM UTC 24 15803313 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3023942147 Oct 03 11:37:52 AM UTC 24 Oct 03 11:38:07 AM UTC 24 205858343 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1534908725 Oct 03 11:37:11 AM UTC 24 Oct 03 11:38:07 AM UTC 24 4308190260 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.3509268696 Oct 03 11:38:03 AM UTC 24 Oct 03 11:38:08 AM UTC 24 77482279 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.614291823 Oct 03 11:37:32 AM UTC 24 Oct 03 11:38:09 AM UTC 24 834237039 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2241051149 Oct 03 11:38:08 AM UTC 24 Oct 03 11:38:10 AM UTC 24 22739684 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1331565303 Oct 03 11:38:04 AM UTC 24 Oct 03 11:38:10 AM UTC 24 267099967 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.2575726480 Oct 03 11:37:58 AM UTC 24 Oct 03 11:38:11 AM UTC 24 770288255 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.872334889 Oct 03 11:37:59 AM UTC 24 Oct 03 11:38:13 AM UTC 24 295554948 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1861355111 Oct 03 11:37:33 AM UTC 24 Oct 03 11:38:14 AM UTC 24 738265623 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.4177715319 Oct 03 11:37:40 AM UTC 24 Oct 03 11:38:14 AM UTC 24 1119507624 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1220191142 Oct 03 11:38:09 AM UTC 24 Oct 03 11:38:15 AM UTC 24 646021035 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2974739916 Oct 03 11:37:58 AM UTC 24 Oct 03 11:38:15 AM UTC 24 670473653 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.897951589 Oct 03 11:38:04 AM UTC 24 Oct 03 11:38:15 AM UTC 24 44781100 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1906523728 Oct 03 11:37:50 AM UTC 24 Oct 03 11:38:16 AM UTC 24 481736214 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.155615831 Oct 03 11:37:54 AM UTC 24 Oct 03 11:38:16 AM UTC 24 600320558 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2067230858 Oct 03 11:37:57 AM UTC 24 Oct 03 11:38:17 AM UTC 24 4216259030 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2171552995 Oct 03 11:37:48 AM UTC 24 Oct 03 11:38:17 AM UTC 24 645424647 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.4165468081 Oct 03 11:38:08 AM UTC 24 Oct 03 11:38:17 AM UTC 24 241748284 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3416433826 Oct 03 11:38:11 AM UTC 24 Oct 03 11:38:19 AM UTC 24 569153904 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3271846891 Oct 03 11:37:40 AM UTC 24 Oct 03 11:38:19 AM UTC 24 7101831550 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.191412667 Oct 03 11:38:14 AM UTC 24 Oct 03 11:38:20 AM UTC 24 227131219 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.2411120859 Oct 03 11:38:06 AM UTC 24 Oct 03 11:38:20 AM UTC 24 678256992 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.3247794570 Oct 03 11:38:17 AM UTC 24 Oct 03 11:38:20 AM UTC 24 127278776 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1411744763 Oct 03 11:38:18 AM UTC 24 Oct 03 11:38:20 AM UTC 24 14613028 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.1503373157 Oct 03 11:38:11 AM UTC 24 Oct 03 11:38:21 AM UTC 24 408082658 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1515929777 Oct 03 11:38:07 AM UTC 24 Oct 03 11:38:21 AM UTC 24 2022595641 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2449930827 Oct 03 11:37:37 AM UTC 24 Oct 03 11:38:22 AM UTC 24 6586669191 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1749072266 Oct 03 11:38:18 AM UTC 24 Oct 03 11:38:22 AM UTC 24 57807996 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1676016203 Oct 03 11:38:21 AM UTC 24 Oct 03 11:38:23 AM UTC 24 14059540 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2850929096 Oct 03 11:38:20 AM UTC 24 Oct 03 11:38:24 AM UTC 24 36376622 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3475553635 Oct 03 11:38:16 AM UTC 24 Oct 03 11:38:35 AM UTC 24 448502641 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2995365578 Oct 03 11:37:55 AM UTC 24 Oct 03 11:38:24 AM UTC 24 1811867981 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.2352426300 Oct 03 11:37:25 AM UTC 24 Oct 03 11:38:27 AM UTC 24 2560188690 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.1350183576 Oct 03 11:38:16 AM UTC 24 Oct 03 11:38:27 AM UTC 24 229839675 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2763105989 Oct 03 11:38:22 AM UTC 24 Oct 03 11:38:28 AM UTC 24 266031662 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.902512440 Oct 03 11:38:25 AM UTC 24 Oct 03 11:38:29 AM UTC 24 134156663 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2762718808 Oct 03 11:37:58 AM UTC 24 Oct 03 11:38:29 AM UTC 24 4703462711 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3958671912 Oct 03 11:38:20 AM UTC 24 Oct 03 11:38:30 AM UTC 24 81481202 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3428805183 Oct 03 11:38:16 AM UTC 24 Oct 03 11:38:30 AM UTC 24 720134983 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.4142005786 Oct 03 11:38:03 AM UTC 24 Oct 03 11:38:31 AM UTC 24 2783472899 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.615876938 Oct 03 11:38:21 AM UTC 24 Oct 03 11:38:32 AM UTC 24 1190116403 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3236262341 Oct 03 11:37:55 AM UTC 24 Oct 03 11:38:33 AM UTC 24 11541840177 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.408644106 Oct 03 11:38:31 AM UTC 24 Oct 03 11:38:33 AM UTC 24 27149045 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.4273983697 Oct 03 11:38:21 AM UTC 24 Oct 03 11:38:33 AM UTC 24 1165602721 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4081881916 Oct 03 11:38:31 AM UTC 24 Oct 03 11:38:35 AM UTC 24 25359499 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.2767708569 Oct 03 11:38:24 AM UTC 24 Oct 03 11:38:35 AM UTC 24 1208349615 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1788969958 Oct 03 11:37:54 AM UTC 24 Oct 03 11:38:36 AM UTC 24 1585689649 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.589664331 Oct 03 11:38:21 AM UTC 24 Oct 03 11:38:38 AM UTC 24 545450283 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.1594031306 Oct 03 11:36:43 AM UTC 24 Oct 03 11:38:38 AM UTC 24 6115829795 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.738402085 Oct 03 11:38:36 AM UTC 24 Oct 03 11:38:38 AM UTC 24 35684134 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3394204043 Oct 03 11:38:19 AM UTC 24 Oct 03 11:38:39 AM UTC 24 360055198 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.2546997125 Oct 03 11:38:25 AM UTC 24 Oct 03 11:38:40 AM UTC 24 595686023 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1582768724 Oct 03 11:38:24 AM UTC 24 Oct 03 11:38:40 AM UTC 24 1433340936 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3491780725 Oct 03 11:38:35 AM UTC 24 Oct 03 11:38:40 AM UTC 24 86071100 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.529274862 Oct 03 11:37:27 AM UTC 24 Oct 03 11:38:42 AM UTC 24 2366306788 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.845012180 Oct 03 11:38:27 AM UTC 24 Oct 03 11:38:42 AM UTC 24 1609762795 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2342863007 Oct 03 11:38:15 AM UTC 24 Oct 03 11:38:42 AM UTC 24 4548591361 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2441694631 Oct 03 11:38:28 AM UTC 24 Oct 03 11:38:42 AM UTC 24 294634906 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3381287862 Oct 03 11:39:06 AM UTC 24 Oct 03 11:39:23 AM UTC 24 473575392 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3196504017 Oct 03 11:38:29 AM UTC 24 Oct 03 11:38:44 AM UTC 24 1176907776 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1674913767 Oct 03 11:38:36 AM UTC 24 Oct 03 11:38:44 AM UTC 24 999380899 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.761081910 Oct 03 11:38:44 AM UTC 24 Oct 03 11:38:46 AM UTC 24 81598808 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.659479567 Oct 03 11:38:36 AM UTC 24 Oct 03 11:38:47 AM UTC 24 811972881 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.1305123267 Oct 03 11:38:35 AM UTC 24 Oct 03 11:38:47 AM UTC 24 104300866 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3794173293 Oct 03 11:38:41 AM UTC 24 Oct 03 11:38:47 AM UTC 24 241024694 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3763827671 Oct 03 11:38:12 AM UTC 24 Oct 03 11:38:47 AM UTC 24 4040565468 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2273553262 Oct 03 11:38:36 AM UTC 24 Oct 03 11:38:47 AM UTC 24 685627940 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.237682238 Oct 03 11:38:15 AM UTC 24 Oct 03 11:38:48 AM UTC 24 1459019422 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3605329421 Oct 03 11:38:45 AM UTC 24 Oct 03 11:38:49 AM UTC 24 13301525 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.965555094 Oct 03 11:38:49 AM UTC 24 Oct 03 11:38:51 AM UTC 24 17284291 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1756456261 Oct 03 11:38:38 AM UTC 24 Oct 03 11:38:52 AM UTC 24 654199532 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.546330898 Oct 03 11:39:22 AM UTC 24 Oct 03 11:39:24 AM UTC 24 194266551 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.148429372 Oct 03 11:38:49 AM UTC 24 Oct 03 11:38:53 AM UTC 24 65764821 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.2371437152 Oct 03 11:38:45 AM UTC 24 Oct 03 11:38:53 AM UTC 24 85279166 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2090540595 Oct 03 11:38:38 AM UTC 24 Oct 03 11:38:54 AM UTC 24 663740881 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.212593229 Oct 03 11:38:48 AM UTC 24 Oct 03 11:38:54 AM UTC 24 60956602 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.4131057012 Oct 03 11:37:30 AM UTC 24 Oct 03 11:38:54 AM UTC 24 9162499436 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2581727418 Oct 03 11:38:35 AM UTC 24 Oct 03 11:38:56 AM UTC 24 475203222 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.1943698194 Oct 03 11:38:47 AM UTC 24 Oct 03 11:38:56 AM UTC 24 121558312 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.171273582 Oct 03 11:38:41 AM UTC 24 Oct 03 11:38:58 AM UTC 24 6297185688 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.1277577277 Oct 03 11:38:53 AM UTC 24 Oct 03 11:38:59 AM UTC 24 1281104192 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.2672801493 Oct 03 11:38:43 AM UTC 24 Oct 03 11:39:00 AM UTC 24 778638800 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.554001340 Oct 03 11:38:25 AM UTC 24 Oct 03 11:39:00 AM UTC 24 1015120483 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.2350006692 Oct 03 11:38:54 AM UTC 24 Oct 03 11:39:00 AM UTC 24 283625621 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.196340763 Oct 03 11:38:40 AM UTC 24 Oct 03 11:39:01 AM UTC 24 12221833147 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3777351465 Oct 03 11:38:33 AM UTC 24 Oct 03 11:39:01 AM UTC 24 1910837514 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.2566007745 Oct 03 11:38:59 AM UTC 24 Oct 03 11:39:01 AM UTC 24 51758328 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.4280171287 Oct 03 11:38:10 AM UTC 24 Oct 03 11:39:02 AM UTC 24 6505787748 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.997871557 Oct 03 11:39:01 AM UTC 24 Oct 03 11:39:03 AM UTC 24 106106316 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3928000426 Oct 03 11:38:49 AM UTC 24 Oct 03 11:39:03 AM UTC 24 545733826 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2121031134 Oct 03 11:39:00 AM UTC 24 Oct 03 11:39:04 AM UTC 24 74800917 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1297955555 Oct 03 11:38:49 AM UTC 24 Oct 03 11:39:04 AM UTC 24 3415367455 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1231666676 Oct 03 11:38:41 AM UTC 24 Oct 03 11:39:04 AM UTC 24 2282293597 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.492155978 Oct 03 11:38:56 AM UTC 24 Oct 03 11:39:05 AM UTC 24 4393114610 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.521915090 Oct 03 11:38:55 AM UTC 24 Oct 03 11:39:08 AM UTC 24 936071148 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3721776529 Oct 03 11:38:54 AM UTC 24 Oct 03 11:39:08 AM UTC 24 716039182 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.2825860924 Oct 03 11:38:16 AM UTC 24 Oct 03 11:39:09 AM UTC 24 2653428305 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.2943298478 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:09 AM UTC 24 528549870 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.657388299 Oct 03 11:39:03 AM UTC 24 Oct 03 11:39:10 AM UTC 24 368735412 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3651739068 Oct 03 11:38:37 AM UTC 24 Oct 03 11:39:11 AM UTC 24 1333510407 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.799874579 Oct 03 11:38:22 AM UTC 24 Oct 03 11:39:12 AM UTC 24 1027702043 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.2611724235 Oct 03 11:38:49 AM UTC 24 Oct 03 11:39:13 AM UTC 24 308775631 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2454959065 Oct 03 11:38:40 AM UTC 24 Oct 03 11:39:14 AM UTC 24 1854917369 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.724776372 Oct 03 11:39:05 AM UTC 24 Oct 03 11:39:14 AM UTC 24 3559963495 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3428292024 Oct 03 11:39:12 AM UTC 24 Oct 03 11:39:14 AM UTC 24 39045104 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2492995348 Oct 03 11:38:57 AM UTC 24 Oct 03 11:39:14 AM UTC 24 1446109640 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.742500090 Oct 03 11:38:52 AM UTC 24 Oct 03 11:39:15 AM UTC 24 1168569289 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.67767321 Oct 03 11:39:13 AM UTC 24 Oct 03 11:39:15 AM UTC 24 31342412 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1744850096 Oct 03 11:39:06 AM UTC 24 Oct 03 11:39:25 AM UTC 24 568239625 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.3935231998 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:16 AM UTC 24 664934417 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.2267889991 Oct 03 11:39:12 AM UTC 24 Oct 03 11:39:16 AM UTC 24 69577566 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3990156982 Oct 03 11:38:25 AM UTC 24 Oct 03 11:39:18 AM UTC 24 3278672781 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1305087242 Oct 03 11:39:15 AM UTC 24 Oct 03 11:39:19 AM UTC 24 103403695 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.3293444525 Oct 03 11:39:05 AM UTC 24 Oct 03 11:39:19 AM UTC 24 727438656 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2294057746 Oct 03 11:39:08 AM UTC 24 Oct 03 11:39:19 AM UTC 24 1139118746 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2045230736 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:19 AM UTC 24 1309420574 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1000341475 Oct 03 11:38:44 AM UTC 24 Oct 03 11:39:20 AM UTC 24 12292521047 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1556242483 Oct 03 11:39:23 AM UTC 24 Oct 03 11:39:26 AM UTC 24 117616607 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2667152287 Oct 03 11:38:54 AM UTC 24 Oct 03 11:39:21 AM UTC 24 3737021623 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.929088441 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:21 AM UTC 24 607315343 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3644348730 Oct 03 11:38:45 AM UTC 24 Oct 03 11:39:22 AM UTC 24 233949067 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1444153304 Oct 03 11:39:08 AM UTC 24 Oct 03 11:39:22 AM UTC 24 806630761 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.4195574401 Oct 03 11:39:16 AM UTC 24 Oct 03 11:39:23 AM UTC 24 153190568 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3320481329 Oct 03 11:39:15 AM UTC 24 Oct 03 11:39:25 AM UTC 24 198224976 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4076292258 Oct 03 11:39:23 AM UTC 24 Oct 03 11:39:25 AM UTC 24 37576047 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3932699971 Oct 03 11:39:15 AM UTC 24 Oct 03 11:39:28 AM UTC 24 398708968 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2584153001 Oct 03 11:39:25 AM UTC 24 Oct 03 11:39:29 AM UTC 24 465704224 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.741450150 Oct 03 11:39:20 AM UTC 24 Oct 03 11:39:30 AM UTC 24 634546055 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.2062814935 Oct 03 11:39:15 AM UTC 24 Oct 03 11:39:31 AM UTC 24 730894322 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.643147402 Oct 03 11:40:14 AM UTC 24 Oct 03 11:40:23 AM UTC 24 262735064 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.526795358 Oct 03 11:39:02 AM UTC 24 Oct 03 11:39:32 AM UTC 24 1346668984 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.1021044749 Oct 03 11:39:18 AM UTC 24 Oct 03 11:39:32 AM UTC 24 472889868 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.238783812 Oct 03 11:39:20 AM UTC 24 Oct 03 11:39:33 AM UTC 24 1442239529 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2354567816 Oct 03 11:39:30 AM UTC 24 Oct 03 11:39:34 AM UTC 24 95866027 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.2826168782 Oct 03 11:39:20 AM UTC 24 Oct 03 11:39:35 AM UTC 24 255569048 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1984154501 Oct 03 11:39:24 AM UTC 24 Oct 03 11:39:35 AM UTC 24 159547469 ps
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