Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61948386

1

T1

821

T2

1896

T3

939

auto[1]

1076809

1

T4

99

T5

294

T12

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61936710

1

T1

821

T2

1896

T3

939

auto[1]

1088485

1

T4

198

T5

98

T12

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5251324	1			T1	75		T2	298		T3	90
auto[IdleSt]	16128524	1			T1	226		T2	326		T3	849
auto[ClkMuxSt]	28449	1			T2	3		T4	3		T5	4
auto[CntIncrSt]	28237	1			T2	3		T4	3		T5	4
auto[CntProgSt]	1332614	1			T2	6		T4	1478		T5	33
auto[TransCheckSt]	22482	1			T2	3		T7	14		T12	9
auto[TokenHashSt]	19743278	1			T2	173		T7	716		T12	98
auto[FlashRmaSt]	28444	1			T2	15		T7	28		T12	9
auto[TokenCheck0St]	10178	1			T2	3		T7	14		T12	9
auto[TokenCheck1St]	7480	1			T2	3		T7	14		T12	9
auto[TransProgSt]	306074	1			T2	6		T7	28		T12	3588
auto[PostTransSt]	8889129	1			T1	520		T2	1057		T4	210
auto[ScrapSt]	209119	1			T15	4		T17	12		T18	3437
auto[EscalateSt]	4449904	1			T4	368		T5	2466		T12	748
auto[InvalidSt]	6588681	1			T12	271		T16	2401		T20	7628

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1278	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6588681	1			T12	271		T16	2401		T20	7628
EscalateSt	4449904	1			T4	368		T5	2466		T12	748
ScrapSt	209119	1			T15	4		T17	12		T18	3437
PostTransSt	8889129	1			T1	520		T2	1057		T4	210
TransProgSt	306074	1			T2	6		T7	28		T12	3588
TokenCheck1St	7480	1			T2	3		T7	14		T12	9
TokenCheck0St	10178	1			T2	3		T7	14		T12	9
FlashRmaSt	28444	1			T2	15		T7	28		T12	9
TokenHashSt	19743278	1			T2	173		T7	716		T12	98
TransCheckSt	22482	1			T2	3		T7	14		T12	9
CntProgSt	1332614	1			T2	6		T4	1478		T5	33
CntIncrSt	28237	1			T2	3		T4	3		T5	4
ClkMuxSt	28449	1			T2	3		T4	3		T5	4
IdleSt	16128524	1			T1	226		T2	326		T3	849
ResetSt	5251324	1			T1	75		T2	298		T3	90
arcs[ResetSt=>IdleSt]	41359	1			T1	1		T2	3		T3	1
arcs[IdleSt=>ScrapSt]	258	1			T15	1		T17	1		T18	1
arcs[IdleSt=>ClkMuxSt]	28273	1			T2	3		T4	3		T5	4
arcs[ClkMuxSt=>CntIncrSt]	28237	1			T2	3		T4	3		T5	4
arcs[CntIncrSt=>PostTransSt]	1258	1			T13	13		T45	9		T52	6
arcs[CntIncrSt=>CntProgSt]	26905	1			T2	3		T4	3		T5	4
arcs[CntProgSt=>PostTransSt]	3431	1			T4	3		T5	4		T13	9
arcs[CntProgSt=>TransCheckSt]	22482	1			T2	3		T7	14		T12	9
arcs[TransCheckSt=>PostTransSt]	3047	1			T13	8		T42	50		T45	9
arcs[TransCheckSt=>TokenHashSt]	19323	1			T2	3		T7	14		T12	9
arcs[TokenHashSt=>PostTransSt]	8336	1			T13	30		T16	6		T42	14
arcs[TokenHashSt=>FlashRmaSt]	10219	1			T2	3		T7	14		T12	9
arcs[FlashRmaSt=>TokenCheck0St]	10178	1			T2	3		T7	14		T12	9
arcs[TokenCheck0St=>PostTransSt]	2651	1			T13	15		T16	10		T42	21
arcs[TokenCheck0St=>TokenCheck1St]	7480	1			T2	3		T7	14		T12	9
arcs[TokenCheck1St=>PostTransSt]	578	1			T16	2		T42	14		T45	1
arcs[TransProgSt=>PostTransSt]	6104	1			T2	3		T7	14		T12	9
arcs[IdleSt=>EscalateSt]	148	1			T15	3		T68	5		T38	12
arcs[ClkMuxSt=>EscalateSt]	36	1			T15	4		T38	2		T49	2
arcs[CntIncrSt=>EscalateSt]	74	1			T15	2		T68	3		T38	5
arcs[CntProgSt=>EscalateSt]	992	1			T15	16		T68	38		T38	34
arcs[TransCheckSt=>EscalateSt]	112	1			T15	6		T38	3		T72	1
arcs[TokenHashSt=>EscalateSt]	768	1			T15	21		T68	9		T48	1
arcs[FlashRmaSt=>EscalateSt]	41	1			T15	1		T68	1		T38	2
arcs[TokenCheck0St=>EscalateSt]	47	1			T68	1		T49	1		T72	1
arcs[TokenCheck1St=>EscalateSt]	27	1			T68	1		T38	1		T72	2
arcs[TransProgSt=>EscalateSt]	771	1			T15	26		T68	22		T38	16
arcs[PostTransSt=>EscalateSt]	3765	1			T4	3		T5	4		T13	9
arcs[InvalidSt=>EscalateSt]	9314	1			T12	4		T16	13		T20	7

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5251154	1			T1	75		T2	298		T3	90
auto[0]	auto[IdleSt]	16128428	1			T1	226		T2	326		T3	849
auto[0]	auto[ClkMuxSt]	28427	1			T2	3		T4	3		T5	4
auto[0]	auto[CntIncrSt]	28183	1			T2	3		T4	3		T5	4
auto[0]	auto[CntProgSt]	1331958	1			T2	6		T4	1478		T5	33
auto[0]	auto[TransCheckSt]	22408	1			T2	3		T7	14		T12	9
auto[0]	auto[TokenHashSt]	19742772	1			T2	173		T7	716		T12	98
auto[0]	auto[FlashRmaSt]	28421	1			T2	15		T7	28		T12	9
auto[0]	auto[TokenCheck0St]	10148	1			T2	3		T7	14		T12	9
auto[0]	auto[TokenCheck1St]	7460	1			T2	3		T7	14		T12	9
auto[0]	auto[TransProgSt]	305572	1			T2	6		T7	28		T12	3588
auto[0]	auto[PostTransSt]	8887186	1			T1	520		T2	1057		T4	209
auto[0]	auto[ScrapSt]	209085	1			T15	3		T17	12		T18	3437
auto[0]	auto[EscalateSt]	3381849	1			T4	270		T5	2175		T12	552
auto[0]	auto[InvalidSt]	6584057	1			T12	269		T16	2397		T20	7623
auto[1]	auto[ResetSt]	170	1			T15	5		T68	2		T38	7
auto[1]	auto[IdleSt]	96	1			T15	2		T68	5		T38	7
auto[1]	auto[ClkMuxSt]	22	1			T15	3		T49	1		T239	1
auto[1]	auto[CntIncrSt]	54	1			T15	1		T68	3		T38	4
auto[1]	auto[CntProgSt]	656	1			T15	9		T68	22		T38	20
auto[1]	auto[TransCheckSt]	74	1			T15	2		T38	3		T240	6
auto[1]	auto[TokenHashSt]	506	1			T15	16		T68	9		T48	1
auto[1]	auto[FlashRmaSt]	23	1			T15	1		T38	2		T72	1
auto[1]	auto[TokenCheck0St]	30	1			T68	1		T49	1		T72	1
auto[1]	auto[TokenCheck1St]	20	1			T38	1		T241	1		T242	1
auto[1]	auto[TransProgSt]	502	1			T15	19		T68	17		T38	9
auto[1]	auto[PostTransSt]	1943	1			T4	1		T5	3		T13	4
auto[1]	auto[ScrapSt]	34	1			T15	1		T49	2		T239	2
auto[1]	auto[EscalateSt]	1068055	1			T4	98		T5	291		T12	196
auto[1]	auto[InvalidSt]	4624	1			T12	2		T16	4		T20	5

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5251151	1			T1	75		T2	298		T3	90
auto[0]	auto[IdleSt]	16128427	1			T1	226		T2	326		T3	849
auto[0]	auto[ClkMuxSt]	28426	1			T2	3		T4	3		T5	4
auto[0]	auto[CntIncrSt]	28183	1			T2	3		T4	3		T5	4
auto[0]	auto[CntProgSt]	1331961	1			T2	6		T4	1478		T5	33
auto[0]	auto[TransCheckSt]	22404	1			T2	3		T7	14		T12	9
auto[0]	auto[TokenHashSt]	19742761	1			T2	173		T7	716		T12	98
auto[0]	auto[FlashRmaSt]	28412	1			T2	15		T7	28		T12	9
auto[0]	auto[TokenCheck0St]	10150	1			T2	3		T7	14		T12	9
auto[0]	auto[TokenCheck1St]	7460	1			T2	3		T7	14		T12	9
auto[0]	auto[TransProgSt]	305556	1			T2	6		T7	28		T12	3588
auto[0]	auto[PostTransSt]	8887194	1			T1	520		T2	1057		T4	208
auto[0]	auto[ScrapSt]	209074	1			T15	4		T17	12		T18	3437
auto[0]	auto[EscalateSt]	3370282	1			T4	172		T5	2369		T12	552
auto[0]	auto[InvalidSt]	6583991	1			T12	269		T16	2392		T20	7626
auto[1]	auto[ResetSt]	173	1			T15	4		T68	2		T38	5
auto[1]	auto[IdleSt]	97	1			T15	2		T68	3		T38	8
auto[1]	auto[ClkMuxSt]	23	1			T15	3		T38	2		T49	2
auto[1]	auto[CntIncrSt]	54	1			T15	2		T68	2		T38	3
auto[1]	auto[CntProgSt]	653	1			T15	12		T68	29		T38	24
auto[1]	auto[TransCheckSt]	78	1			T15	5		T38	1		T72	1
auto[1]	auto[TokenHashSt]	517	1			T15	12		T68	6		T38	10
auto[1]	auto[FlashRmaSt]	32	1			T15	1		T68	1		T38	1
auto[1]	auto[TokenCheck0St]	28	1			T49	1		T243	1		T244	2
auto[1]	auto[TokenCheck1St]	20	1			T68	1		T38	1		T72	2
auto[1]	auto[TransProgSt]	518	1			T15	17		T68	14		T38	10
auto[1]	auto[PostTransSt]	1935	1			T4	2		T5	1		T13	5
auto[1]	auto[ScrapSt]	45	1			T68	1		T245	2		T239	1
auto[1]	auto[EscalateSt]	1079622	1			T4	196		T5	97		T12	196
auto[1]	auto[InvalidSt]	4690	1			T12	2		T16	9		T20	2