Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.33 97.97 95.95 93.40 100.00 98.53 99.00 96.47


Total tests in report: 1009
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.19 67.19 81.25 81.25 51.49 51.49 58.72 58.72 48.84 48.84 82.95 82.95 91.79 91.79 55.30 55.30 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.4027830587
77.57 10.38 88.49 7.25 79.39 27.90 74.11 15.39 53.49 4.65 89.68 6.74 94.03 2.24 63.78 8.48 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3970779343
82.79 5.22 88.70 0.20 80.65 1.26 76.51 2.40 79.07 25.58 90.74 1.05 94.28 0.25 69.61 5.83 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.795528451
85.52 2.72 95.13 6.44 80.83 0.18 79.73 3.22 81.40 2.33 93.05 2.32 94.28 0.00 74.20 4.59 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.931293192
87.25 1.73 95.29 0.15 81.37 0.54 84.10 4.37 86.05 4.65 93.68 0.63 94.28 0.00 75.97 1.77 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1949779231
88.52 1.27 96.25 0.96 84.07 2.70 84.28 0.18 86.05 0.00 94.74 1.05 95.27 1.00 78.98 3.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.240756105
89.74 1.22 96.25 0.00 85.24 1.17 87.26 2.98 86.05 0.00 95.16 0.42 96.27 1.00 81.98 3.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2753774450
90.59 0.85 96.35 0.10 86.05 0.81 87.83 0.57 88.37 2.33 95.79 0.63 96.52 0.25 83.22 1.24 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2954488845
91.42 0.83 96.86 0.51 87.58 1.53 88.27 0.45 90.70 2.33 96.63 0.84 96.52 0.00 83.39 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2977308170
92.24 0.82 96.96 0.10 89.74 2.16 88.27 0.00 90.70 0.00 97.05 0.42 96.77 0.25 86.22 2.83 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1780359367
93.05 0.81 96.96 0.00 89.74 0.00 88.41 0.14 95.35 4.65 97.05 0.00 96.77 0.00 87.10 0.88 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.341638836
93.73 0.67 97.01 0.05 89.83 0.09 90.70 2.29 95.35 0.00 97.05 0.00 96.77 0.00 89.40 2.30 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2086491026
94.15 0.43 97.16 0.15 91.00 1.17 90.70 0.00 95.35 0.00 97.47 0.42 96.77 0.00 90.64 1.24 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1272629470
94.54 0.38 97.16 0.00 91.36 0.36 90.70 0.00 97.67 2.33 97.47 0.00 96.77 0.00 90.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.3953558684
94.90 0.36 97.16 0.00 91.36 0.00 90.70 0.00 100.00 2.33 97.47 0.00 96.77 0.00 90.81 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.681141434
95.21 0.31 97.26 0.10 91.45 0.09 90.72 0.02 100.00 0.00 97.68 0.21 96.77 0.00 92.58 1.77 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2327779817
95.45 0.25 97.26 0.00 91.45 0.00 91.21 0.49 100.00 0.00 97.68 0.00 96.77 0.00 93.82 1.24 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1494635235
95.67 0.21 97.26 0.00 91.45 0.00 91.21 0.00 100.00 0.00 97.68 0.00 98.26 1.49 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3219315720
95.87 0.20 97.62 0.35 92.35 0.90 91.36 0.15 100.00 0.00 97.68 0.00 98.26 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.939448093
96.03 0.16 97.72 0.10 92.62 0.27 91.37 0.01 100.00 0.00 97.89 0.21 98.26 0.00 94.35 0.53 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2601874354
96.18 0.15 97.72 0.00 93.34 0.72 91.37 0.00 100.00 0.00 97.89 0.00 98.26 0.00 94.70 0.35 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3352849019
96.30 0.12 97.72 0.00 93.34 0.00 92.22 0.85 100.00 0.00 97.89 0.00 98.26 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2226941381
96.41 0.11 97.72 0.00 93.34 0.00 92.96 0.74 100.00 0.00 97.89 0.00 98.26 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1061781656
96.51 0.10 97.87 0.15 93.34 0.00 93.10 0.14 100.00 0.00 98.11 0.21 98.26 0.00 94.88 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2062726451
96.58 0.08 97.87 0.00 93.88 0.54 93.10 0.00 100.00 0.00 98.11 0.00 98.26 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3731382287
96.66 0.07 97.87 0.00 93.88 0.00 93.10 0.00 100.00 0.00 98.11 0.00 98.76 0.50 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3573875542
96.72 0.06 97.87 0.00 94.33 0.45 93.10 0.00 100.00 0.00 98.11 0.00 98.76 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1656790869
96.78 0.06 97.97 0.10 94.42 0.09 93.10 0.00 100.00 0.00 98.32 0.21 98.76 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3829353753
96.83 0.06 97.97 0.00 94.60 0.18 93.11 0.01 100.00 0.00 98.53 0.21 98.76 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1877264546
96.87 0.04 97.97 0.00 94.87 0.27 93.11 0.00 100.00 0.00 98.53 0.00 98.76 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.818779414
96.91 0.04 97.97 0.00 95.14 0.27 93.11 0.00 100.00 0.00 98.53 0.00 98.76 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3696143536
96.95 0.04 97.97 0.00 95.14 0.00 93.11 0.00 100.00 0.00 98.53 0.00 99.00 0.25 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3381777010
96.98 0.03 97.97 0.00 95.14 0.00 93.35 0.24 100.00 0.00 98.53 0.00 99.00 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.259762339
97.01 0.03 97.97 0.00 95.14 0.00 93.38 0.03 100.00 0.00 98.53 0.00 99.00 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3735651876
97.04 0.03 97.97 0.00 95.14 0.00 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1730141495
97.06 0.03 97.97 0.00 95.14 0.00 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2857915229
97.09 0.03 97.97 0.00 95.14 0.00 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1153026761
97.11 0.03 97.97 0.00 95.14 0.00 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2376183460
97.14 0.03 97.97 0.00 95.14 0.00 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2372076436
97.16 0.03 97.97 0.00 95.14 0.00 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.608418983
97.19 0.03 97.97 0.00 95.14 0.00 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1038191415
97.21 0.03 97.97 0.00 95.14 0.00 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.4164596817
97.23 0.01 97.97 0.00 95.23 0.09 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1113312311
97.24 0.01 97.97 0.00 95.32 0.09 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3989727639
97.25 0.01 97.97 0.00 95.41 0.09 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4076306653
97.26 0.01 97.97 0.00 95.50 0.09 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.649722967
97.28 0.01 97.97 0.00 95.59 0.09 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2951319189
97.29 0.01 97.97 0.00 95.68 0.09 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.306061917
97.30 0.01 97.97 0.00 95.77 0.09 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3259645666
97.32 0.01 97.97 0.00 95.86 0.09 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3234661177
97.33 0.01 97.97 0.00 95.95 0.09 93.38 0.00 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3809824707
97.33 0.01 97.97 0.00 95.95 0.00 93.40 0.02 100.00 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.2823032095

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3539733612
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3037018273
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4000622350
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.32378415
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3111544263
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3589382189
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.849319179
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1854060228
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.545052483
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1900757736
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3397233770
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1890052730
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.315914499
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2482983223
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2810198371
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3426238738
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3975030486
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2861936893
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.998362491
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3334468027
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2838045436
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.515303731
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3724229998
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2908563877
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3339820191
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3942678421
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.885937806
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2003480764
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2192593942
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3872423716
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.503061583
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4250149796
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1517667744
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2832653042
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.1903977782
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.4085746701
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3310028182
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.3551133645
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.2413318276
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1246712117
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.967949504
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.223925308
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/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3931344394



Total test records in report: 1009
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2977308170 Oct 09 10:55:27 PM UTC 24 Oct 09 10:55:29 PM UTC 24 43285309 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2697551316 Oct 09 10:55:27 PM UTC 24 Oct 09 10:55:30 PM UTC 24 38721559 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.82369393 Oct 09 10:55:30 PM UTC 24 Oct 09 10:55:33 PM UTC 24 34810785 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3149470528 Oct 09 10:55:29 PM UTC 24 Oct 09 10:55:33 PM UTC 24 127872956 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.69076291 Oct 09 10:55:34 PM UTC 24 Oct 09 10:55:37 PM UTC 24 147638290 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2857915229 Oct 09 10:55:33 PM UTC 24 Oct 09 10:55:39 PM UTC 24 178963322 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3896042704 Oct 09 10:55:32 PM UTC 24 Oct 09 10:55:40 PM UTC 24 3368507727 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3995150999 Oct 09 10:55:34 PM UTC 24 Oct 09 10:55:44 PM UTC 24 737867721 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3380499455 Oct 09 10:55:28 PM UTC 24 Oct 09 10:55:44 PM UTC 24 141887410 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.4027830587 Oct 09 10:55:30 PM UTC 24 Oct 09 10:55:45 PM UTC 24 1530139887 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.430929718 Oct 09 10:55:30 PM UTC 24 Oct 09 10:55:47 PM UTC 24 1240734994 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1877264546 Oct 09 10:55:45 PM UTC 24 Oct 09 10:55:48 PM UTC 24 18446267 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.939448093 Oct 09 10:55:45 PM UTC 24 Oct 09 10:55:48 PM UTC 24 35322218 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.795528451 Oct 09 10:55:30 PM UTC 24 Oct 09 10:55:49 PM UTC 24 1653190348 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2943478949 Oct 09 10:55:36 PM UTC 24 Oct 09 10:55:50 PM UTC 24 329871259 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.929630869 Oct 09 10:55:45 PM UTC 24 Oct 09 10:55:51 PM UTC 24 126636397 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2737248883 Oct 09 10:56:40 PM UTC 24 Oct 09 10:56:42 PM UTC 24 104474326 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1949779231 Oct 09 10:55:38 PM UTC 24 Oct 09 10:55:52 PM UTC 24 2249480652 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.490312072 Oct 09 10:55:38 PM UTC 24 Oct 09 10:55:53 PM UTC 24 4897653566 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2784875536 Oct 09 10:55:51 PM UTC 24 Oct 09 10:55:54 PM UTC 24 27334307 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.2797892865 Oct 09 10:55:50 PM UTC 24 Oct 09 10:55:55 PM UTC 24 277897897 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2062726451 Oct 09 10:55:35 PM UTC 24 Oct 09 10:55:55 PM UTC 24 4337467093 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3508388368 Oct 09 10:55:51 PM UTC 24 Oct 09 10:55:58 PM UTC 24 824190085 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1494635235 Oct 09 10:55:32 PM UTC 24 Oct 09 10:56:00 PM UTC 24 7175881338 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3735651876 Oct 09 10:55:49 PM UTC 24 Oct 09 10:56:00 PM UTC 24 212276621 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1061781656 Oct 09 10:55:28 PM UTC 24 Oct 09 10:56:04 PM UTC 24 1033137158 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3970779343 Oct 09 10:55:53 PM UTC 24 Oct 09 10:56:04 PM UTC 24 1288559227 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.374459949 Oct 09 10:55:50 PM UTC 24 Oct 09 10:56:04 PM UTC 24 525033455 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.341638836 Oct 09 10:55:50 PM UTC 24 Oct 09 10:56:06 PM UTC 24 496269462 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1468508484 Oct 09 10:55:50 PM UTC 24 Oct 09 10:56:06 PM UTC 24 1310856553 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.95978059 Oct 09 10:55:48 PM UTC 24 Oct 09 10:56:10 PM UTC 24 189741835 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3774887304 Oct 09 10:56:07 PM UTC 24 Oct 09 10:56:10 PM UTC 24 17909457 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2936654289 Oct 09 10:56:08 PM UTC 24 Oct 09 10:56:11 PM UTC 24 31102008 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.2942439832 Oct 09 10:56:07 PM UTC 24 Oct 09 10:56:12 PM UTC 24 83307148 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2601874354 Oct 09 10:56:00 PM UTC 24 Oct 09 10:56:12 PM UTC 24 276327124 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.197237411 Oct 09 10:56:05 PM UTC 24 Oct 09 10:56:14 PM UTC 24 994688967 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2161279346 Oct 09 10:56:01 PM UTC 24 Oct 09 10:56:15 PM UTC 24 1415643786 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2073905757 Oct 09 10:55:59 PM UTC 24 Oct 09 10:56:15 PM UTC 24 807558731 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.4102961314 Oct 09 10:56:13 PM UTC 24 Oct 09 10:56:15 PM UTC 24 55007019 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2954488845 Oct 09 10:55:41 PM UTC 24 Oct 09 10:56:16 PM UTC 24 638601322 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3379618791 Oct 09 10:56:10 PM UTC 24 Oct 09 10:56:18 PM UTC 24 104724629 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.2458747585 Oct 09 10:56:11 PM UTC 24 Oct 09 10:56:19 PM UTC 24 452728389 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3743039168 Oct 09 10:55:54 PM UTC 24 Oct 09 10:56:19 PM UTC 24 638413246 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2327779817 Oct 09 10:55:40 PM UTC 24 Oct 09 10:56:21 PM UTC 24 1873892865 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.2177051374 Oct 09 10:56:17 PM UTC 24 Oct 09 10:56:22 PM UTC 24 130615336 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1472592513 Oct 09 10:56:11 PM UTC 24 Oct 09 10:56:24 PM UTC 24 689188421 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.240756105 Oct 09 10:55:55 PM UTC 24 Oct 09 10:56:25 PM UTC 24 4160744087 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.643719603 Oct 09 10:56:13 PM UTC 24 Oct 09 10:56:25 PM UTC 24 215662423 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2145324850 Oct 09 10:56:15 PM UTC 24 Oct 09 10:56:25 PM UTC 24 335656400 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3534950734 Oct 09 10:56:26 PM UTC 24 Oct 09 10:56:29 PM UTC 24 23465024 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.962132365 Oct 09 10:56:27 PM UTC 24 Oct 09 10:56:30 PM UTC 24 14756483 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2128203990 Oct 09 10:56:19 PM UTC 24 Oct 09 10:56:31 PM UTC 24 1221043077 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2231323910 Oct 09 10:56:21 PM UTC 24 Oct 09 10:56:31 PM UTC 24 431088153 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.2289272486 Oct 09 10:56:12 PM UTC 24 Oct 09 10:56:31 PM UTC 24 384904693 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.1491402784 Oct 09 10:56:26 PM UTC 24 Oct 09 10:56:31 PM UTC 24 148660271 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1025153160 Oct 09 10:56:17 PM UTC 24 Oct 09 10:56:32 PM UTC 24 873749865 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2397222277 Oct 09 10:56:22 PM UTC 24 Oct 09 10:56:33 PM UTC 24 708543207 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3410121027 Oct 09 10:56:20 PM UTC 24 Oct 09 10:56:34 PM UTC 24 1572575488 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2376183460 Oct 09 10:56:32 PM UTC 24 Oct 09 10:56:34 PM UTC 24 23497795 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3041407083 Oct 09 10:56:10 PM UTC 24 Oct 09 10:56:36 PM UTC 24 875808888 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1934473428 Oct 09 10:56:31 PM UTC 24 Oct 09 10:56:36 PM UTC 24 60523423 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.1974761555 Oct 09 10:55:56 PM UTC 24 Oct 09 10:56:37 PM UTC 24 2844840530 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.1621216784 Oct 09 10:56:32 PM UTC 24 Oct 09 10:56:37 PM UTC 24 307930885 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.89777823 Oct 09 10:55:34 PM UTC 24 Oct 09 10:56:38 PM UTC 24 2238711364 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3235535947 Oct 09 10:56:25 PM UTC 24 Oct 09 10:56:39 PM UTC 24 1277337086 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2850867557 Oct 09 10:56:19 PM UTC 24 Oct 09 10:56:39 PM UTC 24 4147848795 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.1454364377 Oct 09 10:56:37 PM UTC 24 Oct 09 10:56:40 PM UTC 24 137362268 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3283337189 Oct 09 10:56:30 PM UTC 24 Oct 09 10:56:42 PM UTC 24 218250305 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.261653377 Oct 09 10:56:41 PM UTC 24 Oct 09 10:56:43 PM UTC 24 37377034 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2842295021 Oct 09 10:56:42 PM UTC 24 Oct 09 10:56:44 PM UTC 24 185468046 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2207245432 Oct 09 10:56:05 PM UTC 24 Oct 09 10:56:45 PM UTC 24 775008693 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.2823032095 Oct 09 10:55:32 PM UTC 24 Oct 09 10:56:45 PM UTC 24 2973918269 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.4110302461 Oct 09 10:56:32 PM UTC 24 Oct 09 10:56:47 PM UTC 24 310108575 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.2469830428 Oct 09 10:55:55 PM UTC 24 Oct 09 10:56:52 PM UTC 24 11593412467 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.557248299 Oct 09 10:56:32 PM UTC 24 Oct 09 10:56:48 PM UTC 24 2142786855 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.1638233302 Oct 09 10:55:53 PM UTC 24 Oct 09 10:56:49 PM UTC 24 2429751502 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.2653016833 Oct 09 10:56:44 PM UTC 24 Oct 09 10:56:51 PM UTC 24 513618230 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2581968607 Oct 09 10:56:36 PM UTC 24 Oct 09 10:56:51 PM UTC 24 1345922707 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2372076436 Oct 09 10:56:49 PM UTC 24 Oct 09 10:56:51 PM UTC 24 19222495 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.603257743 Oct 09 10:56:35 PM UTC 24 Oct 09 10:56:53 PM UTC 24 614758369 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.2031895701 Oct 09 10:56:43 PM UTC 24 Oct 09 10:56:55 PM UTC 24 662656473 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1266485158 Oct 09 10:56:37 PM UTC 24 Oct 09 10:56:56 PM UTC 24 693377862 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.873307383 Oct 09 10:56:38 PM UTC 24 Oct 09 10:56:56 PM UTC 24 2180394711 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2332092559 Oct 09 10:56:38 PM UTC 24 Oct 09 10:56:57 PM UTC 24 698684678 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3865497072 Oct 09 10:56:45 PM UTC 24 Oct 09 10:56:58 PM UTC 24 1148560457 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2885772637 Oct 09 10:56:46 PM UTC 24 Oct 09 10:56:58 PM UTC 24 1241711628 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.4021277981 Oct 09 10:56:33 PM UTC 24 Oct 09 10:56:58 PM UTC 24 3162960536 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2226941381 Oct 09 10:56:27 PM UTC 24 Oct 09 10:56:58 PM UTC 24 1566663147 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2855885321 Oct 09 10:56:26 PM UTC 24 Oct 09 10:56:58 PM UTC 24 840035090 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2603162751 Oct 09 10:56:32 PM UTC 24 Oct 09 10:57:00 PM UTC 24 1658704401 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3774242519 Oct 09 10:56:58 PM UTC 24 Oct 09 10:57:00 PM UTC 24 24008366 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.2014605645 Oct 09 10:56:45 PM UTC 24 Oct 09 10:57:01 PM UTC 24 633815279 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1558084148 Oct 09 10:56:53 PM UTC 24 Oct 09 10:57:01 PM UTC 24 466003991 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3888495932 Oct 09 10:56:54 PM UTC 24 Oct 09 10:57:02 PM UTC 24 1684050576 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.993338153 Oct 09 10:57:00 PM UTC 24 Oct 09 10:57:02 PM UTC 24 13850611 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.931293192 Oct 09 10:56:38 PM UTC 24 Oct 09 10:57:03 PM UTC 24 918462632 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.456941653 Oct 09 10:57:00 PM UTC 24 Oct 09 10:57:03 PM UTC 24 81467299 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.4071068969 Oct 09 10:57:01 PM UTC 24 Oct 09 10:57:03 PM UTC 24 12597952 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.3695837439 Oct 09 10:56:49 PM UTC 24 Oct 09 10:57:05 PM UTC 24 2106066936 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.1757613588 Oct 09 10:56:58 PM UTC 24 Oct 09 10:57:05 PM UTC 24 232092556 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.3042587943 Oct 09 10:56:40 PM UTC 24 Oct 09 10:57:06 PM UTC 24 112283716 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2979095512 Oct 09 10:56:51 PM UTC 24 Oct 09 10:57:06 PM UTC 24 1841029243 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1344919303 Oct 09 10:56:55 PM UTC 24 Oct 09 10:57:07 PM UTC 24 1553449157 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2142619698 Oct 09 10:57:00 PM UTC 24 Oct 09 10:57:08 PM UTC 24 442405245 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2554391224 Oct 09 10:57:01 PM UTC 24 Oct 09 10:57:08 PM UTC 24 182452891 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2789930771 Oct 09 10:56:52 PM UTC 24 Oct 09 10:57:09 PM UTC 24 2601867752 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3562202182 Oct 09 10:57:04 PM UTC 24 Oct 09 10:57:09 PM UTC 24 171927224 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.3304411593 Oct 09 10:57:02 PM UTC 24 Oct 09 10:57:10 PM UTC 24 1325340296 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2086491026 Oct 09 10:56:43 PM UTC 24 Oct 09 10:57:10 PM UTC 24 4531191797 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.971021855 Oct 09 10:57:03 PM UTC 24 Oct 09 10:57:10 PM UTC 24 508347459 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.807327118 Oct 09 10:57:01 PM UTC 24 Oct 09 10:57:11 PM UTC 24 1242426715 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.348267442 Oct 09 10:56:53 PM UTC 24 Oct 09 10:57:11 PM UTC 24 290310435 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.1689840739 Oct 09 10:57:10 PM UTC 24 Oct 09 10:57:12 PM UTC 24 18003289 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.503196423 Oct 09 10:57:10 PM UTC 24 Oct 09 10:57:12 PM UTC 24 123643724 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.3448663967 Oct 09 10:57:04 PM UTC 24 Oct 09 10:57:12 PM UTC 24 295868170 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2917366318 Oct 09 10:57:10 PM UTC 24 Oct 09 10:57:13 PM UTC 24 189633003 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.1725042273 Oct 09 10:56:35 PM UTC 24 Oct 09 10:57:14 PM UTC 24 6848305980 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.702085239 Oct 09 10:57:00 PM UTC 24 Oct 09 10:57:14 PM UTC 24 379700706 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.4235652563 Oct 09 10:57:13 PM UTC 24 Oct 09 10:57:16 PM UTC 24 18914488 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.349127706 Oct 09 10:56:17 PM UTC 24 Oct 09 10:57:17 PM UTC 24 7966394891 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.470005788 Oct 09 10:57:06 PM UTC 24 Oct 09 10:57:18 PM UTC 24 899881109 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.839143684 Oct 09 10:57:11 PM UTC 24 Oct 09 10:57:18 PM UTC 24 645272079 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.3822083994 Oct 09 10:56:17 PM UTC 24 Oct 09 10:57:18 PM UTC 24 2146403025 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.1903977782 Oct 09 10:57:19 PM UTC 24 Oct 09 10:57:36 PM UTC 24 1551697974 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1750545733 Oct 09 10:57:06 PM UTC 24 Oct 09 10:57:20 PM UTC 24 1698461801 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2590623066 Oct 09 10:56:53 PM UTC 24 Oct 09 10:57:20 PM UTC 24 1167115300 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.2339944469 Oct 09 10:57:16 PM UTC 24 Oct 09 10:57:20 PM UTC 24 45044107 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.2703860280 Oct 09 10:57:13 PM UTC 24 Oct 09 10:57:20 PM UTC 24 283853407 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.536324902 Oct 09 10:57:20 PM UTC 24 Oct 09 10:57:34 PM UTC 24 2244694358 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.1621967231 Oct 09 10:57:07 PM UTC 24 Oct 09 10:57:21 PM UTC 24 1271551934 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.4266135146 Oct 09 10:57:00 PM UTC 24 Oct 09 10:57:22 PM UTC 24 187702486 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.383217723 Oct 09 10:57:11 PM UTC 24 Oct 09 10:57:22 PM UTC 24 80623134 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.772806042 Oct 09 10:57:11 PM UTC 24 Oct 09 10:57:22 PM UTC 24 1164363157 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1930007473 Oct 09 10:57:13 PM UTC 24 Oct 09 10:57:22 PM UTC 24 930464734 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3248328258 Oct 09 10:57:15 PM UTC 24 Oct 09 10:57:22 PM UTC 24 205263124 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3829353753 Oct 09 10:56:05 PM UTC 24 Oct 09 10:57:22 PM UTC 24 2864724294 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1892907805 Oct 09 10:57:25 PM UTC 24 Oct 09 10:57:34 PM UTC 24 1686184293 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.3994157528 Oct 09 10:57:03 PM UTC 24 Oct 09 10:57:23 PM UTC 24 766954365 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.3610006434 Oct 09 10:56:58 PM UTC 24 Oct 09 10:57:23 PM UTC 24 116644038 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3980319802 Oct 09 10:57:22 PM UTC 24 Oct 09 10:57:24 PM UTC 24 45416793 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.3943890527 Oct 09 10:57:22 PM UTC 24 Oct 09 10:57:24 PM UTC 24 79715018 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2843835631 Oct 09 10:57:18 PM UTC 24 Oct 09 10:57:26 PM UTC 24 1844626696 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.2413318276 Oct 09 10:57:22 PM UTC 24 Oct 09 10:57:26 PM UTC 24 146334596 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.608418983 Oct 09 10:57:24 PM UTC 24 Oct 09 10:57:26 PM UTC 24 79493976 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.9471651 Oct 09 10:57:11 PM UTC 24 Oct 09 10:57:28 PM UTC 24 360047593 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1202670729 Oct 09 10:57:25 PM UTC 24 Oct 09 10:57:29 PM UTC 24 460974059 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.335242847 Oct 09 10:57:23 PM UTC 24 Oct 09 10:57:29 PM UTC 24 100614783 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.2513178537 Oct 09 10:57:26 PM UTC 24 Oct 09 10:57:30 PM UTC 24 432081047 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.517431540 Oct 09 10:56:51 PM UTC 24 Oct 09 10:57:30 PM UTC 24 895084559 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.17079009 Oct 09 10:57:26 PM UTC 24 Oct 09 10:57:31 PM UTC 24 2681493309 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1959575999 Oct 09 10:57:03 PM UTC 24 Oct 09 10:57:31 PM UTC 24 2130868373 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2004558962 Oct 09 10:56:52 PM UTC 24 Oct 09 10:57:32 PM UTC 24 2183692413 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.2938215705 Oct 09 10:57:24 PM UTC 24 Oct 09 10:57:33 PM UTC 24 649272856 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.2466585297 Oct 09 10:57:10 PM UTC 24 Oct 09 10:57:33 PM UTC 24 845461920 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.336160223 Oct 09 10:57:14 PM UTC 24 Oct 09 10:57:33 PM UTC 24 412561568 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2255054797 Oct 09 10:57:20 PM UTC 24 Oct 09 10:57:33 PM UTC 24 1828419810 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3163769403 Oct 09 10:57:31 PM UTC 24 Oct 09 10:57:34 PM UTC 24 49064016 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.3551133645 Oct 09 10:57:23 PM UTC 24 Oct 09 10:57:34 PM UTC 24 4062703013 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.1076103391 Oct 09 10:57:15 PM UTC 24 Oct 09 10:57:37 PM UTC 24 20990457428 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1443455104 Oct 09 10:57:32 PM UTC 24 Oct 09 10:57:35 PM UTC 24 19010371 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3563533382 Oct 09 10:57:23 PM UTC 24 Oct 09 10:57:35 PM UTC 24 623374432 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3190622349 Oct 09 10:57:19 PM UTC 24 Oct 09 10:57:35 PM UTC 24 548216033 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.2510461939 Oct 09 10:57:23 PM UTC 24 Oct 09 10:57:38 PM UTC 24 510929194 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.518652738 Oct 09 10:57:04 PM UTC 24 Oct 09 10:57:38 PM UTC 24 6403327473 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1038191415 Oct 09 10:57:35 PM UTC 24 Oct 09 10:57:38 PM UTC 24 11437812 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1937624582 Oct 09 10:57:32 PM UTC 24 Oct 09 10:57:39 PM UTC 24 177860201 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1043117143 Oct 09 10:57:30 PM UTC 24 Oct 09 10:57:40 PM UTC 24 446891326 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.3295157879 Oct 09 10:57:36 PM UTC 24 Oct 09 10:57:40 PM UTC 24 394895352 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2843954805 Oct 09 10:57:35 PM UTC 24 Oct 09 10:57:40 PM UTC 24 51022079 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3108910901 Oct 09 10:57:33 PM UTC 24 Oct 09 10:57:41 PM UTC 24 189687928 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.4085746701 Oct 09 10:57:29 PM UTC 24 Oct 09 10:57:42 PM UTC 24 822205538 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1730002695 Oct 09 10:57:36 PM UTC 24 Oct 09 10:57:42 PM UTC 24 203240995 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1808525295 Oct 09 10:57:39 PM UTC 24 Oct 09 10:57:42 PM UTC 24 60349262 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.960669763 Oct 09 10:57:39 PM UTC 24 Oct 09 10:57:43 PM UTC 24 122487344 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3931344394 Oct 09 10:57:40 PM UTC 24 Oct 09 10:57:43 PM UTC 24 14917221 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3310028182 Oct 09 10:57:29 PM UTC 24 Oct 09 10:57:44 PM UTC 24 8618850263 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1246712117 Oct 09 10:57:37 PM UTC 24 Oct 09 10:57:44 PM UTC 24 413313095 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.137720244 Oct 09 10:57:14 PM UTC 24 Oct 09 10:57:45 PM UTC 24 1411399138 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.4164596817 Oct 09 10:57:43 PM UTC 24 Oct 09 10:57:45 PM UTC 24 10997105 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.3434661023 Oct 09 10:57:41 PM UTC 24 Oct 09 10:57:46 PM UTC 24 186737416 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3002045903 Oct 09 10:57:43 PM UTC 24 Oct 09 10:57:47 PM UTC 24 2350381084 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.967949504 Oct 09 10:57:35 PM UTC 24 Oct 09 10:57:47 PM UTC 24 504404610 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.773770340 Oct 09 10:57:23 PM UTC 24 Oct 09 10:57:48 PM UTC 24 317313057 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.401939389 Oct 09 10:57:37 PM UTC 24 Oct 09 10:57:49 PM UTC 24 1036916990 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.223925308 Oct 09 10:57:37 PM UTC 24 Oct 09 10:57:49 PM UTC 24 224253875 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.4143926347 Oct 09 10:57:25 PM UTC 24 Oct 09 10:57:50 PM UTC 24 842732229 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3663045916 Oct 09 10:57:37 PM UTC 24 Oct 09 10:57:50 PM UTC 24 883399289 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.792640357 Oct 09 10:57:40 PM UTC 24 Oct 09 10:57:50 PM UTC 24 194126999 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.1529647482 Oct 09 10:57:44 PM UTC 24 Oct 09 10:57:51 PM UTC 24 954902428 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1995573697 Oct 09 10:57:27 PM UTC 24 Oct 09 10:57:51 PM UTC 24 3349510385 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.4113359381 Oct 09 10:56:50 PM UTC 24 Oct 09 10:57:52 PM UTC 24 13077092064 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1885015 Oct 09 10:57:37 PM UTC 24 Oct 09 10:57:53 PM UTC 24 825409567 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.2208331810 Oct 09 10:57:35 PM UTC 24 Oct 09 10:57:53 PM UTC 24 335382014 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.646656565 Oct 09 10:57:50 PM UTC 24 Oct 09 10:57:53 PM UTC 24 57813016 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3374729358 Oct 09 10:57:37 PM UTC 24 Oct 09 10:57:53 PM UTC 24 541840655 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3962531575 Oct 09 10:57:25 PM UTC 24 Oct 09 10:57:53 PM UTC 24 2307871421 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3214232943 Oct 09 10:57:42 PM UTC 24 Oct 09 10:57:53 PM UTC 24 1441818688 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3459407284 Oct 09 10:57:36 PM UTC 24 Oct 09 10:57:54 PM UTC 24 1330936822 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3694631759 Oct 09 10:57:37 PM UTC 24 Oct 09 10:58:09 PM UTC 24 965298107 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3938467612 Oct 09 10:56:26 PM UTC 24 Oct 09 10:57:55 PM UTC 24 5476618327 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3737593241 Oct 09 10:57:52 PM UTC 24 Oct 09 10:57:55 PM UTC 24 13181190 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1197731108 Oct 09 10:57:02 PM UTC 24 Oct 09 10:57:55 PM UTC 24 4776449409 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2336409321 Oct 09 10:57:35 PM UTC 24 Oct 09 10:57:55 PM UTC 24 282351859 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.600226082 Oct 09 10:57:52 PM UTC 24 Oct 09 10:57:55 PM UTC 24 79030542 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1581528887 Oct 09 10:57:43 PM UTC 24 Oct 09 10:57:56 PM UTC 24 1286588064 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.602108 Oct 09 10:56:25 PM UTC 24 Oct 09 10:57:56 PM UTC 24 4803721248 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.4281828983 Oct 09 10:57:40 PM UTC 24 Oct 09 10:58:10 PM UTC 24 1283419714 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.4132763096 Oct 09 10:57:53 PM UTC 24 Oct 09 10:57:57 PM UTC 24 113693003 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3895056983 Oct 09 10:57:49 PM UTC 24 Oct 09 10:57:57 PM UTC 24 376578668 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1316936173 Oct 09 10:57:32 PM UTC 24 Oct 09 10:57:57 PM UTC 24 204916228 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3863652695 Oct 09 10:57:49 PM UTC 24 Oct 09 10:57:58 PM UTC 24 3200481542 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.3360257027 Oct 09 10:57:07 PM UTC 24 Oct 09 10:57:59 PM UTC 24 4056961951 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.141907898 Oct 09 10:57:57 PM UTC 24 Oct 09 10:57:59 PM UTC 24 14825446 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.2078293375 Oct 09 10:57:47 PM UTC 24 Oct 09 10:57:59 PM UTC 24 3908014136 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3294115055 Oct 09 10:57:48 PM UTC 24 Oct 09 10:58:00 PM UTC 24 757733601 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.108430054 Oct 09 10:57:58 PM UTC 24 Oct 09 10:58:01 PM UTC 24 45306971 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3936070630 Oct 09 10:57:57 PM UTC 24 Oct 09 10:58:01 PM UTC 24 110007558 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2096121296 Oct 09 10:57:53 PM UTC 24 Oct 09 10:58:01 PM UTC 24 81993827 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.956391776 Oct 09 10:57:43 PM UTC 24 Oct 09 10:58:01 PM UTC 24 791834601 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.122035424 Oct 09 10:57:59 PM UTC 24 Oct 09 10:58:02 PM UTC 24 91321643 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.2435589981 Oct 09 10:57:54 PM UTC 24 Oct 09 10:58:03 PM UTC 24 251424176 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.54025869 Oct 09 10:57:44 PM UTC 24 Oct 09 10:58:03 PM UTC 24 1133078919 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3809824707 Oct 09 10:56:56 PM UTC 24 Oct 09 10:58:04 PM UTC 24 2212754586 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1138024786 Oct 09 10:57:53 PM UTC 24 Oct 09 10:58:04 PM UTC 24 1185355536 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.1004414273 Oct 09 10:57:55 PM UTC 24 Oct 09 10:58:04 PM UTC 24 293997613 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1492099258 Oct 09 10:57:57 PM UTC 24 Oct 09 10:58:04 PM UTC 24 1028688695 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1650793923 Oct 09 10:57:54 PM UTC 24 Oct 09 10:58:05 PM UTC 24 416690508 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.2608835410 Oct 09 10:57:55 PM UTC 24 Oct 09 10:58:05 PM UTC 24 4994211596 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2338146035 Oct 09 10:57:48 PM UTC 24 Oct 09 10:58:07 PM UTC 24 922243005 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1467459168 Oct 09 10:58:00 PM UTC 24 Oct 09 10:58:07 PM UTC 24 204870645 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.431365038 Oct 09 10:57:57 PM UTC 24 Oct 09 10:58:07 PM UTC 24 208988449 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3681259887 Oct 09 10:57:36 PM UTC 24 Oct 09 10:58:08 PM UTC 24 2020319562 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3069290073 Oct 09 10:57:57 PM UTC 24 Oct 09 10:58:08 PM UTC 24 828713328 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2749516095 Oct 09 10:58:05 PM UTC 24 Oct 09 10:58:08 PM UTC 24 50838836 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1961256252 Oct 09 10:58:06 PM UTC 24 Oct 09 10:58:08 PM UTC 24 24351678 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.1644027903 Oct 09 10:57:59 PM UTC 24 Oct 09 10:58:09 PM UTC 24 296069592 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1900496440 Oct 09 10:57:57 PM UTC 24 Oct 09 10:58:09 PM UTC 24 713831298 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.923466477 Oct 09 10:58:06 PM UTC 24 Oct 09 10:58:09 PM UTC 24 84357409 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1153026761 Oct 09 10:58:00 PM UTC 24 Oct 09 10:58:10 PM UTC 24 164155516 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.1550863263 Oct 09 10:57:47 PM UTC 24 Oct 09 10:58:10 PM UTC 24 916619197 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.1860927924 Oct 09 10:58:06 PM UTC 24 Oct 09 10:58:10 PM UTC 24 50327292 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2753774450 Oct 09 10:57:31 PM UTC 24 Oct 09 10:58:12 PM UTC 24 1154900511 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.80599166 Oct 09 10:58:02 PM UTC 24 Oct 09 10:58:13 PM UTC 24 687818339 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3537199750 Oct 09 10:58:12 PM UTC 24 Oct 09 10:58:14 PM UTC 24 76878977 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2800960937 Oct 09 10:58:11 PM UTC 24 Oct 09 10:58:14 PM UTC 24 145148810 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1700227572 Oct 09 10:58:03 PM UTC 24 Oct 09 10:58:14 PM UTC 24 2956174061 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.3150992639 Oct 09 10:58:07 PM UTC 24 Oct 09 10:58:15 PM UTC 24 736502217 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.246315688 Oct 09 10:58:06 PM UTC 24 Oct 09 10:58:16 PM UTC 24 82594491 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.557982937 Oct 09 10:58:11 PM UTC 24 Oct 09 10:58:16 PM UTC 24 298279222 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.259762339 Oct 09 10:57:52 PM UTC 24 Oct 09 10:58:16 PM UTC 24 185309257 ps