Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	60264275	13893	0	0
claim_transition_if_regwen_rd_A	60264275	1375	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60264275	13893	0	0
T26	24694	0	0	0
T52	317746	0	0	0
T55	31897	0	0	0
T59	0	8	0	0
T74	1063	0	0	0
T95	144861	1	0	0
T96	0	17	0	0
T97	0	1	0	0
T98	0	1	0	0
T120	0	5	0	0
T161	0	3	0	0
T162	0	12	0	0
T163	0	8	0	0
T164	0	9	0	0
T165	8211	0	0	0
T166	101165	0	0	0
T167	144494	0	0	0
T168	9743	0	0	0
T169	34219	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60264275	1375	0	0
T27	62205	0	0	0
T97	121602	3	0	0
T120	0	6	0	0
T122	0	60	0	0
T124	0	109	0	0
T128	0	5	0	0
T155	0	6	0	0
T159	0	4	0	0
T161	0	8	0	0
T170	0	26	0	0
T171	0	59	0	0
T172	31342	0	0	0
T173	4119	0	0	0
T174	15120	0	0	0
T175	24152	0	0	0
T176	47648	0	0	0
T177	27844	0	0	0
T178	119929	0	0	0
T179	64914	0	0	0