Unified Coverage Report :: Module :: prim_esc_receiver

Module : prim_esc_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_esc_receiver0	100.00			100.00
tb.dut.u_prim_esc_receiver1	100.00			100.00

---

Module Instance : tb.dut.u_prim_esc_receiver0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
16.07			16.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	4.08			4.08

---

Module Instance : tb.dut.u_prim_esc_receiver1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
16.07			16.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	4.08			4.08

Toggle Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
esc_req_o	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_rx_o.resp_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_tx_i.esc_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT

Toggle Coverage for Instance : tb.dut.u_prim_esc_receiver0

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
esc_req_o	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_rx_o.resp_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_tx_i.esc_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT

Toggle Coverage for Instance : tb.dut.u_prim_esc_receiver1

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
esc_req_o	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_rx_o.resp_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
esc_tx_i.esc_p	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT