50278df8b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 10.000s | 25.964us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 21.000s | 53.362us | 96 | 100 | 96.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 5.000s | 32.744us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 50.296us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 147.258us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 21.563us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 9.000s | 34.997us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 50.296us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 5.000s | 21.563us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 21.000s | 2.299ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 14.000s | 83.825us | 5 | 5 | 100.00 |
| V1 | TOTAL | 162 | 166 | 97.59 | |||
| V2 | reset_recovery | otbn_reset | 38.000s | 159.689us | 9 | 10 | 90.00 |
| V2 | multi_error | otbn_multi_err | 1.350m | 222.840us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 1.717m | 1.574ms | 8 | 10 | 80.00 |
| V2 | stress_all | otbn_stress_all | 1.183m | 378.004us | 8 | 10 | 80.00 |
| V2 | lc_escalation | otbn_escalate | 21.000s | 223.329us | 45 | 60 | 75.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 16.455us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 18.000s | 58.249us | 9 | 10 | 90.00 |
| V2 | alert_test | otbn_alert_test | 8.000s | 21.237us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 18.565us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 56.828us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 56.828us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 5.000s | 32.744us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 50.296us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 21.563us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 25.400us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 5.000s | 32.744us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 50.296us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 21.563us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 6.000s | 25.400us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 225 | 246 | 91.46 | |||
| V2S | mem_integrity | otbn_imem_err | 9.000s | 24.782us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 74.137us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 19.000s | 129.029us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 9.000s | 20.907us | 3 | 5 | 60.00 | ||
| otbn_mac_bignum_acc_err | 10.000s | 36.534us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 8.000s | 46.499us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 10.000s | 34.435us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 9.000s | 58.610us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| otbn_tl_intg_err | 28.000s | 193.710us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 36.000s | 216.869us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | prim_count_check | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 10.000s | 25.964us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 16.000s | 74.137us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 9.000s | 24.782us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 28.000s | 193.710us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 21.000s | 223.329us | 45 | 60 | 75.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 9.000s | 24.782us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 74.137us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 16.455us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 10.000s | 34.435us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 21.000s | 53.362us | 96 | 100 | 96.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 9.000s | 24.782us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 74.137us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 16.455us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 10.000s | 34.435us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 21.000s | 223.329us | 45 | 60 | 75.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 9.000s | 24.782us | 10 | 10 | 100.00 |
| otbn_dmem_err | 16.000s | 74.137us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 16.455us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 10.000s | 34.435us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 21.000s | 53.362us | 96 | 100 | 96.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 10.000s | 39.846us | 10 | 12 | 83.33 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 9.000s | 25.693us | 4 | 5 | 80.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 44.000s | 640.221us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 44.000s | 640.221us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 10.000s | 65.196us | 5 | 10 | 50.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 10.000s | 18.121us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 2.400m | 10.004ms | 4 | 5 | 80.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 2.400m | 10.004ms | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 14.000s | 122.088us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 21.000s | 53.362us | 96 | 100 | 96.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 21.000s | 53.362us | 96 | 100 | 96.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 21.000s | 53.362us | 96 | 100 | 96.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.717m | 1.574ms | 8 | 10 | 80.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 21.000s | 53.362us | 96 | 100 | 96.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 21.000s | 53.362us | 96 | 100 | 96.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 28.000s | 222.589us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 21.000s | 53.362us | 96 | 100 | 96.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 4.467m | 1.336ms | 4 | 5 | 80.00 |
| V2S | TOTAL | 141 | 153 | 92.16 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 7.933m | 91.834ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 533 | 575 | 92.70 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 6 | 54.55 |
| V2S | 19 | 19 | 13 | 68.42 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.76 | 99.53 | 94.51 | 99.64 | 90.97 | 93.09 | 97.44 | 91.28 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,270): Assertion MatchingStatus_A has failed has 9 failures:
2.otbn_escalate.3768197090
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 3828184 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3828184 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3828184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_escalate.633209219
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 4667385 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 4667385 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 4667385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
5.otbn_rf_base_intg_err.1785719615
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 32392795 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32392795 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 32392795 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 32392795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.otbn_rf_base_intg_err.2492102754
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 117486010 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 117486010 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 117486010 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 117486010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
6.otbn_escalate.322467009
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
UVM_FATAL @ 7984587 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 7984587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.otbn_escalate.1517158916
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log
UVM_FATAL @ 10667305 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 10667305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 3 failures:
Test otbn_stress_all has 2 failures.
6.otbn_stress_all.3704577521
Line 277, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all/latest/run.log
UVM_FATAL @ 17648266 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 17648266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.otbn_stress_all.3264590596
Line 278, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all/latest/run.log
UVM_FATAL @ 9893203 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 9893203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all_with_rand_reset has 1 failures.
8.otbn_stress_all_with_rand_reset.2803006590
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 58769971 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 58769971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_controller_ispr_rdata_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 2 failures:
0.otbn_controller_ispr_rdata_err.688817526
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_controller_ispr_rdata_err/latest/run.log
UVM_FATAL @ 8278921 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_controller_ispr_rdata_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 8278921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.otbn_controller_ispr_rdata_err.647551637
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_controller_ispr_rdata_err/latest/run.log
UVM_FATAL @ 12840025 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_controller_ispr_rdata_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 12840025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 2 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
0.otbn_stress_all_with_rand_reset.3831464675
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 355493764 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 355493764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_single has 1 failures.
4.otbn_single.777721142
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_single/latest/run.log
UVM_FATAL @ 71574274 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 71574274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 2 failures:
1.otbn_multi.257031440
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_multi/latest/run.log
UVM_FATAL @ 228295058 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 228295058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.otbn_multi.3980129331
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_multi/latest/run.log
UVM_FATAL @ 1573613584 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 1573613584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 2 failures:
1.otbn_rf_base_intg_err.3290789671
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 16744120 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 16744120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.otbn_rf_base_intg_err.2561391282
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_rf_base_intg_err/latest/run.log
UVM_FATAL @ 23473123 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 23473123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:495) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 2 failures:
Test otbn_sec_cm has 1 failures.
1.otbn_sec_cm.4074240395
Line 225, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log
UVM_FATAL @ 29935989 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 29935989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
20.otbn_escalate.1724187838
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log
UVM_FATAL @ 10423119 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 10423119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:
Test otbn_ctrl_redun has 1 failures.
3.otbn_ctrl_redun.3224595664
Line 247, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21348094 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 21348094 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 21348094 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 21348094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 1 failures.
52.otbn_escalate.1420408353
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/52.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17189215 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 17189215 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 17189215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 2 failures:
74.otbn_single.3786650082
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/74.otbn_single/latest/run.log
UVM_FATAL @ 8071109 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 8071109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
81.otbn_single.570714673
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/81.otbn_single/latest/run.log
UVM_FATAL @ 33824211 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 33824211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_pc_ctrl_flow_redun_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
0.otbn_pc_ctrl_flow_redun.3011647393
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest/run.log
UVM_FATAL @ 25692708 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_pc_ctrl_flow_redun_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 25692708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1258): Assertion InitSecWipeNonZeroWideRegs_A has failed has 1 failures:
0.otbn_ctrl_redun.1062262977
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 7161668 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 7161668 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 7161668 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 7161668 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[28].InitSecWipeNonZeroWideRegs_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1258): (time 7161668 PS) Assertion tb.dut.gen_sec_wipe_wdr_asserts[27].InitSecWipeNonZeroWideRegs_A has failed
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_reset_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
1.otbn_reset.3343659963
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_reset/latest/run.log
UVM_FATAL @ 223954771 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 223954771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
1.otbn_escalate.1122464789
Line 261, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log
UVM_FATAL @ 6490949 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 6490949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
1.otbn_stress_all_with_rand_reset.2066185733
Line 318, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1352211548 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 1352211548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
1.otbn_stack_addr_integ_chk.2062477408
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10004446269 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10004446269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,273): Assertion MatchingReqRND_A has failed has 1 failures:
2.otbn_stress_all_with_rand_reset.3726844697
Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,273): (time 804077208 PS) Assertion tb.MatchingReqRND_A has failed
UVM_ERROR @ 804077208 ps: (tb.sv:273) [ASSERT FAILED] MatchingReqRND_A
UVM_INFO @ 804077208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,87): Assertion IdleIfStart_A has failed has 1 failures:
5.otbn_stress_all_with_rand_reset.2591809899
Line 295, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,87): (time 107366898 PS) Assertion tb.dut.idle_checker.IdleIfStart_A has failed
UVM_ERROR @ 107366898 ps: (otbn_idle_checker.sv:87) [ASSERT FAILED] IdleIfStart_A
UVM_INFO @ 107366898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
7.otbn_single.117613959
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_single/latest/run.log
UVM_FATAL @ 20503800 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 20503800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_sw_errs_fatal_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
9.otbn_sw_errs_fatal_chk.1516852608
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_sw_errs_fatal_chk/latest/run.log
UVM_FATAL @ 44027919 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_sw_errs_fatal_chk_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 44027919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
33.otbn_escalate.681212463
Line 261, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 5337018 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 5337018 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 5337018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
44.otbn_escalate.4108897375
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log
UVM_FATAL @ 120583904 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 120583904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_escalate_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
56.otbn_escalate.2999812277
Line 243, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/56.otbn_escalate/latest/run.log
UVM_FATAL @ 29719673 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_escalate_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 29719673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---