41bc3e0c7f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 12.000s | 124.081us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 1.217m | 1.321ms | 99 | 100 | 99.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 19.009us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 5.000s | 17.409us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 494.080us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 5.000s | 36.449us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 11.000s | 43.594us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 5.000s | 17.409us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 5.000s | 36.449us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 47.000s | 4.985ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 15.000s | 126.321us | 5 | 5 | 100.00 |
| V1 | TOTAL | 165 | 166 | 99.40 | |||
| V2 | reset_recovery | otbn_reset | 32.000s | 396.172us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 1.633m | 431.613us | 0 | 1 | 0.00 |
| V2 | back_to_back | otbn_multi | 10.350m | 9.968ms | 8 | 10 | 80.00 |
| V2 | stress_all | otbn_stress_all | 2.217m | 674.785us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 36.000s | 124.666us | 43 | 60 | 71.67 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 8.000s | 13.318us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 18.000s | 67.861us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 10.000s | 48.409us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 6.000s | 49.819us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 9.000s | 183.470us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 9.000s | 183.470us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 19.009us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 17.409us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 36.449us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 25.259us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 19.009us | 5 | 5 | 100.00 |
| otbn_csr_rw | 5.000s | 17.409us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 5.000s | 36.449us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 25.259us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 225 | 246 | 91.46 | |||
| V2S | mem_integrity | otbn_imem_err | 24.000s | 102.564us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 17.476us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 13.000s | 56.761us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 30.000s | 214.569us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 12.000s | 28.944us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 7.000s | 16.742us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 24.020us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 7.000s | 23.616us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 36.000s | 257.587us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 1.083m | 426.083us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 12.000s | 124.081us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 14.000s | 17.476us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 24.000s | 102.564us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 36.000s | 257.587us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 36.000s | 124.666us | 43 | 60 | 71.67 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 24.000s | 102.564us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 17.476us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 13.318us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 24.020us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 1.217m | 1.321ms | 99 | 100 | 99.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 24.000s | 102.564us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 17.476us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 13.318us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 24.020us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 36.000s | 124.666us | 43 | 60 | 71.67 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 24.000s | 102.564us | 10 | 10 | 100.00 |
| otbn_dmem_err | 14.000s | 17.476us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 8.000s | 13.318us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 24.020us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 1.217m | 1.321ms | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 11.000s | 34.740us | 11 | 12 | 91.67 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 12.000s | 40.568us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 46.000s | 243.169us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 46.000s | 243.169us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 11.000s | 35.004us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 11.000s | 56.328us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.283m | 10.016ms | 4 | 5 | 80.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.283m | 10.016ms | 4 | 5 | 80.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 12.000s | 27.452us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 1.217m | 1.321ms | 99 | 100 | 99.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 1.217m | 1.321ms | 99 | 100 | 99.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 1.217m | 1.321ms | 99 | 100 | 99.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 10.350m | 9.968ms | 8 | 10 | 80.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 1.217m | 1.321ms | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 1.217m | 1.321ms | 99 | 100 | 99.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 17.000s | 43.859us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 1.217m | 1.321ms | 99 | 100 | 99.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 4.483m | 1.531ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 151 | 153 | 98.69 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 17.750m | 17.345ms | 8 | 10 | 80.00 |
| V3 | TOTAL | 8 | 10 | 80.00 | |||
| TOTAL | 549 | 575 | 95.48 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 7 | 63.64 |
| V2S | 19 | 19 | 17 | 89.47 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.84 | 99.53 | 94.46 | 99.61 | 93.51 | 93.11 | 94.87 | 91.38 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,271): Assertion MatchingStatus_A has failed has 8 failures:
12.otbn_escalate.86223374334336044673479407775149216411223023912715946846158133470342534686657
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 6711246 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 6711246 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 6711246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.otbn_escalate.90741625504881704976826581346143412475355938815255200459739883982735237260846
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/14.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,271): (time 22763527 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 22763527 ps: (tb.sv:271) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 22763527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:
Test otbn_zero_state_err_urnd has 1 failures.
1.otbn_zero_state_err_urnd.78967834871977841752737179083072318157983992653756529133071159734591655478187
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13317848 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 13317848 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 13317848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 3 failures.
5.otbn_escalate.56650449652725603342863121801795965422471035940644808988391044227508318732456
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 30506997 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 30506997 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 30506997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.otbn_escalate.84990284151543690385481527793686995487446623769151642351585278119484135021760
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 104853086 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 104853086 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 104853086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test otbn_ctrl_redun has 1 failures.
8.otbn_ctrl_redun.39432251082693235620302339355333845303973711610591579312657053394830245471804
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17320767 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 17320767 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 17320767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:
0.otbn_escalate.114856469451492790036495578720447251050294046365407307841702235256852731066358
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4029510 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4029510 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 4029510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.otbn_escalate.65820781460313850880338325043177446465748485041212149640450631866201411448105
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/18.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 22861840 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 22861840 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 22861840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:
Test otbn_multi has 2 failures.
1.otbn_multi.109696598055698912185919276521481423280473394155081035097371765238051885803271
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_multi/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -6754, which encodes to -3377, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
2.otbn_multi.18752492318696011161685630850755803944009715058549537364996139108566217411390
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_multi/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5214, which encodes to -2607, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
Test otbn_single has 1 failures.
64.otbn_single.48831675834392937689502968076759351539771114865960341628266222459078135920049
Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/64.otbn_single/latest/run.log
gen_res = self.gen(model, program, end)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/snippet_gens.py", line 167, in gen
gen_res = generator.gen(self.gens, model, program)
File "/workspace/mnt/repo_top/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py", line 81, in gen
off_enc = self.imm_op_type.op_val_to_enc_val(tgt_addr, model.pc)
File "/workspace/mnt/repo_top/hw/ip/otbn/util/shared/operand.py", line 433, in op_val_to_enc_val
'' if self.signed else 'un', doc_lo, doc_hi))
ValueError: Cannot encode the value -5022, which encodes to -2511, as a 12-bit signed value. Possible range: -4096..4094.
ninja: build stopped: subcommand failed.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
24.otbn_escalate.74747021234144217625081507559832950242666482640478784206567204161760348681025
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log
UVM_FATAL @ 11424066 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 11424066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.otbn_escalate.103502562777145650473305959399263415964009828648767946307954464934409256820404
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/43.otbn_escalate/latest/run.log
UVM_FATAL @ 25579161 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 25579161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,927): Assertion ImemAddrOKnown_A has failed has 1 failures:
0.otbn_multi_err.3413517378389561398981725567256351474595204580320522452506872029518889809022
Line 409, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,927): (time 431612784 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_A has failed
UVM_ERROR @ 431612784 ps: (otbn_core.sv:927) [ASSERT FAILED] ImemAddrOKnown_A
UVM_INFO @ 431612784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:830) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
2.otbn_stress_all_with_rand_reset.49015717202589079584935714252435365558708604129535356733585082369193471660098
Line 385, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 906853220 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 906853220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
4.otbn_stack_addr_integ_chk.64765855203188073895014325635984718135157042019856362640671984941582956410884
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10016487251 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10016487251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
9.otbn_stress_all_with_rand_reset.84861792575002338581398897571511610945322966309488287480643883930233005339561
Line 524, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11756714209 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 11756714209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
16.otbn_escalate.48773098104075112493236485044358986907734194264078404222572019377239059270082
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log
UVM_FATAL @ 4346808 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 4346808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---