OTBN Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: f8b3c19a2

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1284268927

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 9.000s 252.909us 1 1 100.00
V1 single_binary otbn_single 30.000s 140.275us 93 100 93.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 44.243us 5 5 100.00
V1 csr_rw otbn_csr_rw 6.000s 10.331us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 9.000s 359.794us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 17.991us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 10.000s 96.339us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 6.000s 10.331us 20 20 100.00
otbn_csr_aliasing 6.000s 17.991us 5 5 100.00
V1 mem_walk otbn_mem_walk 37.000s 14.152ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 14.000s 163.907us 5 5 100.00
V1 TOTAL 159 166 95.78
V2 reset_recovery otbn_reset 51.000s 257.852us 10 10 100.00
V2 multi_error otbn_multi_err 1.250m 218.532us 1 1 100.00
V2 back_to_back otbn_multi 1.117m 207.066us 7 10 70.00
V2 stress_all otbn_stress_all 1.133m 172.737us 5 10 50.00
V2 lc_escalation otbn_escalate 15.000s 44.694us 51 60 85.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 29.930us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 15.000s 702.928us 9 10 90.00
V2 alert_test otbn_alert_test 8.000s 28.289us 50 50 100.00
V2 intr_test otbn_intr_test 8.000s 19.371us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 10.000s 126.766us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 10.000s 126.766us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 44.243us 5 5 100.00
otbn_csr_rw 6.000s 10.331us 20 20 100.00
otbn_csr_aliasing 6.000s 17.991us 5 5 100.00
otbn_same_csr_outstanding 8.000s 14.123us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 44.243us 5 5 100.00
otbn_csr_rw 6.000s 10.331us 20 20 100.00
otbn_csr_aliasing 6.000s 17.991us 5 5 100.00
otbn_same_csr_outstanding 8.000s 14.123us 20 20 100.00
V2 TOTAL 227 246 92.28
V2S mem_integrity otbn_imem_err 10.000s 23.701us 9 10 90.00
otbn_dmem_err 11.000s 31.210us 14 15 93.33
V2S internal_integrity otbn_alu_bignum_mod_err 11.000s 66.851us 5 5 100.00
otbn_controller_ispr_rdata_err 8.000s 22.284us 4 5 80.00
otbn_mac_bignum_acc_err 19.000s 314.473us 5 5 100.00
otbn_urnd_err 6.000s 16.758us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 20.413us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 14.657us 2 2 100.00
V2S tl_intg_err otbn_sec_cm 4.800m 4.592ms 3 5 60.00
otbn_tl_intg_err 24.000s 202.706us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 40.000s 271.667us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 9.000s 252.909us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 11.000s 31.210us 14 15 93.33
V2S sec_cm_instruction_mem_integrity otbn_imem_err 10.000s 23.701us 9 10 90.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 24.000s 202.706us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 15.000s 44.694us 51 60 85.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 10.000s 23.701us 9 10 90.00
otbn_dmem_err 11.000s 31.210us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 29.930us 4 5 80.00
otbn_illegal_mem_acc 8.000s 20.413us 5 5 100.00
otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 30.000s 140.275us 93 100 93.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 10.000s 23.701us 9 10 90.00
otbn_dmem_err 11.000s 31.210us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 29.930us 4 5 80.00
otbn_illegal_mem_acc 8.000s 20.413us 5 5 100.00
otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 15.000s 44.694us 51 60 85.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 10.000s 23.701us 9 10 90.00
otbn_dmem_err 11.000s 31.210us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 29.930us 4 5 80.00
otbn_illegal_mem_acc 8.000s 20.413us 5 5 100.00
otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 30.000s 140.275us 93 100 93.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 9.000s 103.263us 12 12 100.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 7.000s 12.128us 4 5 80.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 58.000s 251.006us 5 5 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 58.000s 251.006us 5 5 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 16.000s 46.234us 8 10 80.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 9.000s 61.232us 9 10 90.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 36.000s 10.003ms 3 5 60.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 36.000s 10.003ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 9.000s 56.816us 7 7 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 30.000s 140.275us 93 100 93.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 30.000s 140.275us 93 100 93.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 30.000s 140.275us 93 100 93.00
V2S sec_cm_write_mem_integrity otbn_multi 1.117m 207.066us 7 10 70.00
V2S sec_cm_ctrl_flow_count otbn_single 30.000s 140.275us 93 100 93.00
V2S sec_cm_ctrl_flow_sca otbn_single 30.000s 140.275us 93 100 93.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 19.000s 251.943us 5 5 100.00
V2S sec_cm_key_sideload otbn_single 30.000s 140.275us 93 100 93.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.800m 4.592ms 3 5 60.00
V2S TOTAL 142 153 92.81
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 21.933m 279.671ms 5 10 50.00
V3 TOTAL 5 10 50.00
TOTAL 533 575 92.70

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 11 11 6 54.55
V2S 19 19 11 57.89
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.74 99.52 94.33 99.62 90.99 93.07 94.87 91.17 99.16

Failure Buckets

Past Results