OTBN Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	91.382us	1	1	100.00
V1	single_binary	otbn_single	6.117m	1.621ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	14.300us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	14.617us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	313.876us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	19.868us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	61.406us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	14.617us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.868us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.050m	1.859ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	27.000s	2.911ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.200m	269.454us	10	10	100.00
V2	multi_error	otbn_multi_err	47.000s	337.464us	1	1	100.00
V2	back_to_back	otbn_multi	6.450m	6.998ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.000m	637.450us	10	10	100.00
V2	lc_escalation	otbn_escalate	3.333m	1.015ms	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	43.995us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	53.000s	294.862us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	26.542us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	29.374us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	245.692us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	245.692us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	14.300us	5	5	100.00
		otbn_csr_rw	6.000s	14.617us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.868us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	29.366us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	14.300us	5	5	100.00
		otbn_csr_rw	6.000s	14.617us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.868us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	29.366us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	11.000s	17.322us	10	10	100.00
		otbn_dmem_err	16.000s	39.133us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	35.549us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	85.122us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	29.040us	5	5	100.00
		otbn_urnd_err	8.000s	16.767us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	46.961us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	24.354us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	29.984us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
		otbn_tl_intg_err	34.000s	183.218us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	40.000s	218.849us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	91.382us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	39.133us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	17.322us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	34.000s	183.218us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	3.333m	1.015ms	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	17.322us	10	10	100.00
		otbn_dmem_err	16.000s	39.133us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	43.995us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	46.961us	5	5	100.00
		otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	6.117m	1.621ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	17.322us	10	10	100.00
		otbn_dmem_err	16.000s	39.133us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	43.995us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	46.961us	5	5	100.00
		otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	3.333m	1.015ms	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	17.322us	10	10	100.00
		otbn_dmem_err	16.000s	39.133us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	43.995us	5	5	100.00
		otbn_illegal_mem_acc	7.000s	46.961us	5	5	100.00
		otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	6.117m	1.621ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	21.000s	69.335us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	23.490us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.067m	238.305us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.067m	238.305us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	45.595us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	16.000s	279.792us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	90.631us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	90.631us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	20.000s	50.136us	3	7	42.86
V2S	sec_cm_data_mem_sec_wipe	otbn_single	6.117m	1.621ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	6.117m	1.621ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	6.117m	1.621ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	6.450m	6.998ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	6.117m	1.621ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	6.117m	1.621ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	30.066us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	6.117m	1.621ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.517m	2.098ms	2	5	40.00
V2S		TOTAL			155	163	95.09
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	28.667m	9.462ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			571	585	97.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	11	100.00
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.90	99.62	95.58	99.70	93.44	92.66	100.00	91.61	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 0.otbn_stress_all_with_rand_reset.95559470289769620107665886966703456625260079539818510921736331641825540460873
    Line 406, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9461580772 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9461580772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otbn_stress_all_with_rand_reset.7076068374587770753367677669599188275889343321783907603464307127736646970917
    Line 723, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3539408097 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3539408097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.105078455867835785185573860972584872961271590438315931653932528488622438491587
Line 328, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 223064402 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 223064402 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 223064402 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 223064402 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 223064402 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.29514693184127462364430454391473108715727805696236929843867965032720157877210
Line 297, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 38641165 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 38641165 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 38641165 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 38641165 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 38641165 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_sec_wipe_err has 3 failures.

4.otbn_sec_wipe_err.22441338765274636313675737067164181510024517640227968917682008162000296631584
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 50135898 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  50135898 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  50135898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_sec_wipe_err.22601489226129124207193382817801318573347938483195097170768761088415343864185
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19448854 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19448854 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19448854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 1.otbn_sec_wipe_err.50119657629889650221251063562245241927518305165215069758250266902027075169641
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 15761144 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  15761144 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  15761144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otbn_partial_wipe has 1 failures.
  - 4.otbn_partial_wipe.11255724653972993817190620518036342294621198804538351163925496650931803135279
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 11252442 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  11252442 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  11252442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.68282358152760722139859579987105860124879676776611387266008857774146572503561
    Line 743, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7424079004 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7424079004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.23204592941663524328272795540284856992332776778553048443677196722879275884649
    Line 482, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4529419144 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 4529419144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:486) [otbn_imem_err_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.90037832402311235171989387484613164665725898114712309665389607217143076215774
    Line 997, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 37826676487 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 37826676487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```