OTBN Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	15.000s	404.874us	1	1	100.00
V1	single_binary	otbn_single	1.550m	272.203us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	15.000s	73.985us	5	5	100.00
V1	csr_rw	otbn_csr_rw	15.000s	18.961us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	16.000s	119.411us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	15.000s	28.695us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	16.000s	139.066us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	15.000s	18.961us	20	20	100.00
		otbn_csr_aliasing	15.000s	28.695us	5	5	100.00
V1	mem_walk	otbn_mem_walk	38.000s	351.783us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	1.770ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.383m	167.504us	10	10	100.00
V2	multi_error	otbn_multi_err	1.217m	633.007us	1	1	100.00
V2	back_to_back	otbn_multi	10.150m	1.486ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.217m	321.962us	10	10	100.00
V2	lc_escalation	otbn_escalate	27.000s	79.412us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	69.849us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	23.000s	165.229us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	24.333us	50	50	100.00
V2	intr_test	otbn_intr_test	12.000s	44.530us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	19.000s	110.795us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	19.000s	110.795us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	15.000s	73.985us	5	5	100.00
		otbn_csr_rw	15.000s	18.961us	20	20	100.00
		otbn_csr_aliasing	15.000s	28.695us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	18.028us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	15.000s	73.985us	5	5	100.00
		otbn_csr_rw	15.000s	18.961us	20	20	100.00
		otbn_csr_aliasing	15.000s	28.695us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	18.028us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	16.000s	38.432us	10	10	100.00
		otbn_dmem_err	24.000s	298.986us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	20.000s	65.647us	5	5	100.00
		otbn_controller_ispr_rdata_err	21.000s	33.488us	5	5	100.00
		otbn_mac_bignum_acc_err	25.000s	38.463us	5	5	100.00
		otbn_urnd_err	12.000s	21.004us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	33.199us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	39.700us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	17.000s	68.161us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
		otbn_tl_intg_err	45.000s	249.891us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	40.000s	428.357us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	15.000s	404.874us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	24.000s	298.986us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	16.000s	38.432us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	45.000s	249.891us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	27.000s	79.412us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	16.000s	38.432us	10	10	100.00
		otbn_dmem_err	24.000s	298.986us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	69.849us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	33.199us	5	5	100.00
		otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.550m	272.203us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	16.000s	38.432us	10	10	100.00
		otbn_dmem_err	24.000s	298.986us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	69.849us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	33.199us	5	5	100.00
		otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	27.000s	79.412us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	16.000s	38.432us	10	10	100.00
		otbn_dmem_err	24.000s	298.986us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	69.849us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	33.199us	5	5	100.00
		otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.550m	272.203us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	23.968us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	12.414us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.450m	190.951us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.450m	190.951us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	20.000s	65.988us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	17.000s	49.425us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	38.000s	64.899us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	38.000s	64.899us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	28.000s	174.261us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.550m	272.203us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.550m	272.203us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.550m	272.203us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	10.150m	1.486ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.550m	272.203us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.550m	272.203us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	57.000s	755.671us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.550m	272.203us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	10.817m	17.209ms	2	5	40.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.187h	20.221ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			575	585	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.92	99.59	95.27	99.69	93.47	92.49	97.44	98.60	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test otbn_stress_all_with_rand_reset has 4 failures.
  - 0.otbn_stress_all_with_rand_reset.54430175415151542601473596043905516338227747784140858852380142004495583417978
    Line 258, in log /workspaces/repo/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9254314462 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9254314462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otbn_stress_all_with_rand_reset.62960939160314457677614229270706042616026732049262396862890369652439177562041
    Line 267, in log /workspaces/repo/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2231154043 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2231154043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed

has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.72424142719886800675176300199066215197219400688519933916703083329708088354108
Line 118, in log /workspaces/repo/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 94317884 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 94317884 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 94317884 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 94317884 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 94317884 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.82367439908938635909612195443321652324929757813553678977521354858969130599316
Line 125, in log /workspaces/repo/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 178648280 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 178648280 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 178648280 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 178648280 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 178648280 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed

has 3 failures:

Test otbn_zero_state_err_urnd has 1 failures.

3.otbn_zero_state_err_urnd.69685042552151411224610256348116570697982106759424802523290654776973106874841
Line 90, in log /workspaces/repo/scratch/os_regression/otbn-sim-xcelium/3.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32561385 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  32561385 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  32561385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

17.otbn_escalate.107131784830828349743137600383929109381441629235879630008932128295134413993857
Line 95, in log /workspaces/repo/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 261144484 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 261144484 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 261144484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.otbn_escalate.105106873983276763090016933437196786729067832389461756641286538439884469225560
Line 93, in log /workspaces/repo/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 326841097 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 326841097 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 326841097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---