OTBN Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: XCELIUM

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	16.000s	68.365us	1	1	100.00
V1	single_binary	otbn_single	59.000s	97.671us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	10.000s	18.639us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	35.908us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	16.000s	143.167us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	21.643us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	17.000s	66.852us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	35.908us	20	20	100.00
		otbn_csr_aliasing	9.000s	21.643us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.133m	1.952ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	32.000s	247.909us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.083m	200.848us	10	10	100.00
V2	multi_error	otbn_multi_err	1.283m	717.192us	1	1	100.00
V2	back_to_back	otbn_multi	1.950m	623.844us	10	10	100.00
V2	stress_all	otbn_stress_all	2.567m	401.544us	10	10	100.00
V2	lc_escalation	otbn_escalate	58.000s	183.111us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	13.000s	15.649us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	20.000s	34.886us	10	10	100.00
V2	alert_test	otbn_alert_test	13.000s	28.580us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	42.458us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	394.539us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	394.539us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	10.000s	18.639us	5	5	100.00
		otbn_csr_rw	10.000s	35.908us	20	20	100.00
		otbn_csr_aliasing	9.000s	21.643us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	24.629us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	10.000s	18.639us	5	5	100.00
		otbn_csr_rw	10.000s	35.908us	20	20	100.00
		otbn_csr_aliasing	9.000s	21.643us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	24.629us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	14.000s	33.138us	10	10	100.00
		otbn_dmem_err	18.000s	130.835us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	16.000s	62.475us	5	5	100.00
		otbn_controller_ispr_rdata_err	15.000s	65.719us	5	5	100.00
		otbn_mac_bignum_acc_err	27.000s	39.499us	5	5	100.00
		otbn_urnd_err	9.000s	18.041us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	13.000s	22.090us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	14.000s	30.783us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	84.536us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
		otbn_tl_intg_err	1.450m	355.209us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.983m	478.400us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	16.000s	68.365us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	130.835us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	33.138us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.450m	355.209us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	58.000s	183.111us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	33.138us	10	10	100.00
		otbn_dmem_err	18.000s	130.835us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	15.649us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	22.090us	5	5	100.00
		otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	59.000s	97.671us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	33.138us	10	10	100.00
		otbn_dmem_err	18.000s	130.835us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	15.649us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	22.090us	5	5	100.00
		otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	58.000s	183.111us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	33.138us	10	10	100.00
		otbn_dmem_err	18.000s	130.835us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	15.649us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	22.090us	5	5	100.00
		otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	59.000s	97.671us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	27.134us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	22.000s	48.983us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	4.883m	805.442us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	4.883m	805.442us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	23.000s	49.317us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	17.000s	227.656us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	27.000s	196.275us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	27.000s	196.275us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	23.201us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	59.000s	97.671us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	59.000s	97.671us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	59.000s	97.671us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.950m	623.844us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	59.000s	97.671us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	59.000s	97.671us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	21.828us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	59.000s	97.671us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	10.700m	2.034ms	5	5	100.00
V2S		TOTAL			162	163	99.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	9.133m	2.039ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			576	585	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.94	99.62	95.62	99.71	93.70	93.01	100.00	91.50	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test otbn_stress_all_with_rand_reset has 4 failures.
  - 5.otbn_stress_all_with_rand_reset.21273359653448874885451649017968864455310625573155769400987060250361201856914
    Line 183, in log /workspaces/repo/scratch/os_regression_2024_10_14/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 683330594 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 683330594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otbn_stress_all_with_rand_reset.844628084486932252412028257687650770358396209172501128920147214009476042770
    Line 235, in log /workspaces/repo/scratch/os_regression_2024_10_14/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 754404481 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 754404481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_sec_wipe_err has 1 failures.

6.otbn_sec_wipe_err.32457745464002814293807080834305552459189656794399662966099222570213719838944
Line 106, in log /workspaces/repo/scratch/os_regression_2024_10_14/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_14/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23201055 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  23201055 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  23201055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

36.otbn_escalate.20120709026179510974952227754617230294890225879179011759171901809113747110984
Line 106, in log /workspaces/repo/scratch/os_regression_2024_10_14/otbn-sim-xcelium/36.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_14/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 75919617 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  75919617 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  75919617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:640) virtual_sequencer [otbn_imem_err_vseq] expect alert:fatal to fire has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.60848938809073503125556194197326201269027473714821008070352123545413719404744
    Line 145, in log /workspaces/repo/scratch/os_regression_2024_10_14/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  34676871 ps: (cip_base_vseq.sv:640) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] expect alert:fatal to fire
  UVM_INFO @  34676871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.25476669052253055247334128475973343211809883485708164618735681882338981083002
    Line 180, in log /workspaces/repo/scratch/os_regression_2024_10_14/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3738460168 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 3738460168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 43.otbn_escalate.21247454463851630937566208561200246442539025455247962625855632187193578310768
    Line 98, in log /workspaces/repo/scratch/os_regression_2024_10_14/otbn-sim-xcelium/43.otbn_escalate/latest/run.log
```
  UVM_ERROR @  20536173 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @  20536173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```