OTBN Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	99.241us	1	1	100.00
V1	single_binary	otbn_single	15.000s	180.491us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	23.000s	46.791us	5	5	100.00
V1	csr_rw	otbn_csr_rw	23.000s	52.041us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	12.000s	245.841us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	11.000s	65.191us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	16.000s	44.841us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	23.000s	52.041us	20	20	100.00
		otbn_csr_aliasing	11.000s	65.191us	5	5	100.00
V1	mem_walk	otbn_mem_walk	23.000s	1.935ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	13.000s	586.041us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	34.000s	436.941us	10	10	100.00
V2	multi_error	otbn_multi_err	1.000m	787.191us	1	1	100.00
V2	back_to_back	otbn_multi	1.567m	1.147ms	10	10	100.00
V2	stress_all	otbn_stress_all	34.000s	387.091us	10	10	100.00
V2	lc_escalation	otbn_escalate	16.000s	182.869us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	13.000s	49.202us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	44.000s	582.392us	10	10	100.00
V2	alert_test	otbn_alert_test	14.000s	40.091us	50	50	100.00
V2	intr_test	otbn_intr_test	24.000s	43.191us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	25.000s	181.891us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	25.000s	181.891us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	23.000s	46.791us	5	5	100.00
		otbn_csr_rw	23.000s	52.041us	20	20	100.00
		otbn_csr_aliasing	11.000s	65.191us	5	5	100.00
		otbn_same_csr_outstanding	23.000s	59.541us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	23.000s	46.791us	5	5	100.00
		otbn_csr_rw	23.000s	52.041us	20	20	100.00
		otbn_csr_aliasing	11.000s	65.191us	5	5	100.00
		otbn_same_csr_outstanding	23.000s	59.541us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	13.000s	80.297us	10	10	100.00
		otbn_dmem_err	15.000s	59.202us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	85.591us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	129.091us	5	5	100.00
		otbn_mac_bignum_acc_err	17.000s	270.250us	5	5	100.00
		otbn_urnd_err	11.000s	29.345us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	12.000s	29.059us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	42.583us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
		otbn_tl_intg_err	32.000s	288.791us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	22.000s	484.791us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	99.241us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	15.000s	59.202us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	80.297us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	32.000s	288.791us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	16.000s	182.869us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	80.297us	10	10	100.00
		otbn_dmem_err	15.000s	59.202us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	49.202us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	29.059us	5	5	100.00
		otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	15.000s	180.491us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	80.297us	10	10	100.00
		otbn_dmem_err	15.000s	59.202us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	49.202us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	29.059us	5	5	100.00
		otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	16.000s	182.869us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	80.297us	10	10	100.00
		otbn_dmem_err	15.000s	59.202us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	49.202us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	29.059us	5	5	100.00
		otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	15.000s	180.491us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	42.774us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	42.393us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.417m	989.591us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.417m	989.591us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	1.047ms	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	246.773us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	79.154us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	79.154us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	36.641us	3	7	42.86
V2S	sec_cm_data_mem_sec_wipe	otbn_single	15.000s	180.491us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	15.000s	180.491us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	15.000s	180.491us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.567m	1.147ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	15.000s	180.491us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	15.000s	180.491us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	64.591us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	15.000s	180.491us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.700m	3.440ms	5	5	100.00
V2S		TOTAL			148	153	96.73
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.217m	3.996ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			570	575	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	11	100.00
V2S	19	19	17	89.47
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.67	99.49	93.89	99.60	91.12	92.60	94.87	90.11	94.54

Failure Buckets

• Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,863): Assertion NotBusyAndDone_A has failed has 4 failures:
  • Test otbn_sec_wipe_err has 4 failures.

    • 0.otbn_sec_wipe_err.8507941833163730588714247267571796705974275951146970239049717364701700460755
      Line 238, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,863): (time 38440573 PS) Assertion tb.dut.NotBusyAndDone_A has failed
        UVM_ERROR @  38440573 ps: (otbn.sv:863) [ASSERT FAILED] NotBusyAndDone_A
        UVM_INFO @  38440573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.otbn_sec_wipe_err.2699533165910484490786735056236393580214882462874486320379735568197345180823
      Line 239, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,863): (time 36640573 PS) Assertion tb.dut.NotBusyAndDone_A has failed
        UVM_ERROR @  36640573 ps: (otbn.sv:863) [ASSERT FAILED] NotBusyAndDone_A
        UVM_INFO @  36640573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 2 more failures.

• UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:31) virtual_sequencer [otbn_rf_base_intg_err_vseq] Register file was not used before time limit has 1 failures:
  • Test otbn_rf_base_intg_err has 1 failures.

    • 1.otbn_rf_base_intg_err.75726716284169681855930559026264910492500322557430481455696130295601385638325
      Line 236, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_rf_base_intg_err/latest/run.log

        UVM_FATAL @ 1046590573 ps: (otbn_rf_base_intg_err_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Register file was not used before time limit
        UVM_INFO @ 1046590573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.11.02_03.39.10
• 2023.10.30_18.20.13
• 2023.10.26_03.02.14
• 2023.10.23_18.20.11
• 2023.10.19_02.19.49
• 2023.10.16_18.19.22
• 2023.10.12_18.21.48