OTP_CTRL Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.310s	984.997us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.780s	5.041ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.880s	1.417ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.790s	533.746us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.660s	435.857us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.110s	1.840ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.590s	102.365us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.790s	533.746us	20	20	100.00
		otp_ctrl_csr_aliasing	6.110s	1.840ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.420s	133.802us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.310s	83.196us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.690s	9.949ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.870s	1.981ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	22.190s	1.420ms	10	10	100.00
		otp_ctrl_check_fail	28.530s	11.402ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.880s	1.087ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	2.741m	33.609ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	26.080s	7.913ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	25.450s	11.223ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	21.030s	6.859ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	57.010s	6.831ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.438m	16.047ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.086m	37.809ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.120s	554.229us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.810s	759.346us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.330s	2.920ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.330s	2.920ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.880s	1.417ms	5	5	100.00
		otp_ctrl_csr_rw	1.790s	533.746us	20	20	100.00
		otp_ctrl_csr_aliasing	6.110s	1.840ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	1.850ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.880s	1.417ms	5	5	100.00
		otp_ctrl_csr_rw	1.790s	533.746us	20	20	100.00
		otp_ctrl_csr_aliasing	6.110s	1.840ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.620s	1.850ms	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
		otp_ctrl_tl_intg_err	30.100s	19.036ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	30.100s	19.036ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.780s	5.041ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.780s	5.041ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
		otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
		otp_ctrl_macro_errs	57.010s	6.831ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
		otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
		otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
		otp_ctrl_macro_errs	57.010s	6.831ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.390s	5.917ms	200	200	100.00
		otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.870s	1.981ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	28.530s	11.402ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	2.741m	33.609ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	2.741m	33.609ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	2.741m	33.609ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	2.741m	33.609ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	2.741m	33.609ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.780s	5.041ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	2.741m	33.609ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.780s	5.041ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.117m	138.026ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.880s	1.087ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.780s	5.041ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.780s	5.041ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	57.010s	6.831ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.130s	6.061ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.976h	1.175s	92	100	92.00
V3		TOTAL			93	101	92.08
		TOTAL			1334	1343	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.46	92.63	91.72	92.83	91.83	93.45	96.53	95.19

Failure Buckets

UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.4087355447
    Line 1643, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 655040167326 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 655040167326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 62.otp_ctrl_stress_all_with_rand_reset.1444920004
    Line 1049, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2164697084177 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2164697084177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 12.otp_ctrl_stress_all_with_rand_reset.4223369935
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3f2e95d8-e1af-4fb2-a987-a1804410d1c4
```
  - 33.otp_ctrl_stress_all_with_rand_reset.2820332734
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:581807c5-bbac-49d0-bff8-97c0722458d8
```
UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* has 1 failures:
- Test otp_ctrl_stress_all has 1 failures.
  - 2.otp_ctrl_stress_all.3744996590
    Line 284, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 43854363875 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
  UVM_INFO @ 43854363875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1347) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@31518670) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

51.otp_ctrl_stress_all_with_rand_reset.2691580134
Line 966, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 204300707086 ps: (otp_ctrl_scoreboard.sv:1347) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@31518670) { a_addr: 'hf6eac2bc  a_data: 'h814da6cc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd6  a_opcode: 'h4  a_user: 'h27d4f  d_param: 'h0  d_source: 'hd6  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 204300707086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:246) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 83.otp_ctrl_stress_all_with_rand_reset.3188167657
    Line 372, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43814221467 ps: (otp_ctrl_scoreboard.sv:246) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 43814221467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:923) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 84.otp_ctrl_stress_all_with_rand_reset.3481648515
    Line 2208, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 222574623260 ps: (otp_ctrl_scoreboard.sv:923) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2400809247 [0x8f19711f] vs 4294537503 [0xfff9711f]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 222574623260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```