OTP_CTRL Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.940s	72.202us	1	1	100.00
V1	smoke	otp_ctrl_smoke	25.900s	2.108ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.810s	1.624ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.930s	667.209us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	13.680s	485.268us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	9.000s	1.221ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	6.180s	1.749ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.930s	667.209us	20	20	100.00
		otp_ctrl_csr_aliasing	9.000s	1.221ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	3.480s	538.318us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.200s	38.229us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	16.100s	646.326us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	10.220s	2.849ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	43.730s	2.900ms	10	10	100.00
		otp_ctrl_check_fail	1.126m	6.952ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	19.650s	3.760ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	3.967m	31.695ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	38.380s	3.041ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	34.110s	10.498ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.137m	23.817ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.773m	19.130ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.207m	11.103ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.199m	64.447ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	3.000s	591.895us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.190s	907.005us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.470s	183.248us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.470s	183.248us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.810s	1.624ms	5	5	100.00
		otp_ctrl_csr_rw	2.930s	667.209us	20	20	100.00
		otp_ctrl_csr_aliasing	9.000s	1.221ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	7.460s	1.264ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.810s	1.624ms	5	5	100.00
		otp_ctrl_csr_rw	2.930s	667.209us	20	20	100.00
		otp_ctrl_csr_aliasing	9.000s	1.221ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	7.460s	1.264ms	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
		otp_ctrl_tl_intg_err	34.720s	20.405ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	34.720s	20.405ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	25.900s	2.108ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	25.900s	2.108ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
		otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
		otp_ctrl_macro_errs	1.773m	19.130ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
		otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
		otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
		otp_ctrl_macro_errs	1.773m	19.130ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	44.890s	15.869ms	200	200	100.00
		otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	10.220s	2.849ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.126m	6.952ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	3.967m	31.695ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	3.967m	31.695ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	3.967m	31.695ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	3.967m	31.695ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	3.967m	31.695ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	25.900s	2.108ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	3.967m	31.695ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	25.900s	2.108ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.772m	154.581ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	19.650s	3.760ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	25.900s	2.108ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	25.900s	2.108ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.773m	19.130ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.400s	5.980ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	4.206m	60.413ms	67	100	67.00
V3		TOTAL			68	101	67.33
		TOTAL			1309	1343	97.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.51	93.58	96.60	95.50	89.64	97.21	96.03	92.99

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 16 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 16 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.103746062741465574200089467556049032199883646023510028502821063123076228711599
    Line 23229, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36915731639 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 36915731639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.otp_ctrl_stress_all_with_rand_reset.2783026150872461897912726495710596265676583103841979502812973091366492933057
    Line 2063, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1236942238 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1236942238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.61150905690544870209675608635896133065435927041283858496989151412427305882961
    Line 720, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1561382576 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1589637504 [0x5ebff180] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 1561382576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otp_ctrl_stress_all_with_rand_reset.45595328615872129834425516612117747186500142715848902651780377052670159885997
    Line 7728, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14398296703 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2258942161 [0x86a4b8d1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 14398296703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 7.otp_ctrl_stress_all_with_rand_reset.26470506275438215958510449110599867199914457120064464512379451255972130031646
    Line 102435, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35997186583 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 35997186583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 63.otp_ctrl_stress_all_with_rand_reset.94762018610944286391165896796290592526535108337358157828704566998534409140541
    Line 36789, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10115399591 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10115399591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:608) [scoreboard] Check failed item.d_data == otp_a[otp_addr] (* [*] vs * [*]) mem read mismatch at TLUL addr b17ade*, csr_addr * has 1 failures:
- Test otp_ctrl_stress_all has 1 failures.
  - 4.otp_ctrl_stress_all.80331172839332984432981982788124483739925697402913571642458192334003096194974
    Line 13847, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 891878367 ps: (otp_ctrl_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed item.d_data == otp_a[otp_addr] (3489660911 [0xcfffffef] vs 3416178318 [0xcb9ebe8e]) mem read mismatch at TLUL addr b17ade70, csr_addr 670
  UVM_INFO @ 891878367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *dc rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.otp_ctrl_stress_all_with_rand_reset.52979882384178545963689890663644587129163889649564785143666278420530654387180
    Line 27846, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10358890635 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 988 [0x3dc]) dai addr 3dc rdata0 readout mismatch
  UVM_INFO @ 10358890635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 61.otp_ctrl_stress_all_with_rand_reset.113478166133778646641257187620023778014032923261568832278705487964206641631276
    Line 4110, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 972725339 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 972725339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 69.otp_ctrl_stress_all_with_rand_reset.64773313571866545475114237473250284543800980657984473067921789779037313996356
    Line 21266, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65211819527 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 65211819527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 76.otp_ctrl_stress_all_with_rand_reset.34628486663426713947374018093077916196250706616928162586097868459451915791067
    Line 13552, in log /workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4713409358 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 616 [0x268]) dai addr 268 rdata0 readout mismatch
  UVM_INFO @ 4713409358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `12e3b8572e`