OTP_CTRL Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: f8b3c19a2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1284268927

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 1.920s 119.458us 1 1 100.00
V1 smoke otp_ctrl_smoke 18.400s 4.256ms 50 50 100.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 2.760s 918.218us 5 5 100.00
V1 csr_rw otp_ctrl_csr_rw 2.380s 589.321us 20 20 100.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 6.410s 500.467us 5 5 100.00
V1 csr_aliasing otp_ctrl_csr_aliasing 4.150s 209.167us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 4.410s 1.455ms 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 2.380s 589.321us 20 20 100.00
otp_ctrl_csr_aliasing 4.150s 209.167us 5 5 100.00
V1 mem_walk otp_ctrl_mem_walk 1.660s 525.759us 5 5 100.00
V1 mem_partial_access otp_ctrl_mem_partial_access 1.480s 499.749us 5 5 100.00
V1 TOTAL 115 116 99.14
V2 dai_access_partition_walk otp_ctrl_partition_walk 30.810s 9.993ms 1 1 100.00
V2 init_fail otp_ctrl_init_fail 9.350s 2.202ms 300 300 100.00
V2 partition_check otp_ctrl_background_chks 33.470s 7.201ms 10 10 100.00
otp_ctrl_check_fail 1.106m 8.315ms 50 50 100.00
V2 regwen_during_otp_init otp_ctrl_regwen 11.640s 4.487ms 50 50 100.00
V2 partition_lock otp_ctrl_dai_lock 28.420s 11.900ms 50 50 100.00
V2 interface_key_check otp_ctrl_parallel_key_req 34.090s 3.020ms 50 50 100.00
V2 lc_interactions otp_ctrl_parallel_lc_req 24.420s 8.383ms 50 50 100.00
otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
V2 otp_dai_errors otp_ctrl_dai_errs 28.700s 9.489ms 50 50 100.00
V2 otp_macro_errors otp_ctrl_macro_errs 41.740s 15.245ms 50 50 100.00
V2 test_access otp_ctrl_test_access 31.010s 11.205ms 49 50 98.00
V2 stress_all otp_ctrl_stress_all 7.071m 147.423ms 49 50 98.00
V2 intr_test otp_ctrl_intr_test 1.780s 561.020us 50 50 100.00
V2 alert_test otp_ctrl_alert_test 4.370s 773.648us 50 50 100.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 7.230s 2.443ms 20 20 100.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 7.230s 2.443ms 20 20 100.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 2.760s 918.218us 5 5 100.00
otp_ctrl_csr_rw 2.380s 589.321us 20 20 100.00
otp_ctrl_csr_aliasing 4.150s 209.167us 5 5 100.00
otp_ctrl_same_csr_outstanding 5.120s 1.843ms 20 20 100.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 2.760s 918.218us 5 5 100.00
otp_ctrl_csr_rw 2.380s 589.321us 20 20 100.00
otp_ctrl_csr_aliasing 4.150s 209.167us 5 5 100.00
otp_ctrl_same_csr_outstanding 5.120s 1.843ms 20 20 100.00
V2 TOTAL 1099 1101 99.82
V2S sec_cm_additional_check otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S tl_intg_err otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
otp_ctrl_tl_intg_err 25.130s 2.368ms 20 20 100.00
V2S prim_count_check otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S prim_fsm_check otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 25.130s 2.368ms 20 20 100.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 18.400s 4.256ms 50 50 100.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 18.400s 4.256ms 50 50 100.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
otp_ctrl_macro_errs 41.740s 15.245ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
otp_ctrl_macro_errs 41.740s 15.245ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 18.600s 7.704ms 200 200 100.00
otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 9.350s 2.202ms 300 300 100.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 1.106m 8.315ms 50 50 100.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 28.420s 11.900ms 50 50 100.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 28.420s 11.900ms 50 50 100.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 28.420s 11.900ms 50 50 100.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 28.420s 11.900ms 50 50 100.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 28.420s 11.900ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 18.400s 4.256ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 28.420s 11.900ms 50 50 100.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 18.400s 4.256ms 50 50 100.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 2.517m 36.070ms 5 5 100.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 11.640s 4.487ms 50 50 100.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 18.400s 4.256ms 50 50 100.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 18.400s 4.256ms 50 50 100.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 41.740s 15.245ms 50 50 100.00
V2S TOTAL 25 25 100.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 12.360s 3.405ms 1 1 100.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 2.959h 3.209s 91 100 91.00
V3 TOTAL 92 101 91.09
TOTAL 1331 1343 99.11

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 17 17 15 88.24
V2S 2 2 2 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.27 92.59 91.30 92.05 91.83 93.29 96.53 95.27

Failure Buckets

Past Results