OTP_CTRL Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	3.290s	737.253us	1	1	100.00
V1	smoke	otp_ctrl_smoke	24.660s	6.528ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.520s	103.760us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	3.240s	630.401us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.470s	1.969ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.340s	1.936ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.200s	1.121ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	3.240s	630.401us	20	20	100.00
		otp_ctrl_csr_aliasing	7.340s	1.936ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.600s	554.789us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.250s	70.868us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.950s	2.818ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	10.660s	1.929ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	44.110s	2.164ms	10	10	100.00
		otp_ctrl_check_fail	51.540s	4.766ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	22.940s	4.476ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	2.860m	12.297ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.628m	27.555ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	38.840s	8.276ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	47.770s	4.837ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.434m	70.289ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	2.347m	7.318ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	1.158h	436.977ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	3.620s	542.810us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.820s	571.994us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.480s	664.598us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.480s	664.598us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.520s	103.760us	5	5	100.00
		otp_ctrl_csr_rw	3.240s	630.401us	20	20	100.00
		otp_ctrl_csr_aliasing	7.340s	1.936ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	7.340s	1.276ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.520s	103.760us	5	5	100.00
		otp_ctrl_csr_rw	3.240s	630.401us	20	20	100.00
		otp_ctrl_csr_aliasing	7.340s	1.936ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	7.340s	1.276ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
		otp_ctrl_tl_intg_err	34.170s	2.244ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	34.170s	2.244ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	24.660s	6.528ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	24.660s	6.528ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
		otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
		otp_ctrl_macro_errs	2.434m	70.289ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
		otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
		otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
		otp_ctrl_macro_errs	2.434m	70.289ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	53.340s	5.222ms	200	200	100.00
		otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	10.660s	1.929ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	51.540s	4.766ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	2.860m	12.297ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	2.860m	12.297ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	2.860m	12.297ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	2.860m	12.297ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	2.860m	12.297ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	24.660s	6.528ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	2.860m	12.297ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	24.660s	6.528ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.135m	173.709ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	22.940s	4.476ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	24.660s	6.528ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	24.660s	6.528ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.434m	70.289ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	19.870s	6.939ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.090h	2.173s	75	100	75.00
V3		TOTAL			76	101	75.25
		TOTAL			1318	1343	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.89	93.81	96.15	95.69	91.89	97.10	96.34	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.26622165151816751817226992740897497082054394585915529111595608153570973114458
    Line 63426, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29226440864 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1149607520 [0x44859e60] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 29226440864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.otp_ctrl_stress_all_with_rand_reset.76651166715438624201172389602023661976879824588404645440773989023452776967788
    Line 141, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  37500748 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (897663198 [0x358140de] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  37500748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.110978307654462118908817451777848711621254371483711925159282431601869472267724
    Line 34536, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 197540079585 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 197540079585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.otp_ctrl_stress_all_with_rand_reset.3705216196398066928645144227565620562662022254832364918463368810694067259653
    Line 24119, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26103262739 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 26103262739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Offending '(cio_test_en_o == *)' has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 26.otp_ctrl_stress_all_with_rand_reset.103661658299752600013269155996258342788621504795097994261037680193639711595447
    Line 5266, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 41363696508 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 41363696508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 63.otp_ctrl_stress_all_with_rand_reset.100774440437124996080813189109895802104104424532682784772374308252536639785996
    Line 34105, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 15627862642 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 15627862642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.34021418285854240167838307388347256048893761707369117375951825532871084825812
    Line 151406, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 196994884674 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 196994884674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 25.otp_ctrl_stress_all_with_rand_reset.105289217141829150283957477847234260434129083536126935700027915276037905870339
    Line 83, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2598147790 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1160 [0x488]) dai addr 488 rdata0 readout mismatch
  UVM_INFO @ 2598147790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=245) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 28.otp_ctrl_stress_all_with_rand_reset.103349924727782159505937839389334450671003691147688892958535513978017834461588
    Line 37833, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 45730525313 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x64763010, Comparison=CompareOpEq, exp_data=0x0, call_count=245)
  UVM_INFO @ 45730525313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:205) [scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 74.otp_ctrl_stress_all_with_rand_reset.86020101223779958262385631918265317886896074563414329590806574294257527904712
    Line 6212, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5967821309 ps: (otp_ctrl_scoreboard.sv:205) [uvm_test_top.env.scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5967821309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=173) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 90.otp_ctrl_stress_all_with_rand_reset.25832191582663756171959316540410098801643667257344878785678368169085327462028
    Line 12713, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 132498770354 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.dai_idle (addr=0x17eac010, Comparison=CompareOpEq, exp_data=0x1, call_count=173)
  UVM_INFO @ 132498770354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

95.otp_ctrl_stress_all_with_rand_reset.96600622650151256378252003553122164323733649251954437271871330609064868486845
Line 26086, in log /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 1010177492347 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 1010181159021 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1010181992356 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1010184825695 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1010184992362 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1