Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
78.57	76.79	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_cgs_wrap[otp_ctrl_prim_reg_block]	75.00	1	100	1	64	64
tl_intg_err_cgs_wrap[otp_ctrl_core_reg_block]	78.57	1	100	1	64	64

---

Group Instance : tl_intg_err_cgs_wrap[otp_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_cgs_wrap[otp_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	4	10	75.00

Variables for Group Instance tl_intg_err_cgs_wrap[otp_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	1	1	50.00	100	0	0	2
cp_num_cmd_err_bits	4	1	3	75.00	100	1	1	0
cp_num_data_err_bits	4	2	2	50.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

---

Group Instance : tl_intg_err_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.57	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	3	11	78.57

Variables for Group Instance tl_intg_err_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	0	2	100.00	100	1	1	2
cp_num_cmd_err_bits	4	1	3	75.00	100	1	1	0
cp_num_data_err_bits	4	2	2	50.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	4578580	0			T81	304		T1	454		T12	1024

---

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	1	3	75.00

User Defined Bins for cp_num_cmd_err_bits

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[2]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4578440	1			T81	304		T1	454		T12	1024
values[1]	20	1			T2	1		T4	1		T8	1
values[3]	100	1			T2	5		T4	5		T8	5

---

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_num_data_err_bits

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[1]	0	1	1
values[2]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0]

4578420

1

T81

304

T1

454

T12

1024

values[3]

60

1

T2

3

T4

3

T8

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4578380	1			T81	304		T1	454		T12	1024
auto[TlIntgErrCmd]	40	1			T2	2		T4	2		T8	2
auto[TlIntgErrData]	60	1			T2	3		T4	3		T8	3
auto[TlIntgErrBoth]	100	1			T2	5		T4	5		T8	5

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_mem

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19361187

1

T29

20

T81

585

T1

342

auto[1]

11794400

1

T1

243

T2

7

T3

243

---

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	1	3	75.00

User Defined Bins for cp_num_cmd_err_bits

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[2]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	31155427	1			T29	20		T81	585		T1	585
values[1]	20	1			T2	1		T4	1		T8	1
values[3]	40	1			T2	2		T4	2		T8	2

---

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_num_data_err_bits

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[1]	0	1	1
values[2]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0]

31155507

1

T29

20

T81

585

T1

585

values[3]

40

1

T2

2

T4

2

T8

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31155387	1			T29	20		T81	585		T1	585
auto[TlIntgErrCmd]	120	1			T2	6		T4	6		T8	6
auto[TlIntgErrData]	40	1			T2	2		T4	2		T8	2
auto[TlIntgErrBoth]	40	1			T2	2		T4	2		T8	2