Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_chk.u_chk	87.93			87.93
tb.dut.u_reg_core.u_chk.u_chk	100.00			100.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.93			87.93

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.93			87.93

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T29,*T81,T1	Yes	T29,T81,T1	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
data_o[56:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
syndrome_o[6:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
err_o[1:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_chk.u_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	232	204	87.93
Total Bits 0->1	116	102	87.93
Total Bits 1->0	116	102	87.93

Ports	4	2	50.00
Port Bits	232	204	87.93
Port Bits 0->1	116	102	87.93
Port Bits 1->0	116	102	87.93

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T81,T1,*T12	Yes	T81,T1,T12	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
data_o[42:0]	Yes	Yes	*T81,T1,*T12	Yes	T81,T1,T12	OUTPUT
data_o[45:43]	No	No		No		OUTPUT
data_o[46]	Yes	Yes	*T2,*T4,*T8	Yes	T2,T4,T8	OUTPUT
data_o[56:47]	No	No		No		OUTPUT
syndrome_o[6:0]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
err_o[0]	Yes	Yes	*T81,*T1,*T12	Yes	T2,T4,T5	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_core.u_chk.u_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T29,*T81,T1	Yes	T29,T81,T1	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
data_o[56:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
syndrome_o[6:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
err_o[1:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT

*Tests covering at least one bit in the range