Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	40.41			40.41
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	41.78			41.78
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	46.58			46.58
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	52.74			52.74
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	56.85			56.85
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	60.27			60.27
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	61.64			61.64
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	63.70			63.70
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	63.70			63.70
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	63.70			63.70
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	64.38			64.38
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	64.38			64.38
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	64.38			64.38
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	65.07			65.07
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	65.75			65.75
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	69.18			69.18
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	69.52			69.52
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	70.55			70.55
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	71.23			71.23
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	72.60			72.60
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	72.60			72.60
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	73.97			73.97
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	74.66			74.66
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	78.77			78.77
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	80.82			80.82
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	82.19			82.19
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	84.25			84.25
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	84.93			84.93
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	86.99			86.99
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	89.04			89.04
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	90.41			90.41
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	91.78			91.78
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	91.78			91.78
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	92.47			92.47
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.41			40.41

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.41			40.41

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.78			41.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.78			41.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.58			46.58

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.58			46.58

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.74			52.74

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.74			52.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.85			56.85

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.85			56.85

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.27			60.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.27			60.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.64			61.64

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.64			61.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.70			63.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.70			63.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.70			63.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.70			63.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.70			63.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.70			63.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.07			65.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.07			65.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.75			65.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.75			65.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.18			69.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.18			69.18

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.52			69.52

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.52			69.52

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.55			70.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.55			70.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.23			71.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.23			71.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.97			73.97

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.97			73.97

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.66			74.66

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.66			74.66

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.77			78.77

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.77			78.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.82			80.82

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.82			80.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.19			82.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.19			82.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.25			84.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.25			84.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.93			84.93

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.93			84.93

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.99			86.99

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.99			86.99

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.04			89.04

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.04			89.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.41			90.41

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.41			90.41

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78			91.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78			91.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78			91.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78			91.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.47			92.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.47			92.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T20,T21,T26	Yes	T20,T21,T26	INPUT
data_o[63:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[2:0]	Yes	Yes	T26,T32,T47	Yes	T26,T32,T47	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T26,*T32,*T47	Yes	T26,T32,T47	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	118	40.41
Total Bits 0->1	146	59	40.41
Total Bits 1->0	146	59	40.41

Ports	4	0	0.00
Port Bits	292	118	40.41
Port Bits 0->1	146	59	40.41
Port Bits 1->0	146	59	40.41

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[2:1]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[4:3]	No	No		No		INPUT
data_i[5]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[7:6]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[9]	No	No		No		INPUT
data_i[12:10]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[13]	No	No		No		INPUT
data_i[15:14]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[19:16]	No	No		No		INPUT
data_i[20]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[34:21]	No	No		No		INPUT
data_i[35]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	INPUT
data_i[36]	No	No		No		INPUT
data_i[37]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	INPUT
data_i[40:38]	No	No		No		INPUT
data_i[43:41]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	INPUT
data_i[45:44]	No	No		No		INPUT
data_i[48:46]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	INPUT
data_i[49]	No	No		No		INPUT
data_i[50]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	INPUT
data_i[54:51]	No	No		No		INPUT
data_i[55]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	INPUT
data_i[56]	No	No		No		INPUT
data_i[59:57]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	INPUT
data_i[60]	No	No		No		INPUT
data_i[65:61]	Yes	Yes	T89,T93,*T94	Yes	T89,T93,T94	INPUT
data_i[66]	No	No		No		INPUT
data_i[71:67]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[2:1]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[4:3]	No	No		No		OUTPUT
data_o[5]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[7:6]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[12:10]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[15:14]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[19:16]	No	No		No		OUTPUT
data_o[20]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[34:21]	No	No		No		OUTPUT
data_o[35]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[37]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
data_o[40:38]	No	No		No		OUTPUT
data_o[43:41]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
data_o[45:44]	No	No		No		OUTPUT
data_o[48:46]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[50]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
data_o[54:51]	No	No		No		OUTPUT
data_o[55]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[59:57]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	122	41.78
Total Bits 0->1	146	61	41.78
Total Bits 1->0	146	61	41.78

Ports	4	0	0.00
Port Bits	292	122	41.78
Port Bits 0->1	146	61	41.78
Port Bits 1->0	146	61	41.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[2:0]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	INPUT
data_i[4:3]	No	No		No		INPUT
data_i[8:5]	Yes	Yes	*T42,*T44,T89	Yes	T42,T44,T89	INPUT
data_i[9]	No	No		No		INPUT
data_i[12:10]	Yes	Yes	T42,T44,*T89	Yes	T42,T44,T89	INPUT
data_i[13]	No	No		No		INPUT
data_i[26:14]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[27]	No	No		No		INPUT
data_i[31:28]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	INPUT
data_i[64:32]	No	No		No		INPUT
data_i[71:65]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	INPUT
data_o[2:0]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
data_o[4:3]	No	No		No		OUTPUT
data_o[8:5]	Yes	Yes	*T42,*T44,T89	Yes	T42,T44,T89	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[12:10]	Yes	Yes	T42,T44,*T89	Yes	T42,T44,T89	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[26:14]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[31:28]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
data_o[63:32]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	136	46.58
Total Bits 0->1	146	68	46.58
Total Bits 1->0	146	68	46.58

Ports	4	0	0.00
Port Bits	292	136	46.58
Port Bits 0->1	146	68	46.58
Port Bits 1->0	146	68	46.58

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[3:1]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[9]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[10]	No	No		No		INPUT
data_i[13:11]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[14]	No	No		No		INPUT
data_i[17:15]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[20]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[22:21]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[28]	No	No		No		INPUT
data_i[30:29]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[31]	No	No		No		INPUT
data_i[34:32]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[35]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[37]	No	No		No		INPUT
data_i[39:38]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[41:40]	No	No		No		INPUT
data_i[43:42]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[44]	No	No		No		INPUT
data_i[45]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[46]	No	No		No		INPUT
data_i[47]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[48]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[53:52]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[56:55]	No	No		No		INPUT
data_i[57]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[58]	No	No		No		INPUT
data_i[60:59]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[63:61]	No	No		No		INPUT
data_i[65:64]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[66]	No	No		No		INPUT
data_i[67]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[69:68]	No	No		No		INPUT
data_i[70]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[71]	No	No		No		INPUT
data_o[0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[3:1]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[9]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[13:11]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[17:15]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[20]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[22:21]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[30:29]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[34:32]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[39:38]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[41:40]	No	No		No		OUTPUT
data_o[43:42]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[45]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[47]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[53:52]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[56:55]	No	No		No		OUTPUT
data_o[57]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[60:59]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[63:61]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	154	52.74
Total Bits 0->1	146	77	52.74
Total Bits 1->0	146	77	52.74

Ports	4	0	0.00
Port Bits	292	154	52.74
Port Bits 0->1	146	77	52.74
Port Bits 1->0	146	77	52.74

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	No	No		No		INPUT
data_i[5:4]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[6]	No	No		No		INPUT
data_i[8:7]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[9]	No	No		No		INPUT
data_i[11:10]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[14:12]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[17:16]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[19]	No	No		No		INPUT
data_i[24:20]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[25]	No	No		No		INPUT
data_i[28:26]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[29]	No	No		No		INPUT
data_i[30]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[31]	No	No		No		INPUT
data_i[32]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[33]	No	No		No		INPUT
data_i[35:34]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[36]	No	No		No		INPUT
data_i[38:37]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[39]	No	No		No		INPUT
data_i[41:40]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[43:42]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[49:47]	No	No		No		INPUT
data_i[53:50]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[54]	No	No		No		INPUT
data_i[55]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[56]	No	No		No		INPUT
data_i[58:57]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[59]	No	No		No		INPUT
data_i[62:60]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[63]	No	No		No		INPUT
data_i[66:64]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[71:67]	No	No		No		INPUT
data_o[3:0]	No	No		No		OUTPUT
data_o[5:4]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[8:7]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[11:10]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[14:12]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[17:16]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[24:20]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[28:26]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[30]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[32]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[35:34]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[36]	No	No		No		OUTPUT
data_o[38:37]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[41:40]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[43:42]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[49:47]	No	No		No		OUTPUT
data_o[53:50]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[55]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[58:57]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[62:60]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	166	56.85
Total Bits 0->1	146	83	56.85
Total Bits 1->0	146	83	56.85

Ports	4	0	0.00
Port Bits	292	166	56.85
Port Bits 0->1	146	83	56.85
Port Bits 1->0	146	83	56.85

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[5:4]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[7]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[9]	No	No		No		INPUT
data_i[13:10]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[14]	No	No		No		INPUT
data_i[17:15]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[26:24]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[32:31]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[33]	No	No		No		INPUT
data_i[35:34]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[38:36]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[40]	No	No		No		INPUT
data_i[49:41]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[50]	No	No		No		INPUT
data_i[52:51]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[56:53]	No	No		No		INPUT
data_i[58:57]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[63:61]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[64]	No	No		No		INPUT
data_i[65]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[66]	No	No		No		INPUT
data_i[69:67]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[70]	No	No		No		INPUT
data_i[71]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[5:4]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[13:10]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[17:15]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[26:24]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[32:31]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[35:34]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[38:36]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[49:41]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[52:51]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[56:53]	No	No		No		OUTPUT
data_o[58:57]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[60:59]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	176	60.27
Total Bits 0->1	146	93	63.70
Total Bits 1->0	146	83	56.85

Ports	4	0	0.00
Port Bits	292	176	60.27
Port Bits 0->1	146	93	63.70
Port Bits 1->0	146	83	56.85

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[1]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[4]	No	No		No		INPUT
data_i[5]	Yes	Yes	*T42,*T44,*T50	Yes	T54,T55,T42	INPUT
data_i[6]	No	No		No		INPUT
data_i[9:7]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[10]	No	No		Yes	T54,T55,T56	INPUT
data_i[11]	No	No		No		INPUT
data_i[17:12]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[18]	No	No		Yes	T54,T55,T56	INPUT
data_i[21:19]	Yes	Yes	T42,T44,T50	Yes	T54,T55,T42	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	No	No		Yes	T54,T55,T56	INPUT
data_i[24]	Yes	Yes	*T42,*T44,*T50	Yes	T54,T55,T42	INPUT
data_i[25]	No	No		Yes	T54,T55,T56	INPUT
data_i[27:26]	Yes	Yes	T42,T44,T50	Yes	T54,T55,T42	INPUT
data_i[28]	No	No		Yes	T54,T55,T56	INPUT
data_i[31:29]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[33:32]	No	No		No		INPUT
data_i[39:34]	Yes	Yes	T35,T38,T42	Yes	T35,T38,T42	INPUT
data_i[40]	No	No		No		INPUT
data_i[42:41]	Yes	Yes	T35,T38,T42	Yes	T35,T38,T42	INPUT
data_i[48:43]	No	No		No		INPUT
data_i[50:49]	Yes	Yes	T35,T38,T42	Yes	T35,T38,T42	INPUT
data_i[51]	No	No		No		INPUT
data_i[52]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	INPUT
data_i[53]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	INPUT
data_i[56:55]	No	No		No		INPUT
data_i[57]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	INPUT
data_i[60:58]	No	No		No		INPUT
data_i[64:61]	Yes	Yes	*T35,*T38,T42	Yes	T35,T38,T42	INPUT
data_i[65]	No	Yes	*T54,*T55,*T56	No		INPUT
data_i[67:66]	Yes	Yes	*T35,*T38,T42	Yes	T35,T38,T42	INPUT
data_i[68]	No	No		Yes	T54,T55,T56	INPUT
data_i[71:69]	Yes	Yes	T35,T54,T55	Yes	T35,T38,T42	INPUT
data_o[0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[3:2]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[5]	Yes	Yes	*T42,*T44,*T50	Yes	T54,T55,T42	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[9:7]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[10]	No	No		Yes	T54,T55,T56	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[17:12]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[18]	No	No		Yes	T54,T55,T56	OUTPUT
data_o[21:19]	Yes	Yes	T42,T44,T50	Yes	T54,T55,T42	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	No	No		Yes	T54,T55,T56	OUTPUT
data_o[24]	Yes	Yes	*T42,*T44,*T50	Yes	T54,T55,T42	OUTPUT
data_o[25]	No	No		Yes	T54,T55,T56	OUTPUT
data_o[27:26]	Yes	Yes	T42,T44,T50	Yes	T54,T55,T42	OUTPUT
data_o[28]	No	No		Yes	T54,T55,T56	OUTPUT
data_o[31:29]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[33:32]	No	No		No		OUTPUT
data_o[39:34]	Yes	Yes	T35,T38,T42	Yes	T35,T38,T42	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[42:41]	Yes	Yes	T35,T38,T42	Yes	T35,T38,T42	OUTPUT
data_o[48:43]	No	No		No		OUTPUT
data_o[50:49]	Yes	Yes	T35,T38,T42	Yes	T35,T38,T42	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[52]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
data_o[56:55]	No	No		No		OUTPUT
data_o[57]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
data_o[60:58]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T35,T38,T42	Yes	T35,T38,T42	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	180	61.64
Total Bits 0->1	146	90	61.64
Total Bits 1->0	146	90	61.64

Ports	4	0	0.00
Port Bits	292	180	61.64
Port Bits 0->1	146	90	61.64
Port Bits 1->0	146	90	61.64

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[3:1]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
data_i[5:4]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[9]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
data_i[10]	No	No		No		INPUT
data_i[14:11]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[18:17]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
data_i[21:19]	No	No		No		INPUT
data_i[22]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
data_i[23]	No	No		No		INPUT
data_i[24]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
data_i[28:25]	No	No		No		INPUT
data_i[29]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
data_i[30]	No	No		No		INPUT
data_i[39:31]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
data_i[41:40]	No	No		No		INPUT
data_i[48:42]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[49]	No	No		No		INPUT
data_i[50]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[51]	No	No		No		INPUT
data_i[52]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[53]	No	No		No		INPUT
data_i[57:54]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[58]	No	No		No		INPUT
data_i[71:59]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[3:1]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
data_o[5:4]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[9]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[14:11]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[18:17]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
data_o[21:19]	No	No		No		OUTPUT
data_o[22]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[24]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
data_o[28:25]	No	No		No		OUTPUT
data_o[29]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[39:31]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
data_o[41:40]	No	No		No		OUTPUT
data_o[48:42]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[50]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[52]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[57:54]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[63:59]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	186	63.70
Total Bits 0->1	146	93	63.70
Total Bits 1->0	146	93	63.70

Ports	4	0	0.00
Port Bits	292	186	63.70
Port Bits 0->1	146	93	63.70
Port Bits 1->0	146	93	63.70

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	INPUT
data_i[1]	No	No		No		INPUT
data_i[2]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	INPUT
data_i[3]	No	No		No		INPUT
data_i[6:4]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	T35,T38,T42	Yes	T35,T38,T42	INPUT
data_i[12:11]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	INPUT
data_i[15:14]	No	No		No		INPUT
data_i[16]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	INPUT
data_i[17]	No	No		No		INPUT
data_i[22:18]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[23]	No	No		No		INPUT
data_i[25:24]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[26]	No	No		No		INPUT
data_i[29:27]	Yes	Yes	*T35,*T38,T42	Yes	T35,T38,T42	INPUT
data_i[30]	No	No		No		INPUT
data_i[31]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[33:32]	No	No		No		INPUT
data_i[36:34]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[38:37]	No	No		No		INPUT
data_i[42:39]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[44:43]	No	No		No		INPUT
data_i[50:45]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[53:51]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[55]	No	No		No		INPUT
data_i[66:56]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[67]	No	No		No		INPUT
data_i[71:68]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_o[0]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[2]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[6:4]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	T35,T38,T42	Yes	T35,T38,T42	OUTPUT
data_o[12:11]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
data_o[15:14]	No	No		No		OUTPUT
data_o[16]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[22:18]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[25:24]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[29:27]	Yes	Yes	*T35,*T38,T42	Yes	T35,T38,T42	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[31]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[33:32]	No	No		No		OUTPUT
data_o[36:34]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[38:37]	No	No		No		OUTPUT
data_o[42:39]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[44:43]	No	No		No		OUTPUT
data_o[50:45]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[53:51]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[63:56]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	186	63.70
Total Bits 0->1	146	93	63.70
Total Bits 1->0	146	93	63.70

Ports	4	0	0.00
Port Bits	292	186	63.70
Port Bits 0->1	146	93	63.70
Port Bits 1->0	146	93	63.70

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[3:2]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[23:17]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[27:26]	No	No		No		INPUT
data_i[33:28]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[37]	No	No		No		INPUT
data_i[40:38]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[41]	No	No		No		INPUT
data_i[45:42]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[46]	No	No		No		INPUT
data_i[48:47]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[49]	No	No		No		INPUT
data_i[51:50]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[53:52]	No	No		No		INPUT
data_i[59:54]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[63]	No	No		No		INPUT
data_i[67:64]	Yes	Yes	*T21,*T31,*T33	Yes	T21,T31,T33	INPUT
data_i[68]	No	No		No		INPUT
data_i[71:69]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[3:2]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[23:17]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[27:26]	No	No		No		OUTPUT
data_o[33:28]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[40:38]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[45:42]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[48:47]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[51:50]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[53:52]	No	No		No		OUTPUT
data_o[59:54]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	186	63.70
Total Bits 0->1	146	93	63.70
Total Bits 1->0	146	93	63.70

Ports	4	0	0.00
Port Bits	292	186	63.70
Port Bits 0->1	146	93	63.70
Port Bits 1->0	146	93	63.70

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[5:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[6]	No	No		No		INPUT
data_i[9:7]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[10]	No	No		No		INPUT
data_i[12:11]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[20:18]	No	No		No		INPUT
data_i[21]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[22]	No	No		No		INPUT
data_i[31:23]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[37:35]	No	No		No		INPUT
data_i[42:38]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[43]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[48:47]	No	No		No		INPUT
data_i[50:49]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[53:51]	No	No		No		INPUT
data_i[59:54]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[60]	No	No		No		INPUT
data_i[61]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[62]	No	No		No		INPUT
data_i[68:63]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[69]	No	No		No		INPUT
data_i[71:70]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_o[5:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[9:7]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[12:11]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[20:18]	No	No		No		OUTPUT
data_o[21]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[31:23]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[37:35]	No	No		No		OUTPUT
data_o[42:38]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[48:47]	No	No		No		OUTPUT
data_o[50:49]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[53:51]	No	No		No		OUTPUT
data_o[59:54]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[61]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	188	64.38
Total Bits 0->1	146	94	64.38
Total Bits 1->0	146	94	64.38

Ports	4	0	0.00
Port Bits	292	188	64.38
Port Bits 0->1	146	94	64.38
Port Bits 1->0	146	94	64.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[2:1]	Yes	Yes	T42,T44,T50	Yes	T53,T92,T42	INPUT
data_i[3]	No	No		No		INPUT
data_i[5:4]	Yes	Yes	T42,T44,T89	Yes	T53,T92,T42	INPUT
data_i[6]	No	No		No		INPUT
data_i[12:7]	Yes	Yes	T42,T44,*T89	Yes	T53,T92,T42	INPUT
data_i[13]	No	No		No		INPUT
data_i[17:14]	Yes	Yes	T42,T44,T50	Yes	T53,T92,T42	INPUT
data_i[18]	No	No		No		INPUT
data_i[26:19]	Yes	Yes	*T42,*T44,*T50	Yes	T53,T92,T42	INPUT
data_i[27]	No	No		No		INPUT
data_i[28]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	INPUT
data_i[29]	No	No		No		INPUT
data_i[34:30]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	INPUT
data_i[36:35]	No	No		No		INPUT
data_i[38:37]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	INPUT
data_i[41:39]	No	No		No		INPUT
data_i[43:42]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	INPUT
data_i[44]	No	No		No		INPUT
data_i[48:45]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	INPUT
data_i[49]	No	No		No		INPUT
data_i[50]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	INPUT
data_i[52:51]	No	No		No		INPUT
data_i[56:53]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	INPUT
data_i[57]	No	No		No		INPUT
data_i[58]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	INPUT
data_i[62:59]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[2:1]	Yes	Yes	T42,T44,T50	Yes	T53,T92,T42	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[5:4]	Yes	Yes	T42,T44,T89	Yes	T53,T92,T42	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[12:7]	Yes	Yes	T42,T44,*T89	Yes	T53,T92,T42	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[17:14]	Yes	Yes	T42,T44,T50	Yes	T53,T92,T42	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[26:19]	Yes	Yes	*T42,*T44,*T50	Yes	T53,T92,T42	OUTPUT
data_o[27]	No	No		No		OUTPUT
data_o[28]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[34:30]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	OUTPUT
data_o[36:35]	No	No		No		OUTPUT
data_o[38:37]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	OUTPUT
data_o[41:39]	No	No		No		OUTPUT
data_o[43:42]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[48:45]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[50]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[56:53]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[58]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	OUTPUT
data_o[62:59]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	188	64.38
Total Bits 0->1	146	94	64.38
Total Bits 1->0	146	94	64.38

Ports	4	0	0.00
Port Bits	292	188	64.38
Port Bits 0->1	146	94	64.38
Port Bits 1->0	146	94	64.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[7]	No	No		No		INPUT
data_i[9:8]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[11:10]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[15]	No	No		No		INPUT
data_i[19:16]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[25:23]	No	No		No		INPUT
data_i[27:26]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[28]	No	No		No		INPUT
data_i[30:29]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[32:31]	No	No		No		INPUT
data_i[36:33]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[38:37]	No	No		No		INPUT
data_i[43:39]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[44]	No	No		No		INPUT
data_i[46:45]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[49:47]	No	No		No		INPUT
data_i[52:50]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[53]	No	No		No		INPUT
data_i[57:54]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[59:58]	No	No		No		INPUT
data_i[60]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[9:8]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[11:10]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[19:16]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[25:23]	No	No		No		OUTPUT
data_o[27:26]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[30:29]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[32:31]	No	No		No		OUTPUT
data_o[36:33]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[38:37]	No	No		No		OUTPUT
data_o[43:39]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[46:45]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[49:47]	No	No		No		OUTPUT
data_o[52:50]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[57:54]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[59:58]	No	No		No		OUTPUT
data_o[60]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	188	64.38
Total Bits 0->1	146	94	64.38
Total Bits 1->0	146	94	64.38

Ports	4	0	0.00
Port Bits	292	188	64.38
Port Bits 0->1	146	94	64.38
Port Bits 1->0	146	94	64.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[2]	No	No		No		INPUT
data_i[4:3]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[5]	No	No		No		INPUT
data_i[9:6]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[10]	No	No		No		INPUT
data_i[11]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[12]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[16]	No	No		No		INPUT
data_i[19:17]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[21:20]	No	No		No		INPUT
data_i[23:22]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[24]	No	No		No		INPUT
data_i[31:25]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[35]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[40]	No	No		No		INPUT
data_i[41]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[43:42]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[47]	No	No		No		INPUT
data_i[49:48]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[51:50]	No	No		No		INPUT
data_i[57:52]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[58]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[4:3]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[9:6]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[11]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[19:17]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[21:20]	No	No		No		OUTPUT
data_o[23:22]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[31:25]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[41]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[43:42]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[49:48]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[51:50]	No	No		No		OUTPUT
data_o[57:52]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	190	65.07
Total Bits 0->1	146	95	65.07
Total Bits 1->0	146	95	65.07

Ports	4	0	0.00
Port Bits	292	190	65.07
Port Bits 0->1	146	95	65.07
Port Bits 1->0	146	95	65.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[6:1]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[14:9]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[15]	No	No		No		INPUT
data_i[18:16]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[19]	No	No		No		INPUT
data_i[22:20]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[34:30]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[35]	No	No		No		INPUT
data_i[38:36]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[39]	No	No		No		INPUT
data_i[42:40]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[45:43]	No	No		No		INPUT
data_i[47:46]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[48]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[55]	No	No		No		INPUT
data_i[58:56]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[59]	No	No		No		INPUT
data_i[64:60]	Yes	Yes	*T20,T21,*T22	Yes	T20,T21,T22	INPUT
data_i[65]	No	No		No		INPUT
data_i[71:66]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[6:1]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[14:9]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[18:16]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[22:20]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[34:30]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[38:36]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[42:40]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[45:43]	No	No		No		OUTPUT
data_o[47:46]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[58:56]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	192	65.75
Total Bits 0->1	146	96	65.75
Total Bits 1->0	146	96	65.75

Ports	4	0	0.00
Port Bits	292	192	65.75
Port Bits 0->1	146	96	65.75
Port Bits 1->0	146	96	65.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[28:0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[29]	No	No		No		INPUT
data_i[32:30]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	INPUT
data_i[36:33]	No	No		No		INPUT
data_i[40:37]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[44:41]	No	No		No		INPUT
data_i[45]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[46]	No	No		No		INPUT
data_i[47]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[50:48]	No	No		No		INPUT
data_i[52:51]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[53]	No	No		No		INPUT
data_i[54]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[57:55]	No	No		No		INPUT
data_i[58]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[59]	No	No		No		INPUT
data_i[60]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[61]	No	No		No		INPUT
data_i[62]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	INPUT
data_o[28:0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[32:30]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	OUTPUT
data_o[36:33]	No	No		No		OUTPUT
data_o[40:37]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[44:41]	No	No		No		OUTPUT
data_o[45]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[47]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[50:48]	No	No		No		OUTPUT
data_o[52:51]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[57:55]	No	No		No		OUTPUT
data_o[58]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[60]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[62]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	202	69.18
Total Bits 0->1	146	101	69.18
Total Bits 1->0	146	101	69.18

Ports	4	0	0.00
Port Bits	292	202	69.18
Port Bits 0->1	146	101	69.18
Port Bits 1->0	146	101	69.18

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[3:1]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[4]	No	No		No		INPUT
data_i[8:5]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[9]	No	No		No		INPUT
data_i[10]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[27:17]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[32:28]	No	No		No		INPUT
data_i[41:33]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[42]	No	No		No		INPUT
data_i[46:43]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[47]	No	No		No		INPUT
data_i[51:48]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[55]	No	No		No		INPUT
data_i[61:56]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[67:64]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[68]	No	No		No		INPUT
data_i[71:69]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[3:1]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[8:5]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[10]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[27:17]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[32:28]	No	No		No		OUTPUT
data_o[41:33]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[46:43]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[51:48]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[61:56]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	203	69.52
Total Bits 0->1	146	101	69.18
Total Bits 1->0	146	102	69.86

Ports	4	0	0.00
Port Bits	292	203	69.52
Port Bits 0->1	146	101	69.18
Port Bits 1->0	146	102	69.86

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[11]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[17:16]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[19]	No	No		No		INPUT
data_i[23:20]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[26]	No	No		No		INPUT
data_i[37:27]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[38]	No	No		No		INPUT
data_i[44:39]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[47:45]	No	No		No		INPUT
data_i[51:48]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[52]	No	No		No		INPUT
data_i[55:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[56]	No	No		No		INPUT
data_i[59:57]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[61:60]	No	No		No		INPUT
data_i[64:62]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[65]	No	Yes	*T97,*T98,*T99	No		INPUT
data_i[71:66]	Yes	Yes	T42,T44,T50	Yes	T53,T92,T42	INPUT
data_o[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[17:16]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[23:20]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[37:27]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[44:39]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[47:45]	No	No		No		OUTPUT
data_o[51:48]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[55:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[59:57]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[61:60]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	206	70.55
Total Bits 0->1	146	103	70.55
Total Bits 1->0	146	103	70.55

Ports	4	0	0.00
Port Bits	292	206	70.55
Port Bits 0->1	146	103	70.55
Port Bits 1->0	146	103	70.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[1]	No	No		No		INPUT
data_i[4:2]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[8]	No	No		No		INPUT
data_i[12:9]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[13]	No	No		No		INPUT
data_i[17:14]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[18]	No	No		No		INPUT
data_i[21:19]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[24:22]	No	No		No		INPUT
data_i[28:25]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[38:31]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[39]	No	No		No		INPUT
data_i[45:40]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[46]	No	No		No		INPUT
data_i[50:47]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[52:51]	No	No		No		INPUT
data_i[55:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[56]	No	No		No		INPUT
data_i[60:57]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[61]	No	No		No		INPUT
data_i[69:62]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[70]	No	No		No		INPUT
data_i[71]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[0]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[4:2]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[12:9]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[17:14]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[21:19]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[24:22]	No	No		No		OUTPUT
data_o[28:25]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[38:31]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[45:40]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[50:47]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[55:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[60:57]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	208	71.23
Total Bits 0->1	146	104	71.23
Total Bits 1->0	146	104	71.23

Ports	4	0	0.00
Port Bits	292	208	71.23
Port Bits 0->1	146	104	71.23
Port Bits 1->0	146	104	71.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[2]	No	No		No		INPUT
data_i[7:3]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[8]	No	No		No		INPUT
data_i[9]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[11:10]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[14]	No	No		No		INPUT
data_i[16:15]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[17]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T20,*T22,*T34	Yes	T20,T22,T34	INPUT
data_i[19]	No	No		No		INPUT
data_i[28:20]	Yes	Yes	T20,*T21,T22	Yes	T20,T21,T22	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[36:31]	Yes	Yes	T20,T22,T34	Yes	T20,T22,T34	INPUT
data_i[37]	No	No		No		INPUT
data_i[45:38]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[48:46]	No	No		No		INPUT
data_i[53:49]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[54]	No	No		No		INPUT
data_i[56:55]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[57]	No	No		No		INPUT
data_i[60:58]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[7:3]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[9]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[11:10]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[16:15]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T20,*T22,*T34	Yes	T20,T22,T34	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[28:20]	Yes	Yes	T20,*T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[36:31]	Yes	Yes	T20,T22,T34	Yes	T20,T22,T34	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[45:38]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[48:46]	No	No		No		OUTPUT
data_o[53:49]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[56:55]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[60:58]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	212	72.60
Total Bits 0->1	146	106	72.60
Total Bits 1->0	146	106	72.60

Ports	4	0	0.00
Port Bits	292	212	72.60
Port Bits 0->1	146	106	72.60
Port Bits 1->0	146	106	72.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
data_i[3]	No	No		No		INPUT
data_i[8:4]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[9]	No	No		No		INPUT
data_i[31:10]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[35]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[37]	No	No		No		INPUT
data_i[38]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[39]	No	No		No		INPUT
data_i[41:40]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[42]	No	No		No		INPUT
data_i[43]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[45:44]	No	No		No		INPUT
data_i[49:46]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[52:50]	No	No		No		INPUT
data_i[59:53]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[62:60]	No	No		No		INPUT
data_i[71:63]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_o[2:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[8:4]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[31:10]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[38]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[41:40]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[43]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[45:44]	No	No		No		OUTPUT
data_o[49:46]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[52:50]	No	No		No		OUTPUT
data_o[59:53]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[62:60]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	212	72.60
Total Bits 0->1	146	106	72.60
Total Bits 1->0	146	106	72.60

Ports	4	0	0.00
Port Bits	292	212	72.60
Port Bits 0->1	146	106	72.60
Port Bits 1->0	146	106	72.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	No	No		No		INPUT
data_i[12:2]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	INPUT
data_i[15]	No	No		No		INPUT
data_i[20:16]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[22:21]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[25]	No	No		No		INPUT
data_i[36:26]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[38:37]	No	No		No		INPUT
data_i[40:39]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[42:41]	No	No		No		INPUT
data_i[51:43]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[55]	No	No		No		INPUT
data_i[57:56]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[58]	No	No		No		INPUT
data_i[60:59]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[12:2]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[20:16]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[22:21]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[36:26]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[38:37]	No	No		No		OUTPUT
data_o[40:39]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[42:41]	No	No		No		OUTPUT
data_o[51:43]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[57:56]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[60:59]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	216	73.97
Total Bits 0->1	146	108	73.97
Total Bits 1->0	146	108	73.97

Ports	4	0	0.00
Port Bits	292	216	73.97
Port Bits 0->1	146	108	73.97
Port Bits 1->0	146	108	73.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	*T26,*T32,*T47	Yes	T26,T32,T47	INPUT
data_i[4]	No	No		No		INPUT
data_i[6:5]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[12:9]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[13]	No	No		No		INPUT
data_i[15:14]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[16]	No	No		No		INPUT
data_i[31:17]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[33:32]	No	No		No		INPUT
data_i[34]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[35]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[40]	No	No		No		INPUT
data_i[43:41]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[44]	No	No		No		INPUT
data_i[46:45]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[47]	No	No		No		INPUT
data_i[50:48]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[51]	No	No		No		INPUT
data_i[58:52]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[59]	No	No		No		INPUT
data_i[61:60]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[62]	No	No		No		INPUT
data_i[68:63]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[70:69]	No	No		No		INPUT
data_i[71]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_o[3:0]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[6:5]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[12:9]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[15:14]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[31:17]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[33:32]	No	No		No		OUTPUT
data_o[34]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[43:41]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[46:45]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[50:48]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[51]	No	No		No		OUTPUT
data_o[58:52]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[61:60]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[62]	No	No		No		OUTPUT
data_o[63]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
syndrome_o[2:0]	Yes	Yes	T26,T32,T47	Yes	T26,T32,T47	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T26,*T32,*T47	Yes	T26,T32,T47	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	218	74.66
Total Bits 0->1	146	109	74.66
Total Bits 1->0	146	109	74.66

Ports	4	0	0.00
Port Bits	292	218	74.66
Port Bits 0->1	146	109	74.66
Port Bits 1->0	146	109	74.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[4]	No	No		No		INPUT
data_i[7:5]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[11]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[16]	No	No		No		INPUT
data_i[18:17]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[19]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[22]	No	No		No		INPUT
data_i[38:23]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[39]	No	No		No		INPUT
data_i[40]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[41]	No	No		No		INPUT
data_i[56:42]	Yes	Yes	*T40,T42,*T43	Yes	T40,T42,T43	INPUT
data_i[57]	No	No		No		INPUT
data_i[62:58]	Yes	Yes	*T40,T42,*T43	Yes	T40,T42,T43	INPUT
data_i[63]	No	No		No		INPUT
data_i[66:64]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[67]	No	No		No		INPUT
data_i[71:68]	Yes	Yes	T40,T42,T43	Yes	T40,T42,T43	INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[3:2]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[7:5]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[18:17]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[38:23]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[40]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[56:42]	Yes	Yes	*T40,T42,*T43	Yes	T40,T42,T43	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[62:58]	Yes	Yes	*T40,T42,*T43	Yes	T40,T42,T43	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	230	78.77
Total Bits 0->1	146	115	78.77
Total Bits 1->0	146	115	78.77

Ports	4	0	0.00
Port Bits	292	230	78.77
Port Bits 0->1	146	115	78.77
Port Bits 1->0	146	115	78.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[1]	No	No		No		INPUT
data_i[2]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[3]	No	No		No		INPUT
data_i[11:4]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[12]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[16]	No	No		No		INPUT
data_i[18:17]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[19]	No	No		No		INPUT
data_i[38:20]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[39]	No	No		No		INPUT
data_i[41:40]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[42]	No	No		No		INPUT
data_i[55:43]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[56]	No	No		No		INPUT
data_i[62:57]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[63]	No	No		No		INPUT
data_i[68:64]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[69]	No	No		No		INPUT
data_i[71:70]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_o[0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[2]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[11:4]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[18:17]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[38:20]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[41:40]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[55:43]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[62:57]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	236	80.82
Total Bits 0->1	146	118	80.82
Total Bits 1->0	146	118	80.82

Ports	4	0	0.00
Port Bits	292	236	80.82
Port Bits 0->1	146	118	80.82
Port Bits 1->0	146	118	80.82

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[2]	No	No		No		INPUT
data_i[5:3]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[6]	No	No		No		INPUT
data_i[12:7]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[13]	No	No		No		INPUT
data_i[16:14]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[17]	No	No		No		INPUT
data_i[28:18]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[29]	No	No		No		INPUT
data_i[30]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[31]	No	No		No		INPUT
data_i[32]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[33]	No	No		No		INPUT
data_i[41:34]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[42]	No	No		No		INPUT
data_i[68:43]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[70:69]	No	No		No		INPUT
data_i[71]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_o[1:0]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[5:3]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[12:7]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[16:14]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[28:18]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[30]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[32]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[41:34]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[63:43]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	240	82.19
Total Bits 0->1	146	120	82.19
Total Bits 1->0	146	120	82.19

Ports	4	0	0.00
Port Bits	292	240	82.19
Port Bits 0->1	146	120	82.19
Port Bits 1->0	146	120	82.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[1]	No	No		No		INPUT
data_i[2]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[3]	No	No		No		INPUT
data_i[5:4]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[6]	No	No		No		INPUT
data_i[11:7]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[14:12]	No	No		No		INPUT
data_i[18:15]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[19]	No	No		No		INPUT
data_i[24:20]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_i[25]	No	No		No		INPUT
data_i[71:26]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[2]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[5:4]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[11:7]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[14:12]	No	No		No		OUTPUT
data_o[18:15]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[24:20]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[63:26]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	246	84.25
Total Bits 0->1	146	123	84.25
Total Bits 1->0	146	123	84.25

Ports	4	0	0.00
Port Bits	292	246	84.25
Port Bits 0->1	146	123	84.25
Port Bits 1->0	146	123	84.25

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[3:1]	No	No		No		INPUT
data_i[9:4]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[10]	No	No		No		INPUT
data_i[43:11]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[44]	No	No		No		INPUT
data_i[62:45]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[63]	No	No		No		INPUT
data_i[68:64]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[69]	No	No		No		INPUT
data_i[71:70]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[3:1]	No	No		No		OUTPUT
data_o[9:4]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[43:11]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[62:45]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	248	84.93
Total Bits 0->1	146	124	84.93
Total Bits 1->0	146	124	84.93

Ports	4	0	0.00
Port Bits	292	248	84.93
Port Bits 0->1	146	124	84.93
Port Bits 1->0	146	124	84.93

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[12:0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[13]	No	No		No		INPUT
data_i[30:14]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[31]	No	No		No		INPUT
data_i[32]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[33]	No	No		No		INPUT
data_i[42:34]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[43]	No	No		No		INPUT
data_i[66:44]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[68:67]	No	No		No		INPUT
data_i[69]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[71:70]	No	No		No		INPUT
data_o[12:0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[30:14]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[31]	No	No		No		OUTPUT
data_o[32]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[42:34]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[63:44]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	254	86.99
Total Bits 0->1	146	127	86.99
Total Bits 1->0	146	127	86.99

Ports	4	0	0.00
Port Bits	292	254	86.99
Port Bits 0->1	146	127	86.99
Port Bits 1->0	146	127	86.99

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[6:0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[7]	No	No		No		INPUT
data_i[18:8]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[19]	No	No		No		INPUT
data_i[45:20]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[46]	No	No		No		INPUT
data_i[49:47]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[50]	No	No		No		INPUT
data_i[70:51]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[71]	No	No		No		INPUT
data_o[6:0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[18:8]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[45:20]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[49:47]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[63:51]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	260	89.04
Total Bits 0->1	146	130	89.04
Total Bits 1->0	146	130	89.04

Ports	4	0	0.00
Port Bits	292	260	89.04
Port Bits 0->1	146	130	89.04
Port Bits 1->0	146	130	89.04

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[16:0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[17]	No	No		No		INPUT
data_i[47:18]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[48]	No	No		No		INPUT
data_i[66:49]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[67]	No	No		No		INPUT
data_i[70:68]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[71]	No	No		No		INPUT
data_o[16:0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[47:18]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[63:49]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	264	90.41
Total Bits 0->1	146	132	90.41
Total Bits 1->0	146	132	90.41

Ports	4	0	0.00
Port Bits	292	264	90.41
Port Bits 0->1	146	132	90.41
Port Bits 1->0	146	132	90.41

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[6:0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[7]	No	No		No		INPUT
data_i[49:8]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
data_i[50]	No	No		No		INPUT
data_i[71:51]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[6:0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[49:8]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[63:51]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	268	91.78
Total Bits 0->1	146	134	91.78
Total Bits 1->0	146	134	91.78

Ports	4	0	0.00
Port Bits	292	268	91.78
Port Bits 0->1	146	134	91.78
Port Bits 1->0	146	134	91.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[25:0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
data_i[26]	No	No		No		INPUT
data_i[71:27]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[25:0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[63:27]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	268	91.78
Total Bits 0->1	146	134	91.78
Total Bits 1->0	146	134	91.78

Ports	4	0	0.00
Port Bits	292	268	91.78
Port Bits 0->1	146	134	91.78
Port Bits 1->0	146	134	91.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[2:0]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_i[3]	No	No		No		INPUT
data_i[71:4]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[2:0]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
data_o[3]	No	No		No		OUTPUT
data_o[63:4]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	1	25.00
Total Bits	292	270	92.47
Total Bits 0->1	146	135	92.47
Total Bits 1->0	146	135	92.47

Ports	4	1	25.00
Port Bits	292	270	92.47
Port Bits 0->1	146	135	92.47
Port Bits 1->0	146	135	92.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[70:0]	Yes	Yes	*T20,*T22,*T34	Yes	T20,T22,T34	INPUT
data_i[71]	No	No		No		INPUT
data_o[63:0]	Yes	Yes	T20,T22,T34	Yes	T20,T22,T34	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T20,T22,T34	Yes	T20,T22,T34	INPUT
data_o[63:0]	Yes	Yes	T20,T22,T34	Yes	T20,T22,T34	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T21,T36,T42	Yes	T21,T49,T36	INPUT
data_o[63:0]	Yes	Yes	T21,T36,T42	Yes	T21,T49,T36	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	INPUT
data_o[63:0]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T42,T44,T89	Yes	T53,T92,T42	INPUT
data_o[63:0]	Yes	Yes	T42,T44,T89	Yes	T53,T92,T42	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	INPUT
data_o[63:0]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T42,T44,T50	Yes	T53,T92,T42	INPUT
data_o[63:0]	Yes	Yes	T42,T44,T50	Yes	T53,T92,T42	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T42,T44,T50	Yes	T54,T55,T42	INPUT
data_o[63:0]	Yes	Yes	T42,T44,T50	Yes	T54,T55,T42	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	INPUT
data_o[63:0]	Yes	Yes	T31,T33,T48	Yes	T31,T33,T48	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[63:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[63:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[63:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[63:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
data_o[63:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_o[63:0]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
data_o[63:0]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T42,T44,T50	Yes	T31,T33,T48	INPUT
data_o[63:0]	Yes	Yes	T42,T44,T50	Yes	T31,T33,T48	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T20,T22,T34	Yes	T20,T22,T34	INPUT
data_o[63:0]	Yes	Yes	T20,T22,T34	Yes	T20,T22,T34	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT