OTP_CTRL Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.820s	62.509us	1	1	100.00
V1	smoke	otp_ctrl_smoke	3.240s	138.839us	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	1.930s	64.059us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.530s	38.049us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	5.020s	225.479us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	2.740s	71.489us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	2.030s	65.579us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.530s	38.049us	20	20	100.00
		otp_ctrl_csr_aliasing	2.740s	71.489us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.340s	35.669us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.450s	35.669us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	16.470s	601.119us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	4.570s	156.689us	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	5.080s	190.889us	10	10	100.00
		otp_ctrl_check_fail	2.890s	111.269us	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	4.120s	137.469us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	11.180s	614.979us	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	8.110s	346.349us	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	12.850s	486.419us	50	50	100.00
		otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	12.000s	390.019us	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	20.310s	1.138ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	9.520s	549.639us	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	2.285m	13.240ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.430s	38.239us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	1.960s	71.069us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	3.230s	71.439us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	3.230s	71.439us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	1.930s	64.059us	5	5	100.00
		otp_ctrl_csr_rw	1.530s	38.049us	20	20	100.00
		otp_ctrl_csr_aliasing	2.740s	71.489us	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.120s	61.029us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	1.930s	64.059us	5	5	100.00
		otp_ctrl_csr_rw	1.530s	38.049us	20	20	100.00
		otp_ctrl_csr_aliasing	2.740s	71.489us	5	5	100.00
		otp_ctrl_same_csr_outstanding	2.120s	61.029us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
		otp_ctrl_tl_intg_err	10.040s	647.529us	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	10.040s	647.529us	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	3.240s	138.839us	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	3.240s	138.839us	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
		otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
		otp_ctrl_macro_errs	20.310s	1.138ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
		otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
		otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
		otp_ctrl_macro_errs	20.310s	1.138ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	4.770s	176.929us	200	200	100.00
		otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	4.570s	156.689us	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	2.890s	111.269us	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	11.180s	614.979us	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	11.180s	614.979us	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	11.180s	614.979us	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	11.180s	614.979us	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	11.180s	614.979us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	3.240s	138.839us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	11.180s	614.979us	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	3.240s	138.839us	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.513m	8.539ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	4.120s	137.469us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	3.240s	138.839us	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	3.240s	138.839us	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	20.310s	1.138ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.380s	5.946ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	33.436m	150.269ms	100	100	100.00
V3		TOTAL			101	101	100.00
		TOTAL			1343	1343	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
85.25	91.02	88.86	82.89	67.89	91.20	94.19	80.68

Past Results

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• 2023.10.23_18.21.27
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