Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	51	7	44	86.27

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	7	44	86.27	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49117	1			T2	51		T3	89		T8	337
access_err	82602	1			T1	4		T3	1		T8	1
write_blank_err	334	1			T90	1		T17	1		T121	1
ecc_uncorr_err	62631	1			T90	390		T107	31		T17	496
ecc_corr_err	1232	1			T89	60		T54	41		T107	13
no_err	375603	1			T1	18		T2	53		T3	90

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	43765	1			T3	180		T8	676		T4	26
secret2	61145	1			T1	6		T4	38		T5	72
secret1	89983	1			T1	4		T4	32		T5	464
secret0	110641	1			T1	2		T4	12		T5	46
hw_cfg	67960	1			T1	4		T2	104		T4	30
owner_sw_cfg	63853	1			T4	10		T5	118		T6	136
creator_sw_cfg	61015	1			T1	4		T4	28		T5	62
vendor_test	73157	1			T1	2		T8	2		T4	22

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	7	44	86.27	7
Automatically Generated Cross Bins	51	7	44	86.27	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	1893	1			T3	89		T8	337		T294	37
fsm_err	secret2	3517	1			T87	100		T295	4		T296	302
fsm_err	secret1	8302	1			T5	204		T297	168		T103	160
fsm_err	secret0	8344	1			T275	86		T298	91		T299	86
fsm_err	hw_cfg	7158	1			T2	51		T75	485		T86	107
fsm_err	owner_sw_cfg	3638	1			T17	14		T151	332		T124	59
fsm_err	creator_sw_cfg	2631	1			T107	5		T124	60		T119	12
fsm_err	vendor_test	13634	1			T88	339		T172	104		T174	349
access_err	lc_or_oob	19986	1			T3	1		T8	1		T4	13
access_err	secret2	13463	1			T1	3		T4	13		T5	1
access_err	secret1	7088	1			T5	1		T6	57		T75	9
access_err	secret0	5702	1			T4	2		T6	23		T75	2
access_err	hw_cfg	3249	1			T6	37		T75	2		T89	16
access_err	owner_sw_cfg	12271	1			T4	1		T5	22		T6	57
access_err	creator_sw_cfg	12494	1			T1	1		T4	5		T5	4
access_err	vendor_test	8349	1			T4	3		T5	12		T6	49
write_blank_err	secret2	15	1			T300	1		T301	1		T302	1
write_blank_err	secret1	43	1			T90	1		T303	1		T19	1
write_blank_err	secret0	81	1			T17	1		T121	1		T127	1
write_blank_err	hw_cfg	22	1			T256	1		T171	1		T206	1
write_blank_err	owner_sw_cfg	72	1			T276	2		T19	3		T155	2
write_blank_err	creator_sw_cfg	72	1			T276	1		T256	3		T171	2
write_blank_err	vendor_test	29	1			T304	1		T155	2		T305	1
ecc_uncorr_err	secret2	5842	1			T118	29		T120	49		T162	35
ecc_uncorr_err	secret1	16743	1			T90	390		T123	15		T125	16
ecc_uncorr_err	secret0	29357	1			T17	496		T118	51		T124	117
ecc_uncorr_err	hw_cfg	6619	1			T107	31		T123	51		T125	19
ecc_uncorr_err	owner_sw_cfg	1945	1			T118	24		T124	60		T125	48
ecc_uncorr_err	creator_sw_cfg	2125	1			T123	26		T125	15		T119	17
ecc_corr_err	secret2	126	1			T89	6		T54	5		T107	2
ecc_corr_err	secret1	153	1			T89	11		T54	1		T118	2
ecc_corr_err	secret0	169	1			T89	5		T54	8		T118	2
ecc_corr_err	hw_cfg	275	1			T89	17		T54	6		T107	5
ecc_corr_err	owner_sw_cfg	154	1			T89	10		T54	4		T107	4
ecc_corr_err	creator_sw_cfg	175	1			T89	6		T54	7		T107	1
ecc_corr_err	vendor_test	180	1			T89	5		T54	10		T107	1
no_err	lc_or_oob	21886	1			T3	90		T8	338		T4	13
no_err	secret2	38182	1			T1	3		T4	25		T5	71
no_err	secret1	57654	1			T1	4		T4	32		T5	259
no_err	secret0	66988	1			T1	2		T4	10		T5	46
no_err	hw_cfg	50637	1			T1	4		T2	53		T4	30
no_err	owner_sw_cfg	45773	1			T4	9		T5	96		T6	79
no_err	creator_sw_cfg	43518	1			T1	3		T4	23		T5	58
no_err	vendor_test	50965	1			T1	2		T8	2		T4	19

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded