Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.63 92.61 91.57 92.42 93.52 93.49 96.53 95.27


Total tests in report: 1333
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.45 40.45 68.29 68.29 57.14 57.14 30.59 30.59 0.00 0.00 65.08 65.08 43.97 43.97 18.06 18.06 /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3691974942
67.71 27.26 85.78 17.49 69.25 12.11 35.49 4.90 93.52 93.52 78.77 13.69 87.78 43.82 23.38 5.32 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3851709068
76.89 9.18 86.09 0.30 71.66 2.42 78.08 42.59 93.52 0.00 80.32 1.55 88.99 1.21 39.58 16.20 /workspace/coverage/default/38.otp_ctrl_stress_all.1956118382
85.60 8.71 90.33 4.24 83.22 11.56 86.42 8.35 93.52 0.00 88.77 8.45 90.87 1.89 66.08 26.50 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1059467200
86.95 1.35 90.37 0.04 85.48 2.25 86.53 0.11 93.52 0.00 88.93 0.16 91.33 0.45 72.49 6.41 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3181524621
87.75 0.80 90.37 0.00 86.02 0.54 88.16 1.63 93.52 0.00 89.25 0.32 91.63 0.30 75.27 2.78 /workspace/coverage/default/39.otp_ctrl_stress_all.3678465898
88.47 0.73 90.52 0.15 86.59 0.57 88.55 0.39 93.52 0.00 90.64 1.39 93.89 2.26 75.61 0.34 /workspace/coverage/default/1.otp_ctrl_sec_cm.306301821
89.01 0.54 90.65 0.13 87.05 0.46 88.57 0.01 93.52 0.00 90.86 0.21 93.89 0.00 78.57 2.95 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.2126695833
89.52 0.50 90.65 0.00 87.05 0.00 90.23 1.67 93.52 0.00 90.86 0.00 93.89 0.00 80.42 1.86 /workspace/coverage/default/22.otp_ctrl_stress_all.792385166
89.99 0.47 90.65 0.00 87.08 0.03 90.23 0.00 93.52 0.00 90.86 0.00 93.89 0.00 83.71 3.29 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.4108100112
90.40 0.41 90.65 0.00 87.16 0.08 90.63 0.40 93.52 0.00 90.91 0.05 93.97 0.08 85.99 2.28 /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.3283609163
90.72 0.31 90.76 0.11 87.76 0.60 90.63 0.00 93.52 0.00 91.12 0.21 94.04 0.08 87.17 1.18 /workspace/coverage/default/43.otp_ctrl_macro_errs.3685672363
90.99 0.28 90.76 0.00 87.95 0.19 90.63 0.00 93.52 0.00 91.12 0.00 95.63 1.58 87.34 0.17 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1010124940
91.25 0.26 90.76 0.00 88.22 0.27 90.81 0.17 93.52 0.00 91.12 0.00 95.63 0.00 88.69 1.35 /workspace/coverage/default/8.otp_ctrl_stress_all.2341290772
91.42 0.17 90.93 0.17 88.38 0.16 90.89 0.08 93.52 0.00 91.44 0.32 95.85 0.23 88.95 0.25 /workspace/coverage/default/126.otp_ctrl_init_fail.2345716109
91.58 0.15 90.93 0.00 88.41 0.03 91.27 0.38 93.52 0.00 91.44 0.00 95.85 0.00 89.62 0.68 /workspace/coverage/default/43.otp_ctrl_stress_all.2835155810
91.72 0.14 90.93 0.00 88.87 0.46 91.56 0.30 93.52 0.00 91.60 0.16 95.85 0.00 89.70 0.08 /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.2041394977
91.85 0.13 90.95 0.02 89.31 0.43 91.56 0.00 93.52 0.00 91.66 0.05 95.85 0.00 90.13 0.42 /workspace/coverage/default/1.otp_ctrl_check_fail.2122536179
91.97 0.11 91.08 0.13 89.58 0.27 91.56 0.00 93.52 0.00 91.87 0.21 95.93 0.08 90.21 0.08 /workspace/coverage/default/277.otp_ctrl_init_fail.3075135093
92.07 0.11 91.33 0.25 89.82 0.24 91.56 0.00 93.52 0.00 91.87 0.00 95.93 0.00 90.46 0.25 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1765459191
92.18 0.10 91.43 0.09 89.96 0.14 91.56 0.00 93.52 0.00 92.03 0.16 95.93 0.00 90.80 0.34 /workspace/coverage/default/36.otp_ctrl_check_fail.45288275
92.25 0.07 91.50 0.08 90.04 0.08 91.68 0.12 93.52 0.00 92.19 0.16 95.93 0.00 90.89 0.08 /workspace/coverage/default/72.otp_ctrl_init_fail.597011469
92.32 0.07 91.50 0.00 90.04 0.00 91.68 0.00 93.52 0.00 92.19 0.00 95.93 0.00 91.39 0.51 /workspace/coverage/default/26.otp_ctrl_regwen.204782567
92.39 0.07 91.58 0.08 90.09 0.05 91.68 0.00 93.52 0.00 92.30 0.11 96.00 0.08 91.56 0.17 /workspace/coverage/default/32.otp_ctrl_macro_errs.272627188
92.46 0.06 91.58 0.00 90.15 0.05 91.68 0.00 93.52 0.00 92.30 0.00 96.23 0.23 91.73 0.17 /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.2745942949
92.52 0.06 91.65 0.08 90.23 0.08 91.68 0.00 93.52 0.00 92.41 0.11 96.23 0.00 91.90 0.17 /workspace/coverage/default/18.otp_ctrl_check_fail.2418101172
92.58 0.06 91.99 0.34 90.23 0.00 91.68 0.00 93.52 0.00 92.41 0.00 96.23 0.00 91.98 0.08 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3045695245
92.64 0.06 92.07 0.08 90.31 0.08 91.68 0.00 93.52 0.00 92.57 0.16 96.23 0.00 92.07 0.08 /workspace/coverage/default/121.otp_ctrl_init_fail.3569766373
92.69 0.05 92.09 0.02 90.34 0.03 91.68 0.00 93.52 0.00 92.57 0.00 96.23 0.00 92.41 0.34 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3461495742
92.74 0.05 92.09 0.00 90.34 0.00 91.68 0.00 93.52 0.00 92.57 0.00 96.23 0.00 92.74 0.34 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3327590755
92.79 0.05 92.09 0.00 90.34 0.00 91.68 0.00 93.52 0.00 92.57 0.00 96.23 0.00 93.08 0.34 /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.3536448382
92.83 0.05 92.16 0.08 90.36 0.03 91.70 0.02 93.52 0.00 92.67 0.11 96.23 0.00 93.16 0.08 /workspace/coverage/default/124.otp_ctrl_init_fail.138711584
92.87 0.04 92.22 0.06 90.39 0.03 91.78 0.08 93.52 0.00 92.73 0.05 96.23 0.00 93.25 0.08 /workspace/coverage/default/286.otp_ctrl_init_fail.30369521
92.91 0.04 92.22 0.00 90.66 0.27 91.79 0.01 93.52 0.00 92.73 0.00 96.23 0.00 93.25 0.00 /workspace/coverage/default/0.otp_ctrl_alert_test.1773211628
92.95 0.04 92.28 0.06 90.69 0.03 91.83 0.04 93.52 0.00 92.78 0.05 96.23 0.00 93.33 0.08 /workspace/coverage/default/156.otp_ctrl_init_fail.3190983009
92.99 0.04 92.28 0.00 90.69 0.00 91.83 0.00 93.52 0.00 92.78 0.00 96.23 0.00 93.59 0.25 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3202768621
93.02 0.04 92.33 0.06 90.72 0.03 91.86 0.03 93.52 0.00 92.83 0.05 96.23 0.00 93.67 0.08 /workspace/coverage/default/57.otp_ctrl_init_fail.1390117426
93.06 0.03 92.33 0.00 90.77 0.05 91.88 0.02 93.52 0.00 92.83 0.00 96.23 0.00 93.84 0.17 /workspace/coverage/default/29.otp_ctrl_stress_all.690064156
93.09 0.03 92.33 0.00 90.77 0.00 91.88 0.00 93.52 0.00 92.83 0.00 96.46 0.23 93.84 0.00 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3552415244
93.12 0.03 92.39 0.06 90.80 0.03 91.88 0.00 93.52 0.00 92.89 0.05 96.46 0.00 93.92 0.08 /workspace/coverage/default/142.otp_ctrl_init_fail.714384625
93.15 0.03 92.45 0.06 90.83 0.03 91.88 0.00 93.52 0.00 92.94 0.05 96.46 0.00 94.01 0.08 /workspace/coverage/default/8.otp_ctrl_check_fail.878913766
93.18 0.03 92.47 0.02 90.88 0.05 91.88 0.00 93.52 0.00 92.99 0.05 96.46 0.00 94.09 0.08 /workspace/coverage/default/31.otp_ctrl_check_fail.1879464593
93.21 0.03 92.47 0.00 90.88 0.00 91.98 0.11 93.52 0.00 92.99 0.00 96.46 0.00 94.18 0.08 /workspace/coverage/default/2.otp_ctrl_stress_all.2140266785
93.24 0.02 92.50 0.04 90.96 0.08 91.98 0.00 93.52 0.00 93.05 0.05 96.46 0.00 94.18 0.00 /workspace/coverage/default/88.otp_ctrl_init_fail.1626682257
93.26 0.02 92.50 0.00 90.96 0.00 91.98 0.00 93.52 0.00 93.05 0.00 96.46 0.00 94.35 0.17 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3610743793
93.28 0.02 92.50 0.00 90.96 0.00 91.98 0.00 93.52 0.00 93.05 0.00 96.46 0.00 94.51 0.17 /workspace/coverage/default/0.otp_ctrl_regwen.1245087623
93.31 0.02 92.50 0.00 90.96 0.00 91.98 0.00 93.52 0.00 93.05 0.00 96.46 0.00 94.68 0.17 /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.531470783
93.33 0.02 92.56 0.06 91.02 0.05 91.98 0.00 93.52 0.00 93.10 0.05 96.46 0.00 94.68 0.00 /workspace/coverage/default/38.otp_ctrl_check_fail.2967433784
93.35 0.02 92.66 0.09 91.02 0.00 91.98 0.00 93.52 0.00 93.16 0.05 96.46 0.00 94.68 0.00 /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.976942614
93.37 0.02 92.66 0.00 91.07 0.05 91.98 0.00 93.52 0.00 93.16 0.00 96.46 0.00 94.77 0.08 /workspace/coverage/default/27.otp_ctrl_stress_all.2287628631
93.39 0.02 92.71 0.06 91.10 0.03 91.98 0.00 93.52 0.00 93.21 0.05 96.46 0.00 94.77 0.00 /workspace/coverage/default/298.otp_ctrl_init_fail.3945239936
93.41 0.02 92.77 0.06 91.12 0.03 91.98 0.00 93.52 0.00 93.26 0.05 96.46 0.00 94.77 0.00 /workspace/coverage/default/40.otp_ctrl_check_fail.4140008393
93.43 0.02 92.81 0.04 91.15 0.03 92.00 0.01 93.52 0.00 93.32 0.05 96.46 0.00 94.77 0.00 /workspace/coverage/default/117.otp_ctrl_init_fail.1617747583
93.45 0.02 92.81 0.00 91.18 0.03 92.01 0.01 93.52 0.00 93.32 0.00 96.46 0.00 94.85 0.08 /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1001259188
93.46 0.02 92.84 0.04 91.21 0.03 92.01 0.00 93.52 0.00 93.37 0.05 96.46 0.00 94.85 0.00 /workspace/coverage/default/102.otp_ctrl_init_fail.109854745
93.48 0.02 92.88 0.04 91.23 0.03 92.01 0.00 93.52 0.00 93.42 0.05 96.46 0.00 94.85 0.00 /workspace/coverage/default/161.otp_ctrl_init_fail.473873899
93.50 0.02 92.88 0.00 91.34 0.11 92.01 0.00 93.52 0.00 93.42 0.00 96.46 0.00 94.85 0.00 /workspace/coverage/default/44.otp_ctrl_stress_all.4164145457
93.51 0.02 92.88 0.00 91.34 0.00 92.03 0.02 93.52 0.00 93.42 0.00 96.46 0.00 94.94 0.08 /workspace/coverage/default/25.otp_ctrl_regwen.3112384951
93.53 0.01 92.90 0.02 91.34 0.00 92.03 0.00 93.52 0.00 93.42 0.00 96.46 0.00 95.02 0.08 /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.4056916061
93.54 0.01 92.90 0.00 91.34 0.00 92.04 0.01 93.52 0.00 93.42 0.00 96.46 0.00 95.11 0.08 /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.3665225405
93.55 0.01 92.90 0.00 91.34 0.00 92.04 0.00 93.52 0.00 93.42 0.00 96.46 0.00 95.19 0.08 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3132325885
93.56 0.01 92.90 0.00 91.34 0.00 92.04 0.00 93.52 0.00 93.42 0.00 96.46 0.00 95.27 0.08 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.853022918
93.58 0.01 92.90 0.00 91.34 0.00 92.04 0.00 93.52 0.00 93.42 0.00 96.53 0.08 95.27 0.00 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3338995483
93.58 0.01 92.90 0.00 91.34 0.00 92.09 0.06 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/0.otp_ctrl_init_fail.389763605
93.59 0.01 92.90 0.00 91.34 0.00 92.15 0.06 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/210.otp_ctrl_init_fail.2038104568
93.60 0.01 92.90 0.00 91.34 0.00 92.21 0.06 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/213.otp_ctrl_init_fail.193374250
93.61 0.01 92.90 0.00 91.40 0.05 92.21 0.00 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3887751226
93.61 0.01 92.90 0.00 91.40 0.00 92.25 0.04 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/29.otp_ctrl_init_fail.1862672775
93.62 0.01 92.90 0.00 91.40 0.00 92.28 0.04 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/182.otp_ctrl_init_fail.3898790351
93.62 0.01 92.90 0.00 91.40 0.00 92.31 0.03 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/299.otp_ctrl_init_fail.3622367038
93.63 0.01 92.90 0.00 91.40 0.00 92.34 0.03 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/40.otp_ctrl_init_fail.111871930
93.63 0.01 92.90 0.00 91.42 0.03 92.34 0.00 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/14.otp_ctrl_check_fail.3349928831
93.63 0.01 92.90 0.00 91.45 0.03 92.34 0.00 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/24.otp_ctrl_stress_all.3608793185
93.64 0.01 92.92 0.02 91.45 0.00 92.34 0.00 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/23.otp_ctrl_stress_all.1445102350
93.64 0.01 92.94 0.02 91.45 0.00 92.34 0.00 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/3.otp_ctrl_test_access.558059503
93.64 0.01 92.94 0.00 91.45 0.00 92.35 0.01 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/245.otp_ctrl_init_fail.956134482
93.64 0.01 92.94 0.00 91.45 0.00 92.37 0.01 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/249.otp_ctrl_init_fail.1291143501
93.65 0.01 92.94 0.00 91.45 0.00 92.38 0.01 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/255.otp_ctrl_init_fail.629119416
93.65 0.01 92.94 0.00 91.45 0.00 92.40 0.01 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/8.otp_ctrl_init_fail.1202585441
93.65 0.01 92.94 0.00 91.45 0.00 92.40 0.01 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/0.otp_ctrl_stress_all.3289872449
93.65 0.01 92.94 0.00 91.45 0.00 92.41 0.01 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/14.otp_ctrl_init_fail.2609410718
93.65 0.01 92.94 0.00 91.45 0.00 92.42 0.01 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/207.otp_ctrl_init_fail.2453498156
93.65 0.01 92.94 0.00 91.45 0.00 92.42 0.01 93.52 0.00 93.42 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/10.otp_ctrl_check_fail.290927504

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3330794839
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2690342422
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.674066766
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.316312482
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3516587311
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2101910800
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2751788610
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.4042661317
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1969626308
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2328122342
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3362557512
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1598563882
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3669341593
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1914603118
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1438147196
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.66792347
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.739061404
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.4124058185
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.578953794
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.395427862
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.595844131
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1902383975
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1433255742
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1443663679
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3965468152
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1974865909
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1730926861
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3767874009
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4251698629
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.662853048
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1408838697
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.955545506
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2687598088
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2555226596
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2976134510
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.265581730
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.4065042814
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3124919747
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2323367022
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3585543081
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1196199912
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.163513328
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1921719942
/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2760963155
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.323488262
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3225867261
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.4012389274
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2904258100
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3956957314
/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2454845798
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1440338891
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.805091640
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/workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.4098391888
/workspace/coverage/default/92.otp_ctrl_init_fail.3501802410
/workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.1339878774
/workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1928462404
/workspace/coverage/default/93.otp_ctrl_init_fail.784840132
/workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.402415389
/workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1853745040
/workspace/coverage/default/94.otp_ctrl_init_fail.453079780
/workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.217548120
/workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2314785463
/workspace/coverage/default/95.otp_ctrl_init_fail.2040479875
/workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.3519286628
/workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.3339965469
/workspace/coverage/default/96.otp_ctrl_init_fail.3006543955
/workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.604296654
/workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.400711292
/workspace/coverage/default/97.otp_ctrl_init_fail.2799935411
/workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.2346842558
/workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3418225073
/workspace/coverage/default/98.otp_ctrl_init_fail.2438339149
/workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.4108127505
/workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1372198599
/workspace/coverage/default/99.otp_ctrl_init_fail.3212548891
/workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.355251171



Total test records in report: 1333
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T21 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3851709068 Dec 24 01:52:48 PM PST 23 Dec 24 01:52:58 PM PST 23 68466984 ps
T108 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3330794839 Dec 24 01:53:00 PM PST 23 Dec 24 01:53:12 PM PST 23 160310026 ps
T109 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1010124940 Dec 24 01:52:49 PM PST 23 Dec 24 01:53:03 PM PST 23 82356290 ps
T110 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.473184412 Dec 24 01:52:48 PM PST 23 Dec 24 01:53:00 PM PST 23 276955091 ps
T114 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1059467200 Dec 24 01:53:20 PM PST 23 Dec 24 01:53:47 PM PST 23 1350002370 ps
T175 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1975377898 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:27 PM PST 23 96987401 ps
T111 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3293142121 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:21 PM PST 23 516665067 ps
T112 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2760963155 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:30 PM PST 23 50886616 ps
T115 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.183808296 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:27 PM PST 23 98709992 ps
T176 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1045410713 Dec 24 01:52:49 PM PST 23 Dec 24 01:53:00 PM PST 23 137044857 ps
T204 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.805091640 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:46 PM PST 23 1751649945 ps
T205 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3887751226 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:28 PM PST 23 1292890491 ps
T113 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.712837479 Dec 24 01:52:57 PM PST 23 Dec 24 01:53:11 PM PST 23 42245808 ps
T177 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2555226596 Dec 24 01:53:20 PM PST 23 Dec 24 01:53:33 PM PST 23 100797203 ps
T178 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1433255742 Dec 24 01:53:02 PM PST 23 Dec 24 01:53:17 PM PST 23 762567707 ps
T187 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.964608824 Dec 24 01:53:13 PM PST 23 Dec 24 01:53:20 PM PST 23 68570189 ps
T188 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3322414407 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:14 PM PST 23 147428716 ps
T189 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.2126695833 Dec 24 01:53:13 PM PST 23 Dec 24 01:53:20 PM PST 23 86728557 ps
T179 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3181524621 Dec 24 01:52:57 PM PST 23 Dec 24 01:53:13 PM PST 23 153542985 ps
T190 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2475869540 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:27 PM PST 23 42649406 ps
T180 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3965468152 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:30 PM PST 23 1083703115 ps
T191 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.240067859 Dec 24 01:52:59 PM PST 23 Dec 24 01:53:11 PM PST 23 164012448 ps
T181 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1709542575 Dec 24 01:53:24 PM PST 23 Dec 24 01:53:34 PM PST 23 126985024 ps
T229 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3767874009 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:29 PM PST 23 239030747 ps
T228 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.4108100112 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:37 PM PST 23 18904696229 ps
T182 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.4079284383 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:15 PM PST 23 199573266 ps
T233 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2932363579 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:28 PM PST 23 128038167 ps
T230 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2904258100 Dec 24 01:53:22 PM PST 23 Dec 24 01:53:33 PM PST 23 579620120 ps
T257 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3362557512 Dec 24 01:53:13 PM PST 23 Dec 24 01:53:22 PM PST 23 315172728 ps
T231 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3610743793 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:29 PM PST 23 1204958979 ps
T116 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3435522502 Dec 24 01:52:58 PM PST 23 Dec 24 01:53:11 PM PST 23 69295207 ps
T234 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3552415244 Dec 24 01:53:00 PM PST 23 Dec 24 01:53:11 PM PST 23 37926258 ps
T250 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1412626770 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 38214610 ps
T251 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1680970271 Dec 24 01:53:10 PM PST 23 Dec 24 01:53:19 PM PST 23 546270973 ps
T183 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3461495742 Dec 24 01:53:20 PM PST 23 Dec 24 01:53:33 PM PST 23 370992914 ps
T235 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2410280395 Dec 24 01:52:50 PM PST 23 Dec 24 01:53:04 PM PST 23 1121934278 ps
T184 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.163513328 Dec 24 01:53:21 PM PST 23 Dec 24 01:53:34 PM PST 23 95533934 ps
T252 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.283275962 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:29 PM PST 23 72593932 ps
T185 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3397836231 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:16 PM PST 23 70303734 ps
T253 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2961879915 Dec 24 01:53:16 PM PST 23 Dec 24 01:53:26 PM PST 23 404474218 ps
T259 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3830361136 Dec 24 01:53:02 PM PST 23 Dec 24 01:53:15 PM PST 23 43931688 ps
T232 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1085765876 Dec 24 01:53:03 PM PST 23 Dec 24 01:53:51 PM PST 23 19083347795 ps
T186 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.316312482 Dec 24 01:53:12 PM PST 23 Dec 24 01:53:21 PM PST 23 104354721 ps
T226 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3078804595 Dec 24 01:53:04 PM PST 23 Dec 24 01:53:21 PM PST 23 641994413 ps
T261 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2976134510 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:49 PM PST 23 1811750967 ps
T308 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3132325885 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:59 PM PST 23 18495298613 ps
T236 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2328122342 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:23 PM PST 23 297015844 ps
T225 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.4128020706 Dec 24 01:52:50 PM PST 23 Dec 24 01:53:06 PM PST 23 256786530 ps
T237 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2323367022 Dec 24 01:53:24 PM PST 23 Dec 24 01:53:35 PM PST 23 306372828 ps
T224 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1440338891 Dec 24 01:53:22 PM PST 23 Dec 24 01:53:37 PM PST 23 175202117 ps
T227 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1765459191 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:26 PM PST 23 2287604856 ps
T350 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3225867261 Dec 24 01:53:20 PM PST 23 Dec 24 01:53:36 PM PST 23 2395016649 ps
T351 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.261712586 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:21 PM PST 23 223597049 ps
T306 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3124919747 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 48541379 ps
T260 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2594598182 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:13 PM PST 23 213135187 ps
T238 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.442551941 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:30 PM PST 23 219381403 ps
T239 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1408838697 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:30 PM PST 23 68737615 ps
T352 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3327590755 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 60392849 ps
T353 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.992654784 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 73433446 ps
T354 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.825822419 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:26 PM PST 23 57735822 ps
T355 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.853022918 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:29 PM PST 23 41394979 ps
T240 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2454845798 Dec 24 01:53:20 PM PST 23 Dec 24 01:53:32 PM PST 23 916202970 ps
T241 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3338995483 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 38345436 ps
T356 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3811826400 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:27 PM PST 23 81413362 ps
T357 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3364581694 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:28 PM PST 23 531276705 ps
T358 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3953544876 Dec 24 01:52:57 PM PST 23 Dec 24 01:53:11 PM PST 23 77215583 ps
T359 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.540544376 Dec 24 01:52:47 PM PST 23 Dec 24 01:52:57 PM PST 23 140304312 ps
T360 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.78324826 Dec 24 01:53:16 PM PST 23 Dec 24 01:53:23 PM PST 23 36704853 ps
T242 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3938531537 Dec 24 01:53:12 PM PST 23 Dec 24 01:53:19 PM PST 23 38926343 ps
T361 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1324002690 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 78378093 ps
T362 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1298336875 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:32 PM PST 23 284990884 ps
T243 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1634408991 Dec 24 01:52:50 PM PST 23 Dec 24 01:53:04 PM PST 23 234757819 ps
T244 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2021644477 Dec 24 01:52:48 PM PST 23 Dec 24 01:52:58 PM PST 23 142380504 ps
T311 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2733213731 Dec 24 01:52:47 PM PST 23 Dec 24 01:53:13 PM PST 23 9361589130 ps
T363 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3027587420 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 47443512 ps
T364 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3956957314 Dec 24 01:53:16 PM PST 23 Dec 24 01:53:24 PM PST 23 72938673 ps
T312 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1281324520 Dec 24 01:52:50 PM PST 23 Dec 24 01:53:11 PM PST 23 1015540648 ps
T245 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.4065042814 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:21 PM PST 23 38830153 ps
T262 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3777229094 Dec 24 01:53:00 PM PST 23 Dec 24 01:53:14 PM PST 23 399152126 ps
T266 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.605632021 Dec 24 01:52:59 PM PST 23 Dec 24 01:53:15 PM PST 23 506957704 ps
T365 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.231167241 Dec 24 01:52:53 PM PST 23 Dec 24 01:53:03 PM PST 23 36777372 ps
T246 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3314343032 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:13 PM PST 23 38827434 ps
T366 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.4012389274 Dec 24 01:53:21 PM PST 23 Dec 24 01:53:34 PM PST 23 1114825024 ps
T117 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.97563067 Dec 24 01:52:48 PM PST 23 Dec 24 01:52:57 PM PST 23 290413379 ps
T267 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2690342422 Dec 24 01:52:51 PM PST 23 Dec 24 01:53:10 PM PST 23 518019283 ps
T268 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.595844131 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:30 PM PST 23 36894954 ps
T269 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2350454890 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:21 PM PST 23 42124657 ps
T270 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.963573848 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:30 PM PST 23 75298153 ps
T247 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1921719942 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 153094275 ps
T271 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.265581730 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:21 PM PST 23 92057314 ps
T272 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.4034678651 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:30 PM PST 23 142173608 ps
T367 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3967926836 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:23 PM PST 23 182647604 ps
T368 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2687598088 Dec 24 01:53:21 PM PST 23 Dec 24 01:53:32 PM PST 23 42754758 ps
T248 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1974865909 Dec 24 01:53:26 PM PST 23 Dec 24 01:53:35 PM PST 23 580679233 ps
T369 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1674245055 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:29 PM PST 23 55324348 ps
T370 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1677637843 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:26 PM PST 23 37640661 ps
T371 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3669341593 Dec 24 01:52:52 PM PST 23 Dec 24 01:53:05 PM PST 23 235919441 ps
T372 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1730926861 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:26 PM PST 23 142970398 ps
T249 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.760447633 Dec 24 01:53:20 PM PST 23 Dec 24 01:53:31 PM PST 23 38919689 ps
T373 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3958133918 Dec 24 01:53:20 PM PST 23 Dec 24 01:53:31 PM PST 23 553105845 ps
T292 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.578953794 Dec 24 01:53:02 PM PST 23 Dec 24 01:53:18 PM PST 23 1488929181 ps
T374 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2347256243 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:43 PM PST 23 9714536143 ps
T307 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.29782729 Dec 24 01:52:59 PM PST 23 Dec 24 01:53:34 PM PST 23 2980983297 ps
T309 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3202768621 Dec 24 01:52:57 PM PST 23 Dec 24 01:53:28 PM PST 23 3512842644 ps
T375 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1438147196 Dec 24 01:53:02 PM PST 23 Dec 24 01:53:14 PM PST 23 38476990 ps
T376 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1196199912 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:30 PM PST 23 904866866 ps
T377 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2540132658 Dec 24 01:52:47 PM PST 23 Dec 24 01:53:04 PM PST 23 4350612416 ps
T378 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.705596429 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:21 PM PST 23 54229859 ps
T379 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.904070752 Dec 24 01:53:11 PM PST 23 Dec 24 01:53:19 PM PST 23 41315952 ps
T380 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.4124058185 Dec 24 01:52:46 PM PST 23 Dec 24 01:52:52 PM PST 23 179650095 ps
T381 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2353935215 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:13 PM PST 23 129667054 ps
T382 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2751788610 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:22 PM PST 23 509403279 ps
T383 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.340168526 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:13 PM PST 23 83510019 ps
T384 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1528581650 Dec 24 01:53:13 PM PST 23 Dec 24 01:53:19 PM PST 23 39634241 ps
T385 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.74981745 Dec 24 01:53:13 PM PST 23 Dec 24 01:53:19 PM PST 23 38422639 ps
T386 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1504214643 Dec 24 01:53:22 PM PST 23 Dec 24 01:53:41 PM PST 23 2266415815 ps
T263 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1902383975 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:30 PM PST 23 246957078 ps
T387 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1316010194 Dec 24 01:53:13 PM PST 23 Dec 24 01:53:23 PM PST 23 1013362145 ps
T388 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.97074632 Dec 24 01:53:16 PM PST 23 Dec 24 01:53:23 PM PST 23 142448596 ps
T389 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.793179826 Dec 24 01:52:45 PM PST 23 Dec 24 01:52:47 PM PST 23 54841217 ps
T390 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3876843770 Dec 24 01:53:12 PM PST 23 Dec 24 01:53:34 PM PST 23 1223244110 ps
T391 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.955545506 Dec 24 01:53:27 PM PST 23 Dec 24 01:53:35 PM PST 23 64884041 ps
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