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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.63 92.61 91.57 92.42 93.52 93.49 96.53 95.27


Total test records in report: 1333
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T1254 /workspace/coverage/default/71.otp_ctrl_init_fail.401588369 Dec 24 02:08:31 PM PST 23 Dec 24 02:08:50 PM PST 23 114521521 ps
T1255 /workspace/coverage/default/22.otp_ctrl_parallel_key_req.3231357238 Dec 24 02:07:01 PM PST 23 Dec 24 02:07:29 PM PST 23 1996565104 ps
T1256 /workspace/coverage/default/1.otp_ctrl_background_chks.1188993451 Dec 24 02:06:02 PM PST 23 Dec 24 02:06:24 PM PST 23 6828328890 ps
T1257 /workspace/coverage/default/17.otp_ctrl_init_fail.3711122503 Dec 24 02:06:58 PM PST 23 Dec 24 02:07:10 PM PST 23 256038576 ps
T1258 /workspace/coverage/default/245.otp_ctrl_init_fail.956134482 Dec 24 02:09:21 PM PST 23 Dec 24 02:09:37 PM PST 23 280948255 ps
T1259 /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2287177505 Dec 24 02:06:30 PM PST 23 Dec 24 02:06:51 PM PST 23 9257428105 ps
T1260 /workspace/coverage/default/3.otp_ctrl_init_fail.2325954732 Dec 24 02:06:19 PM PST 23 Dec 24 02:06:29 PM PST 23 200631993 ps
T1261 /workspace/coverage/default/35.otp_ctrl_stress_all.264032021 Dec 24 02:07:41 PM PST 23 Dec 24 02:08:15 PM PST 23 1424740687 ps
T1262 /workspace/coverage/default/27.otp_ctrl_smoke.1197758924 Dec 24 02:07:06 PM PST 23 Dec 24 02:07:23 PM PST 23 3262105772 ps
T1263 /workspace/coverage/default/15.otp_ctrl_dai_errs.2601394086 Dec 24 02:06:58 PM PST 23 Dec 24 02:07:13 PM PST 23 325394756 ps
T1264 /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.2354679403 Dec 24 02:08:39 PM PST 23 Dec 24 02:08:58 PM PST 23 646201279 ps
T1265 /workspace/coverage/default/33.otp_ctrl_stress_all.3104820517 Dec 24 02:08:14 PM PST 23 Dec 24 02:09:50 PM PST 23 3894811404 ps
T1266 /workspace/coverage/default/100.otp_ctrl_init_fail.2001760420 Dec 24 02:08:38 PM PST 23 Dec 24 02:08:57 PM PST 23 473698754 ps
T1267 /workspace/coverage/default/8.otp_ctrl_regwen.529984908 Dec 24 02:06:47 PM PST 23 Dec 24 02:07:00 PM PST 23 202090108 ps
T1268 /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.1919772386 Dec 24 02:08:33 PM PST 23 Dec 24 03:25:04 PM PST 23 5093001590398 ps
T1269 /workspace/coverage/default/106.otp_ctrl_init_fail.2895699299 Dec 24 02:08:40 PM PST 23 Dec 24 02:08:59 PM PST 23 217845022 ps
T1270 /workspace/coverage/default/12.otp_ctrl_dai_lock.136586538 Dec 24 02:06:42 PM PST 23 Dec 24 02:06:51 PM PST 23 346700505 ps
T1271 /workspace/coverage/default/7.otp_ctrl_parallel_key_req.2332618920 Dec 24 02:06:57 PM PST 23 Dec 24 02:07:15 PM PST 23 7643664028 ps
T1272 /workspace/coverage/default/6.otp_ctrl_stress_all.1629095793 Dec 24 02:06:45 PM PST 23 Dec 24 02:07:56 PM PST 23 35355136750 ps
T1273 /workspace/coverage/default/177.otp_ctrl_init_fail.4140284020 Dec 24 02:09:03 PM PST 23 Dec 24 02:09:12 PM PST 23 605234439 ps
T1274 /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.2043643174 Dec 24 02:06:58 PM PST 23 Dec 24 02:07:15 PM PST 23 4124748779 ps
T1275 /workspace/coverage/default/7.otp_ctrl_stress_all.4260061038 Dec 24 02:06:55 PM PST 23 Dec 24 02:07:19 PM PST 23 2647554029 ps
T1276 /workspace/coverage/default/294.otp_ctrl_init_fail.1015537462 Dec 24 02:09:24 PM PST 23 Dec 24 02:09:37 PM PST 23 112924960 ps
T1277 /workspace/coverage/default/136.otp_ctrl_init_fail.1285001960 Dec 24 02:08:42 PM PST 23 Dec 24 02:09:00 PM PST 23 190913720 ps
T1278 /workspace/coverage/default/37.otp_ctrl_dai_errs.1689062400 Dec 24 02:08:12 PM PST 23 Dec 24 02:08:31 PM PST 23 634114579 ps
T1279 /workspace/coverage/default/151.otp_ctrl_init_fail.1617240387 Dec 24 02:08:35 PM PST 23 Dec 24 02:08:54 PM PST 23 1645466247 ps
T1280 /workspace/coverage/default/84.otp_ctrl_init_fail.2300386726 Dec 24 02:08:30 PM PST 23 Dec 24 02:08:46 PM PST 23 535133362 ps
T1281 /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.3276404451 Dec 24 02:09:07 PM PST 23 Dec 24 02:09:15 PM PST 23 793997948 ps
T1282 /workspace/coverage/default/137.otp_ctrl_init_fail.2825333296 Dec 24 02:08:29 PM PST 23 Dec 24 02:08:45 PM PST 23 204151626 ps
T1283 /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1731728642 Dec 24 02:06:29 PM PST 23 Dec 24 03:29:28 PM PST 23 714801013868 ps
T1284 /workspace/coverage/default/43.otp_ctrl_check_fail.1839470955 Dec 24 02:08:29 PM PST 23 Dec 24 02:08:47 PM PST 23 379184907 ps
T1285 /workspace/coverage/default/216.otp_ctrl_init_fail.3965734155 Dec 24 02:09:10 PM PST 23 Dec 24 02:09:21 PM PST 23 139091356 ps
T1286 /workspace/coverage/default/119.otp_ctrl_init_fail.685751093 Dec 24 02:08:30 PM PST 23 Dec 24 02:08:48 PM PST 23 757837646 ps
T1287 /workspace/coverage/default/10.otp_ctrl_stress_all.2228491837 Dec 24 02:06:55 PM PST 23 Dec 24 02:08:08 PM PST 23 25388551970 ps
T1288 /workspace/coverage/default/258.otp_ctrl_init_fail.3021342065 Dec 24 02:09:11 PM PST 23 Dec 24 02:09:23 PM PST 23 2282322719 ps
T1289 /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2118463661 Dec 24 02:08:27 PM PST 23 Dec 24 02:47:11 PM PST 23 121033017829 ps
T1290 /workspace/coverage/default/40.otp_ctrl_alert_test.2565245376 Dec 24 02:08:11 PM PST 23 Dec 24 02:08:24 PM PST 23 84281301 ps
T1291 /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2111459215 Dec 24 02:08:32 PM PST 23 Dec 24 03:45:33 PM PST 23 2220780046818 ps
T1292 /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.4147150657 Dec 24 02:07:06 PM PST 23 Dec 24 03:28:46 PM PST 23 1291294264716 ps
T1293 /workspace/coverage/default/118.otp_ctrl_init_fail.2856529358 Dec 24 02:08:27 PM PST 23 Dec 24 02:08:42 PM PST 23 200568911 ps
T1294 /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3582490911 Dec 24 02:08:14 PM PST 23 Dec 24 03:54:42 PM PST 23 3636993865904 ps
T1295 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1969626308 Dec 24 01:53:12 PM PST 23 Dec 24 01:53:20 PM PST 23 114205173 ps
T1296 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1598563882 Dec 24 01:53:21 PM PST 23 Dec 24 01:53:32 PM PST 23 66854440 ps
T1297 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1914603118 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 38159041 ps
T1298 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.395427862 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:31 PM PST 23 258631538 ps
T1299 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.393038567 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:12 PM PST 23 36945145 ps
T1300 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3271611352 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:22 PM PST 23 69006745 ps
T1301 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3189664932 Dec 24 01:53:13 PM PST 23 Dec 24 01:53:21 PM PST 23 213982114 ps
T1302 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3275764120 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:22 PM PST 23 247762686 ps
T1303 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.4182498289 Dec 24 01:52:46 PM PST 23 Dec 24 01:52:50 PM PST 23 234745739 ps
T1304 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3045695245 Dec 24 01:53:00 PM PST 23 Dec 24 01:53:27 PM PST 23 1233202036 ps
T254 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2795766619 Dec 24 01:52:53 PM PST 23 Dec 24 01:53:04 PM PST 23 178580629 ps
T1305 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.4042661317 Dec 24 01:53:16 PM PST 23 Dec 24 01:53:22 PM PST 23 131141675 ps
T1306 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2299474580 Dec 24 01:53:13 PM PST 23 Dec 24 01:53:24 PM PST 23 145657432 ps
T1307 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1401337973 Dec 24 01:52:45 PM PST 23 Dec 24 01:52:48 PM PST 23 70488129 ps
T1308 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.245079116 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:21 PM PST 23 136696070 ps
T310 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1443663679 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:43 PM PST 23 4168843292 ps
T1309 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3516587311 Dec 24 01:52:59 PM PST 23 Dec 24 01:53:11 PM PST 23 84486847 ps
T255 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.343021707 Dec 24 01:52:58 PM PST 23 Dec 24 01:53:19 PM PST 23 1029347564 ps
T1310 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.4038026208 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:21 PM PST 23 140024610 ps
T1311 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3839724247 Dec 24 01:52:59 PM PST 23 Dec 24 01:53:16 PM PST 23 500535076 ps
T1312 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1544969050 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:27 PM PST 23 944297644 ps
T1313 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1718413897 Dec 24 01:52:48 PM PST 23 Dec 24 01:52:57 PM PST 23 38736710 ps
T1314 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3772607064 Dec 24 01:53:22 PM PST 23 Dec 24 01:53:33 PM PST 23 103700777 ps
T1315 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3729869073 Dec 24 01:52:59 PM PST 23 Dec 24 01:53:11 PM PST 23 39133434 ps
T1316 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2934727952 Dec 24 01:53:00 PM PST 23 Dec 24 01:53:11 PM PST 23 506220129 ps
T1317 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3226929447 Dec 24 01:53:01 PM PST 23 Dec 24 01:53:13 PM PST 23 71343200 ps
T1318 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.66792347 Dec 24 01:53:21 PM PST 23 Dec 24 01:53:32 PM PST 23 129617515 ps
T1319 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1170658095 Dec 24 01:53:00 PM PST 23 Dec 24 01:53:16 PM PST 23 1428459903 ps
T1320 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2110900733 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:20 PM PST 23 125892019 ps
T1321 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.770162658 Dec 24 01:53:14 PM PST 23 Dec 24 01:53:38 PM PST 23 2354892354 ps
T1322 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2968302086 Dec 24 01:53:12 PM PST 23 Dec 24 01:53:19 PM PST 23 532649460 ps
T1323 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.443578851 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:27 PM PST 23 79660662 ps
T1324 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.621298623 Dec 24 01:52:49 PM PST 23 Dec 24 01:52:58 PM PST 23 123954856 ps
T1325 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.299699528 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:27 PM PST 23 501405328 ps
T1326 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.674066766 Dec 24 01:53:21 PM PST 23 Dec 24 01:53:33 PM PST 23 117320844 ps
T1327 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.4221355820 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:27 PM PST 23 40097077 ps
T1328 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2101910800 Dec 24 01:53:02 PM PST 23 Dec 24 01:53:14 PM PST 23 47015792 ps
T1329 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.644212857 Dec 24 01:53:17 PM PST 23 Dec 24 01:53:27 PM PST 23 513356276 ps
T1330 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.881558530 Dec 24 01:53:21 PM PST 23 Dec 24 01:53:32 PM PST 23 550985175 ps
T1331 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3634217927 Dec 24 01:53:15 PM PST 23 Dec 24 01:53:22 PM PST 23 75488112 ps
T1332 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2041766203 Dec 24 01:53:18 PM PST 23 Dec 24 01:53:30 PM PST 23 172230032 ps
T1333 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4251698629 Dec 24 01:53:19 PM PST 23 Dec 24 01:53:30 PM PST 23 104607497 ps

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3691974942
Short name T5
Test name
Test status
Simulation time 793845076953 ps
CPU time 4618.41 seconds
Started Dec 24 02:07:36 PM PST 23
Finished Dec 24 03:24:36 PM PST 23
Peak memory 309616 kb
Host smart-455e4d7b-548a-4bbb-a824-803b72afe80c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691974942 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.3691974942
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3851709068
Short name T21
Test name
Test status
Simulation time 68466984 ps
CPU time 1.35 seconds
Started Dec 24 01:52:48 PM PST 23
Finished Dec 24 01:52:58 PM PST 23
Peak memory 229244 kb
Host smart-c8a4b0ee-a6d8-4456-acaf-8b59b7c84191
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851709068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.3851709068
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.1956118382
Short name T17
Test name
Test status
Simulation time 26282025638 ps
CPU time 206.72 seconds
Started Dec 24 02:07:44 PM PST 23
Finished Dec 24 02:11:12 PM PST 23
Peak memory 245020 kb
Host smart-ccf349da-83cc-45f9-bcc0-387b2d892b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956118382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.1956118382
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1059467200
Short name T114
Test name
Test status
Simulation time 1350002370 ps
CPU time 17.23 seconds
Started Dec 24 01:53:20 PM PST 23
Finished Dec 24 01:53:47 PM PST 23
Peak memory 229536 kb
Host smart-777d2cc3-edb4-4186-b749-656467e3523e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059467200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.1059467200
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3181524621
Short name T179
Test name
Test status
Simulation time 153542985 ps
CPU time 3.35 seconds
Started Dec 24 01:52:57 PM PST 23
Finished Dec 24 01:53:13 PM PST 23
Peak memory 237644 kb
Host smart-4a66e67b-d8f5-42d5-a576-1f65e6cf17fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181524621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3181524621
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.3678465898
Short name T90
Test name
Test status
Simulation time 13684878666 ps
CPU time 101.77 seconds
Started Dec 24 02:08:09 PM PST 23
Finished Dec 24 02:10:03 PM PST 23
Peak memory 246804 kb
Host smart-45574382-22bf-41c2-840b-29b4b51a0b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678465898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.3678465898
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.306301821
Short name T208
Test name
Test status
Simulation time 8908816963 ps
CPU time 140.25 seconds
Started Dec 24 02:06:11 PM PST 23
Finished Dec 24 02:08:37 PM PST 23
Peak memory 267640 kb
Host smart-00a13a0a-f2ba-4703-82f6-e0378a56802f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306301821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.306301821
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.2126695833
Short name T189
Test name
Test status
Simulation time 86728557 ps
CPU time 1.43 seconds
Started Dec 24 01:53:13 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229372 kb
Host smart-a52bd8d1-87f5-4ffc-bd47-af1c20636903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126695833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.2126695833
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.792385166
Short name T102
Test name
Test status
Simulation time 12871276557 ps
CPU time 143.04 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:09:35 PM PST 23
Peak memory 242408 kb
Host smart-2d6f4a6d-1669-48d3-a8fb-c87595facbba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792385166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.
792385166
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.4108100112
Short name T228
Test name
Test status
Simulation time 18904696229 ps
CPU time 25.71 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:37 PM PST 23
Peak memory 229740 kb
Host smart-545cbccf-1e20-401c-a29a-eacf0485b9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108100112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.4108100112
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.3283609163
Short name T202
Test name
Test status
Simulation time 262437269355 ps
CPU time 5061.18 seconds
Started Dec 24 02:07:59 PM PST 23
Finished Dec 24 03:32:33 PM PST 23
Peak memory 994512 kb
Host smart-3f9d459e-2de6-4aef-a3e6-c0a743045916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283609163 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.3283609163
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.3685672363
Short name T162
Test name
Test status
Simulation time 1446641145 ps
CPU time 15.39 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 246896 kb
Host smart-dc0c92bd-d460-4c94-8b62-b78704090f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685672363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.3685672363
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1010124940
Short name T109
Test name
Test status
Simulation time 82356290 ps
CPU time 2.82 seconds
Started Dec 24 01:52:49 PM PST 23
Finished Dec 24 01:53:03 PM PST 23
Peak memory 229408 kb
Host smart-a49d985b-5b66-4933-84c8-1168c4336ee9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010124940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.1010124940
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.2341290772
Short name T155
Test name
Test status
Simulation time 34750934035 ps
CPU time 147.77 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:09:16 PM PST 23
Peak memory 255124 kb
Host smart-937266c8-b24b-4669-a7ac-25dd8dc096b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341290772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
2341290772
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.2345716109
Short name T130
Test name
Test status
Simulation time 165878004 ps
CPU time 3.61 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 238344 kb
Host smart-2e7b99bb-a8a9-498e-8765-c470f037fd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345716109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.2345716109
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.2835155810
Short name T103
Test name
Test status
Simulation time 24391540425 ps
CPU time 116.54 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:10:40 PM PST 23
Peak memory 242616 kb
Host smart-d1da87c7-bc49-49a7-bbf4-de01b99f6482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835155810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.2835155810
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.2041394977
Short name T7
Test name
Test status
Simulation time 388108754357 ps
CPU time 2254.33 seconds
Started Dec 24 02:07:15 PM PST 23
Finished Dec 24 02:45:01 PM PST 23
Peak memory 261316 kb
Host smart-f890fe55-4833-43ca-a891-e63d3b3359f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041394977 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.2041394977
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.2122536179
Short name T36
Test name
Test status
Simulation time 760020789 ps
CPU time 18.47 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 02:06:37 PM PST 23
Peak memory 238536 kb
Host smart-6868ebc9-513a-44c4-93f1-d812799c256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122536179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2122536179
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.3075135093
Short name T11
Test name
Test status
Simulation time 128962987 ps
CPU time 3.13 seconds
Started Dec 24 02:09:24 PM PST 23
Finished Dec 24 02:09:36 PM PST 23
Peak memory 238340 kb
Host smart-04c5dcb9-ac46-4953-848a-47602eccdc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075135093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3075135093
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1765459191
Short name T227
Test name
Test status
Simulation time 2287604856 ps
CPU time 6.59 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:26 PM PST 23
Peak memory 237844 kb
Host smart-67f488bb-b48a-451a-96b7-6ef170a46f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765459191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1765459191
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.45288275
Short name T55
Test name
Test status
Simulation time 1612426450 ps
CPU time 22.95 seconds
Started Dec 24 02:07:44 PM PST 23
Finished Dec 24 02:08:09 PM PST 23
Peak memory 238680 kb
Host smart-ff8e4aa9-8ab6-4b23-b93e-80ba19a0c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45288275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.45288275
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.597011469
Short name T27
Test name
Test status
Simulation time 234504151 ps
CPU time 4.08 seconds
Started Dec 24 02:08:42 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 238488 kb
Host smart-570164e2-f015-4751-8cb2-fe75d79d9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597011469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.597011469
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.204782567
Short name T506
Test name
Test status
Simulation time 3999304075 ps
CPU time 7.96 seconds
Started Dec 24 02:07:08 PM PST 23
Finished Dec 24 02:07:25 PM PST 23
Peak memory 238776 kb
Host smart-126f7178-7e6f-4ba7-9a59-d6e4562269fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204782567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.204782567
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.272627188
Short name T124
Test name
Test status
Simulation time 662891222 ps
CPU time 11.47 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 238496 kb
Host smart-a340564b-d8eb-41ca-999a-95ed622f258c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272627188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.272627188
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.2745942949
Short name T19
Test name
Test status
Simulation time 384411875392 ps
CPU time 7480.39 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 04:13:40 PM PST 23
Peak memory 658320 kb
Host smart-548cf537-23c2-4e7f-9981-ccfbf0c275d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745942949 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.2745942949
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.2418101172
Short name T46
Test name
Test status
Simulation time 795339921 ps
CPU time 13 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 238508 kb
Host smart-45ab4b2e-fe16-4343-9865-cdb118d57a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418101172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2418101172
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3045695245
Short name T1304
Test name
Test status
Simulation time 1233202036 ps
CPU time 17.14 seconds
Started Dec 24 01:53:00 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229612 kb
Host smart-8828c170-2063-4386-a36b-d4198ce5f4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045695245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.3045695245
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.3569766373
Short name T703
Test name
Test status
Simulation time 599089991 ps
CPU time 4.68 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 240676 kb
Host smart-231b07a1-5914-45bd-ba28-a0a9ff87d9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569766373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.3569766373
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3461495742
Short name T183
Test name
Test status
Simulation time 370992914 ps
CPU time 2.77 seconds
Started Dec 24 01:53:20 PM PST 23
Finished Dec 24 01:53:33 PM PST 23
Peak memory 237792 kb
Host smart-a0ee20be-ca80-4309-8a0f-d7726da50129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461495742 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3461495742
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3327590755
Short name T352
Test name
Test status
Simulation time 60392849 ps
CPU time 1.44 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229312 kb
Host smart-952dce78-5668-4f06-8f9b-4bea0d8e8a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327590755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3327590755
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.3536448382
Short name T346
Test name
Test status
Simulation time 372424373 ps
CPU time 4.83 seconds
Started Dec 24 02:08:10 PM PST 23
Finished Dec 24 02:08:27 PM PST 23
Peak memory 238308 kb
Host smart-67899674-c939-4aef-97c0-1c6604b64f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536448382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.3536448382
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.138711584
Short name T31
Test name
Test status
Simulation time 398270132 ps
CPU time 5.35 seconds
Started Dec 24 02:08:38 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 243124 kb
Host smart-cff1581f-6d55-43c4-9c1c-4bb0e73438cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138711584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.138711584
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.30369521
Short name T58
Test name
Test status
Simulation time 125719370 ps
CPU time 4.03 seconds
Started Dec 24 02:09:20 PM PST 23
Finished Dec 24 02:09:36 PM PST 23
Peak memory 238364 kb
Host smart-103304eb-c534-4a04-b696-26f6e581a237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30369521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.30369521
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.1773211628
Short name T405
Test name
Test status
Simulation time 134536362 ps
CPU time 1.69 seconds
Started Dec 24 02:06:02 PM PST 23
Finished Dec 24 02:06:07 PM PST 23
Peak memory 239280 kb
Host smart-b5bed802-67ee-401c-a582-9d79756c0437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773211628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.1773211628
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3190983009
Short name T67
Test name
Test status
Simulation time 242445041 ps
CPU time 4.04 seconds
Started Dec 24 02:08:47 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 240868 kb
Host smart-64d83dc1-96e3-4665-a107-d4dd5f16d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190983009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3190983009
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3202768621
Short name T309
Test name
Test status
Simulation time 3512842644 ps
CPU time 18.43 seconds
Started Dec 24 01:52:57 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 229624 kb
Host smart-9e31b37e-2906-48fc-9611-ed63ecd40355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202768621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.3202768621
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.1390117426
Short name T79
Test name
Test status
Simulation time 233822151 ps
CPU time 4.47 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 238444 kb
Host smart-0ba6c0eb-352f-4eaf-bba0-ada3406db8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390117426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1390117426
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.690064156
Short name T203
Test name
Test status
Simulation time 8562964893 ps
CPU time 143.26 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:09:50 PM PST 23
Peak memory 246812 kb
Host smart-5c3ad6df-941c-4a90-a0ed-3ac0a9063130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690064156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.
690064156
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3552415244
Short name T234
Test name
Test status
Simulation time 37926258 ps
CPU time 1.51 seconds
Started Dec 24 01:53:00 PM PST 23
Finished Dec 24 01:53:11 PM PST 23
Peak memory 229564 kb
Host smart-2691f810-e163-4bbb-b9cd-f35bcc42e22c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552415244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3552415244
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.714384625
Short name T1250
Test name
Test status
Simulation time 211353108 ps
CPU time 5.04 seconds
Started Dec 24 02:08:46 PM PST 23
Finished Dec 24 02:09:05 PM PST 23
Peak memory 238372 kb
Host smart-b9299775-2635-416b-84b9-e6fe068f609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714384625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.714384625
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.878913766
Short name T52
Test name
Test status
Simulation time 502436258 ps
CPU time 11.54 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:10 PM PST 23
Peak memory 243928 kb
Host smart-c590275b-fc90-4c80-b181-f319f4a56ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878913766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.878913766
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.1879464593
Short name T64
Test name
Test status
Simulation time 10894694441 ps
CPU time 29.8 seconds
Started Dec 24 02:07:11 PM PST 23
Finished Dec 24 02:07:52 PM PST 23
Peak memory 238516 kb
Host smart-81f66d81-d5e0-4c2f-96f0-fccb10b71d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879464593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.1879464593
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.2140266785
Short name T169
Test name
Test status
Simulation time 30719375947 ps
CPU time 90.71 seconds
Started Dec 24 02:06:18 PM PST 23
Finished Dec 24 02:07:55 PM PST 23
Peak memory 240768 kb
Host smart-0c6146d9-f8e7-45cc-8122-d62f4d5b2bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140266785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
2140266785
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.1626682257
Short name T164
Test name
Test status
Simulation time 119421565 ps
CPU time 3.34 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:08:37 PM PST 23
Peak memory 238416 kb
Host smart-1d48a296-506a-4cde-9fd2-8f0cd1a1bc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626682257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1626682257
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3610743793
Short name T231
Test name
Test status
Simulation time 1204958979 ps
CPU time 9.79 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:29 PM PST 23
Peak memory 229832 kb
Host smart-43a8d01e-48bb-46aa-b43d-fc3729412c3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610743793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.3610743793
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.1245087623
Short name T321
Test name
Test status
Simulation time 490485627 ps
CPU time 8.33 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 02:06:26 PM PST 23
Peak memory 238536 kb
Host smart-d139bd07-5429-4259-8872-a499dfdf7450
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245087623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1245087623
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.531470783
Short name T327
Test name
Test status
Simulation time 2334445449 ps
CPU time 7.62 seconds
Started Dec 24 02:08:36 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 243800 kb
Host smart-7be030e5-d609-4f83-9632-6b210f44dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531470783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.531470783
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.2967433784
Short name T61
Test name
Test status
Simulation time 5514159225 ps
CPU time 24.06 seconds
Started Dec 24 02:07:44 PM PST 23
Finished Dec 24 02:08:10 PM PST 23
Peak memory 238688 kb
Host smart-c8682e56-e2df-41cd-9e45-4bf73e5f104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967433784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2967433784
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.976942614
Short name T22
Test name
Test status
Simulation time 123088320958 ps
CPU time 2481.56 seconds
Started Dec 24 02:06:47 PM PST 23
Finished Dec 24 02:48:15 PM PST 23
Peak memory 272796 kb
Host smart-2cfff3a7-f14f-4831-930d-8acc3d007832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976942614 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.976942614
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2287628631
Short name T1017
Test name
Test status
Simulation time 21756741409 ps
CPU time 149.36 seconds
Started Dec 24 02:07:10 PM PST 23
Finished Dec 24 02:09:50 PM PST 23
Peak memory 246872 kb
Host smart-e3389f2c-e64d-4029-bc94-bc42ef96720d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287628631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2287628631
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.3945239936
Short name T53
Test name
Test status
Simulation time 194273795 ps
CPU time 4.43 seconds
Started Dec 24 02:09:34 PM PST 23
Finished Dec 24 02:09:43 PM PST 23
Peak memory 240912 kb
Host smart-699195b5-3944-49d7-9293-edd593faa6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945239936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3945239936
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.4140008393
Short name T34
Test name
Test status
Simulation time 653820487 ps
CPU time 10.39 seconds
Started Dec 24 02:07:59 PM PST 23
Finished Dec 24 02:08:20 PM PST 23
Peak memory 238588 kb
Host smart-4556872a-9b64-4e67-a5fd-84ff35fa5202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140008393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.4140008393
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.1617747583
Short name T69
Test name
Test status
Simulation time 126596735 ps
CPU time 2.98 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 240280 kb
Host smart-8ed86075-893c-452b-be18-09fb0e1d4e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617747583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1617747583
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1001259188
Short name T302
Test name
Test status
Simulation time 5490867592352 ps
CPU time 6982.32 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 04:05:05 PM PST 23
Peak memory 276140 kb
Host smart-425a7f89-bf56-4f96-9098-afe1ea258954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001259188 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.1001259188
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.109854745
Short name T688
Test name
Test status
Simulation time 2632710973 ps
CPU time 7.2 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 238604 kb
Host smart-09b192c9-a16e-46e5-b367-14fd802a2141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109854745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.109854745
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.473873899
Short name T161
Test name
Test status
Simulation time 259357425 ps
CPU time 3.89 seconds
Started Dec 24 02:08:34 PM PST 23
Finished Dec 24 02:08:53 PM PST 23
Peak memory 240904 kb
Host smart-4a2a6f6c-e8b4-4abf-9d2e-dbba902a205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473873899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.473873899
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.4164145457
Short name T193
Test name
Test status
Simulation time 67785483690 ps
CPU time 160.54 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:11:36 PM PST 23
Peak memory 241104 kb
Host smart-bcd14c32-c2b6-41e5-8507-3d9530d7af54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164145457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.4164145457
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.3112384951
Short name T168
Test name
Test status
Simulation time 315684451 ps
CPU time 5.31 seconds
Started Dec 24 02:07:07 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 239748 kb
Host smart-04517a15-8a94-4309-86fd-ea8e3d7e2369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112384951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3112384951
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.4056916061
Short name T265
Test name
Test status
Simulation time 3490794313001 ps
CPU time 6619.8 seconds
Started Dec 24 02:08:18 PM PST 23
Finished Dec 24 03:58:48 PM PST 23
Peak memory 964740 kb
Host smart-dce1c639-2d01-448c-8a77-5c78c996940e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056916061 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.4056916061
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.3665225405
Short name T75
Test name
Test status
Simulation time 228718489 ps
CPU time 8.33 seconds
Started Dec 24 02:08:35 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 238512 kb
Host smart-ced67253-1884-43a0-ae86-ec6610a742d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665225405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.3665225405
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3132325885
Short name T308
Test name
Test status
Simulation time 18495298613 ps
CPU time 32.46 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:59 PM PST 23
Peak memory 238048 kb
Host smart-f3d31e7c-563a-42d1-93f8-ae0c13dc7bea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132325885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.3132325885
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.853022918
Short name T355
Test name
Test status
Simulation time 41394979 ps
CPU time 1.38 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:29 PM PST 23
Peak memory 229396 kb
Host smart-dd0baa57-d2a9-4394-a477-dd17e849ee0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853022918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.853022918
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3338995483
Short name T241
Test name
Test status
Simulation time 38345436 ps
CPU time 1.52 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229564 kb
Host smart-2126a4ac-48ac-45f9-a393-e2febeb2bd39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338995483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3338995483
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.389763605
Short name T30
Test name
Test status
Simulation time 588168585 ps
CPU time 4.51 seconds
Started Dec 24 02:06:07 PM PST 23
Finished Dec 24 02:06:16 PM PST 23
Peak memory 241268 kb
Host smart-cf81aeb7-0288-49b5-b9bb-146c9539204c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389763605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.389763605
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.2038104568
Short name T1081
Test name
Test status
Simulation time 541592367 ps
CPU time 4.09 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 238392 kb
Host smart-67d1e59f-36f6-4ca8-b7eb-c1e8bd96a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038104568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.2038104568
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.193374250
Short name T50
Test name
Test status
Simulation time 399465872 ps
CPU time 3.8 seconds
Started Dec 24 02:09:09 PM PST 23
Finished Dec 24 02:09:17 PM PST 23
Peak memory 240340 kb
Host smart-05149316-49a8-4461-882f-65e2d324ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193374250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.193374250
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3887751226
Short name T205
Test name
Test status
Simulation time 1292890491 ps
CPU time 17.43 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 229768 kb
Host smart-a880d736-630d-45ae-87ca-6a4d1aa07418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887751226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.3887751226
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.1862672775
Short name T218
Test name
Test status
Simulation time 167620461 ps
CPU time 4.59 seconds
Started Dec 24 02:07:17 PM PST 23
Finished Dec 24 02:07:33 PM PST 23
Peak memory 240724 kb
Host smart-a0a7b67f-ca67-412b-abe2-b8e405250923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862672775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.1862672775
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.3898790351
Short name T1084
Test name
Test status
Simulation time 142494974 ps
CPU time 3.59 seconds
Started Dec 24 02:09:09 PM PST 23
Finished Dec 24 02:09:15 PM PST 23
Peak memory 241064 kb
Host smart-ff8d8b98-e480-4b9f-9be4-ab5d63f42497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898790351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3898790351
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.3622367038
Short name T42
Test name
Test status
Simulation time 542113080 ps
CPU time 4.62 seconds
Started Dec 24 02:09:25 PM PST 23
Finished Dec 24 02:09:38 PM PST 23
Peak memory 238420 kb
Host smart-9be245c7-c5e2-4214-b059-71821766a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622367038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.3622367038
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.111871930
Short name T220
Test name
Test status
Simulation time 583092612 ps
CPU time 5.08 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:08:16 PM PST 23
Peak memory 240664 kb
Host smart-62cd0503-7ecb-4b74-b40a-97eeb831c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111871930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.111871930
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.3349928831
Short name T45
Test name
Test status
Simulation time 785742753 ps
CPU time 15.37 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:14 PM PST 23
Peak memory 238600 kb
Host smart-56cedf4c-2fc3-4888-8ef5-be414412644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349928831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.3349928831
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.3608793185
Short name T196
Test name
Test status
Simulation time 21466836083 ps
CPU time 172.14 seconds
Started Dec 24 02:07:08 PM PST 23
Finished Dec 24 02:10:10 PM PST 23
Peak memory 244416 kb
Host smart-1aaf7f40-90e2-4ee7-a3dc-8f50bfd8bb9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608793185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.3608793185
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.1445102350
Short name T853
Test name
Test status
Simulation time 22429746689 ps
CPU time 100.32 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 243952 kb
Host smart-840ec1eb-3e96-4ab2-a8e4-1768fe93d5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445102350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.1445102350
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.558059503
Short name T1050
Test name
Test status
Simulation time 2575479120 ps
CPU time 21.54 seconds
Started Dec 24 02:06:31 PM PST 23
Finished Dec 24 02:06:56 PM PST 23
Peak memory 246880 kb
Host smart-abdad13c-d390-4573-ac54-7a35b09cf73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558059503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.558059503
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.956134482
Short name T1258
Test name
Test status
Simulation time 280948255 ps
CPU time 3.82 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 241116 kb
Host smart-e0e347ef-2b95-4954-8a59-e7dcfce65755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956134482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.956134482
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.1291143501
Short name T222
Test name
Test status
Simulation time 486332083 ps
CPU time 4.38 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 238232 kb
Host smart-1354da89-47fb-4e67-80b5-5d39b2e07944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291143501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1291143501
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.629119416
Short name T72
Test name
Test status
Simulation time 716123688 ps
CPU time 5.36 seconds
Started Dec 24 02:09:15 PM PST 23
Finished Dec 24 02:09:32 PM PST 23
Peak memory 238444 kb
Host smart-29dd9910-57d0-4201-bda7-170977c378ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629119416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.629119416
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.1202585441
Short name T219
Test name
Test status
Simulation time 159167678 ps
CPU time 4.16 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:06:48 PM PST 23
Peak memory 238404 kb
Host smart-402fcd5d-c1f4-42e7-a11b-9db795af1e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202585441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1202585441
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.3289872449
Short name T1066
Test name
Test status
Simulation time 71603132063 ps
CPU time 182.03 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 02:09:20 PM PST 23
Peak memory 255044 kb
Host smart-5e6af5f1-3e0c-442b-9095-37bd6187de7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289872449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
3289872449
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.2609410718
Short name T83
Test name
Test status
Simulation time 427012282 ps
CPU time 3.46 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:02 PM PST 23
Peak memory 240412 kb
Host smart-89717216-8da4-43a9-bcc8-f32614fa5c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609410718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2609410718
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.2453498156
Short name T858
Test name
Test status
Simulation time 140379286 ps
CPU time 3.52 seconds
Started Dec 24 02:09:07 PM PST 23
Finished Dec 24 02:09:13 PM PST 23
Peak memory 238392 kb
Host smart-567b6ffe-8edd-4698-8dc7-5f472f2b878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453498156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2453498156
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.290927504
Short name T89
Test name
Test status
Simulation time 1127566468 ps
CPU time 18.54 seconds
Started Dec 24 02:06:47 PM PST 23
Finished Dec 24 02:07:12 PM PST 23
Peak memory 243648 kb
Host smart-40b372e0-80ad-4da1-8f84-1de1bdc1a236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290927504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.290927504
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3330794839
Short name T108
Test name
Test status
Simulation time 160310026 ps
CPU time 2.88 seconds
Started Dec 24 01:53:00 PM PST 23
Finished Dec 24 01:53:12 PM PST 23
Peak memory 229612 kb
Host smart-d4af3abf-76fc-4a8f-a65d-b5e9ba514cf1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330794839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.3330794839
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2690342422
Short name T267
Test name
Test status
Simulation time 518019283 ps
CPU time 9.36 seconds
Started Dec 24 01:52:51 PM PST 23
Finished Dec 24 01:53:10 PM PST 23
Peak memory 229500 kb
Host smart-1e0d9d7b-f2bd-439e-a090-bd57eb3a9a16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690342422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.2690342422
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.674066766
Short name T1326
Test name
Test status
Simulation time 117320844 ps
CPU time 1.75 seconds
Started Dec 24 01:53:21 PM PST 23
Finished Dec 24 01:53:33 PM PST 23
Peak memory 229556 kb
Host smart-19f7df82-1ab9-4471-bd83-c1e4f8af0eee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674066766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.674066766
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.316312482
Short name T186
Test name
Test status
Simulation time 104354721 ps
CPU time 3.48 seconds
Started Dec 24 01:53:12 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 237784 kb
Host smart-cdaa0520-2029-4f22-b976-3ab8dc5c7fa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316312482 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.316312482
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3516587311
Short name T1309
Test name
Test status
Simulation time 84486847 ps
CPU time 1.52 seconds
Started Dec 24 01:52:59 PM PST 23
Finished Dec 24 01:53:11 PM PST 23
Peak memory 229404 kb
Host smart-dedda8de-cb9b-40fe-b31c-4da2de421f57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516587311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.3516587311
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2101910800
Short name T1328
Test name
Test status
Simulation time 47015792 ps
CPU time 1.43 seconds
Started Dec 24 01:53:02 PM PST 23
Finished Dec 24 01:53:14 PM PST 23
Peak memory 229492 kb
Host smart-4a05aa2c-bb6f-4194-a25a-2eaadd7cfe21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101910800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2101910800
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2751788610
Short name T382
Test name
Test status
Simulation time 509403279 ps
CPU time 1.89 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:22 PM PST 23
Peak memory 229240 kb
Host smart-1cd530ca-13a8-4118-a880-23e5ec38ca81
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751788610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.2751788610
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.4042661317
Short name T1305
Test name
Test status
Simulation time 131141675 ps
CPU time 1.25 seconds
Started Dec 24 01:53:16 PM PST 23
Finished Dec 24 01:53:22 PM PST 23
Peak memory 229172 kb
Host smart-7d3d3901-ec9e-4288-99a7-6b3aee75318e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042661317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.4042661317
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1969626308
Short name T1295
Test name
Test status
Simulation time 114205173 ps
CPU time 1.79 seconds
Started Dec 24 01:53:12 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229636 kb
Host smart-a946d62c-cc10-4b9d-b99b-f9cebaa70ea5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969626308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1969626308
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2328122342
Short name T236
Test name
Test status
Simulation time 297015844 ps
CPU time 2.97 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:23 PM PST 23
Peak memory 229500 kb
Host smart-4e2137fe-d513-4fa7-94cf-d9244b8fb8b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328122342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.2328122342
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3362557512
Short name T257
Test name
Test status
Simulation time 315172728 ps
CPU time 3.78 seconds
Started Dec 24 01:53:13 PM PST 23
Finished Dec 24 01:53:22 PM PST 23
Peak memory 229460 kb
Host smart-549aed2b-e10e-4548-b4dc-37fe3e6a3fd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362557512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.3362557512
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1598563882
Short name T1296
Test name
Test status
Simulation time 66854440 ps
CPU time 1.84 seconds
Started Dec 24 01:53:21 PM PST 23
Finished Dec 24 01:53:32 PM PST 23
Peak memory 229448 kb
Host smart-08d19963-ae0c-44ff-a179-7ada66543bfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598563882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.1598563882
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3669341593
Short name T371
Test name
Test status
Simulation time 235919441 ps
CPU time 3.26 seconds
Started Dec 24 01:52:52 PM PST 23
Finished Dec 24 01:53:05 PM PST 23
Peak memory 237692 kb
Host smart-58c32a46-7e38-4e5e-b71b-c7246abf86a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669341593 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.3669341593
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1914603118
Short name T1297
Test name
Test status
Simulation time 38159041 ps
CPU time 1.43 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229492 kb
Host smart-bdea5819-4aae-4bd3-bdec-33616bfb9229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914603118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1914603118
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1438147196
Short name T375
Test name
Test status
Simulation time 38476990 ps
CPU time 1.38 seconds
Started Dec 24 01:53:02 PM PST 23
Finished Dec 24 01:53:14 PM PST 23
Peak memory 229148 kb
Host smart-1aefc627-1c9e-4704-83dc-89d7a95bb9f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438147196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1438147196
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.66792347
Short name T1318
Test name
Test status
Simulation time 129617515 ps
CPU time 1.41 seconds
Started Dec 24 01:53:21 PM PST 23
Finished Dec 24 01:53:32 PM PST 23
Peak memory 229156 kb
Host smart-8b98956e-cd28-491d-a000-563980e64aa6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66792347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_
mem_partial_access.66792347
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.739061404
Short name T392
Test name
Test status
Simulation time 37319351 ps
CPU time 1.32 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 229276 kb
Host smart-d9713914-dc25-42fc-8aee-27ed1e9d8528
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739061404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.
739061404
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.4124058185
Short name T380
Test name
Test status
Simulation time 179650095 ps
CPU time 2.84 seconds
Started Dec 24 01:52:46 PM PST 23
Finished Dec 24 01:52:52 PM PST 23
Peak memory 229624 kb
Host smart-72ae7fe1-fd7c-49cc-8367-bc7e8c6e04e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124058185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.4124058185
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.578953794
Short name T292
Test name
Test status
Simulation time 1488929181 ps
CPU time 4.39 seconds
Started Dec 24 01:53:02 PM PST 23
Finished Dec 24 01:53:18 PM PST 23
Peak memory 237728 kb
Host smart-3cfb27b0-1121-4153-a77b-537dbaa83824
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578953794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.578953794
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.395427862
Short name T1298
Test name
Test status
Simulation time 258631538 ps
CPU time 2.86 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:31 PM PST 23
Peak memory 246028 kb
Host smart-5f659b7f-9dac-43a9-993b-44ae164f5909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395427862 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.395427862
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.595844131
Short name T268
Test name
Test status
Simulation time 36894954 ps
CPU time 1.34 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 229220 kb
Host smart-4d95b513-3a3f-4719-b492-c91d9a5b926d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595844131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.595844131
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1902383975
Short name T263
Test name
Test status
Simulation time 246957078 ps
CPU time 3.19 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 229548 kb
Host smart-5e83d56d-0b03-488f-a7e7-7029dc5468d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902383975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1902383975
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1433255742
Short name T178
Test name
Test status
Simulation time 762567707 ps
CPU time 3.48 seconds
Started Dec 24 01:53:02 PM PST 23
Finished Dec 24 01:53:17 PM PST 23
Peak memory 237844 kb
Host smart-b4f55e59-38b7-4512-97fc-9f55aeb52243
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433255742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1433255742
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1443663679
Short name T310
Test name
Test status
Simulation time 4168843292 ps
CPU time 16.32 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:43 PM PST 23
Peak memory 229824 kb
Host smart-9cd788c8-07b7-4ea1-9e2b-25af2921b9d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443663679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.1443663679
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3965468152
Short name T180
Test name
Test status
Simulation time 1083703115 ps
CPU time 2.96 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 237756 kb
Host smart-56edc928-1351-4ce6-a5b2-386b1cf4cb60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965468152 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3965468152
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1974865909
Short name T248
Test name
Test status
Simulation time 580679233 ps
CPU time 1.71 seconds
Started Dec 24 01:53:26 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 229400 kb
Host smart-8e414d54-3b43-4038-bfe7-0df103557f1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974865909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1974865909
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1730926861
Short name T372
Test name
Test status
Simulation time 142970398 ps
CPU time 1.41 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:26 PM PST 23
Peak memory 229200 kb
Host smart-ca36bb0a-5cfe-4a11-b9a1-c3dec3baeda5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730926861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1730926861
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3767874009
Short name T229
Test name
Test status
Simulation time 239030747 ps
CPU time 2.05 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:29 PM PST 23
Peak memory 229564 kb
Host smart-cb37d368-48b9-4c70-a073-e2e7af32f7c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767874009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3767874009
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4251698629
Short name T1333
Test name
Test status
Simulation time 104607497 ps
CPU time 2.93 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 237744 kb
Host smart-e13784c8-5cb4-46b4-9c37-659e65a0b133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251698629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.4251698629
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.662853048
Short name T397
Test name
Test status
Simulation time 273657142 ps
CPU time 3.58 seconds
Started Dec 24 01:53:22 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 237764 kb
Host smart-f8ade17b-842a-4962-b09c-adeb1b8cbce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662853048 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.662853048
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1408838697
Short name T239
Test name
Test status
Simulation time 68737615 ps
CPU time 1.35 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 229524 kb
Host smart-9f9b717f-3d0f-486a-92a0-9d5e957ac41c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408838697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1408838697
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.955545506
Short name T391
Test name
Test status
Simulation time 64884041 ps
CPU time 1.34 seconds
Started Dec 24 01:53:27 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 229208 kb
Host smart-a2a8dd00-5af8-4193-bc2c-fe72fa388441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955545506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.955545506
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2687598088
Short name T368
Test name
Test status
Simulation time 42754758 ps
CPU time 1.74 seconds
Started Dec 24 01:53:21 PM PST 23
Finished Dec 24 01:53:32 PM PST 23
Peak memory 229540 kb
Host smart-9497eeb4-e6f3-4b31-b294-44b2467b7ab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687598088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.2687598088
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2555226596
Short name T177
Test name
Test status
Simulation time 100797203 ps
CPU time 3.3 seconds
Started Dec 24 01:53:20 PM PST 23
Finished Dec 24 01:53:33 PM PST 23
Peak memory 237844 kb
Host smart-afbd0a7b-d664-4ff5-9cfd-5abb1b3f15fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555226596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2555226596
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2976134510
Short name T261
Test name
Test status
Simulation time 1811750967 ps
CPU time 20.46 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:49 PM PST 23
Peak memory 229664 kb
Host smart-c561eb65-1b31-4b47-9a72-a0c477098347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976134510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2976134510
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.265581730
Short name T271
Test name
Test status
Simulation time 92057314 ps
CPU time 2.15 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 237860 kb
Host smart-dece78cd-3de5-4b07-b396-054e484848a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265581730 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.265581730
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.4065042814
Short name T245
Test name
Test status
Simulation time 38830153 ps
CPU time 1.54 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 229576 kb
Host smart-f95b03d2-ddac-4a9a-bf2a-3ac4ec472ec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065042814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.4065042814
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3124919747
Short name T306
Test name
Test status
Simulation time 48541379 ps
CPU time 1.37 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229552 kb
Host smart-c3acbfdc-07b0-479e-b8a2-40451eb06bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124919747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3124919747
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2323367022
Short name T237
Test name
Test status
Simulation time 306372828 ps
CPU time 3.19 seconds
Started Dec 24 01:53:24 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 229612 kb
Host smart-55eaf209-6eee-49e9-bdc7-0ce10a96d1a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323367022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.2323367022
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3585543081
Short name T395
Test name
Test status
Simulation time 57514382 ps
CPU time 2.91 seconds
Started Dec 24 01:53:16 PM PST 23
Finished Dec 24 01:53:26 PM PST 23
Peak memory 237920 kb
Host smart-27529d5e-57da-4f54-a8df-b91548bcc68b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585543081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3585543081
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1196199912
Short name T376
Test name
Test status
Simulation time 904866866 ps
CPU time 10.42 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 229376 kb
Host smart-c3eae8cb-b3b4-4b60-a47f-46df6eb2e0bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196199912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.1196199912
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.163513328
Short name T184
Test name
Test status
Simulation time 95533934 ps
CPU time 2.76 seconds
Started Dec 24 01:53:21 PM PST 23
Finished Dec 24 01:53:34 PM PST 23
Peak memory 237892 kb
Host smart-63726844-e129-4611-ba18-462a830ffc43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163513328 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.163513328
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1921719942
Short name T247
Test name
Test status
Simulation time 153094275 ps
CPU time 1.64 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229564 kb
Host smart-d91e729b-32b0-4988-826a-17edb230caf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921719942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1921719942
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2760963155
Short name T112
Test name
Test status
Simulation time 50886616 ps
CPU time 1.38 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 229376 kb
Host smart-00c53fd5-7045-4522-81da-4f814815627a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760963155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2760963155
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.323488262
Short name T396
Test name
Test status
Simulation time 146100046 ps
CPU time 2.44 seconds
Started Dec 24 01:53:16 PM PST 23
Finished Dec 24 01:53:23 PM PST 23
Peak memory 229612 kb
Host smart-884fd591-2f16-48e5-98f4-45694a4ee526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323488262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_c
trl_same_csr_outstanding.323488262
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3225867261
Short name T350
Test name
Test status
Simulation time 2395016649 ps
CPU time 6.23 seconds
Started Dec 24 01:53:20 PM PST 23
Finished Dec 24 01:53:36 PM PST 23
Peak memory 237824 kb
Host smart-18b26e61-8064-418c-89fb-eafb3c810fd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225867261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3225867261
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.4012389274
Short name T366
Test name
Test status
Simulation time 1114825024 ps
CPU time 3.58 seconds
Started Dec 24 01:53:21 PM PST 23
Finished Dec 24 01:53:34 PM PST 23
Peak memory 245144 kb
Host smart-7385dbbb-43c7-47cb-80bb-e9e4aad5d35a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012389274 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.4012389274
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2904258100
Short name T230
Test name
Test status
Simulation time 579620120 ps
CPU time 1.86 seconds
Started Dec 24 01:53:22 PM PST 23
Finished Dec 24 01:53:33 PM PST 23
Peak memory 229420 kb
Host smart-080ec198-3dc6-47e6-b37e-9660b64c2fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904258100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2904258100
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3956957314
Short name T364
Test name
Test status
Simulation time 72938673 ps
CPU time 1.34 seconds
Started Dec 24 01:53:16 PM PST 23
Finished Dec 24 01:53:24 PM PST 23
Peak memory 229256 kb
Host smart-67f22556-a2b4-416f-9224-af92af95b657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956957314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3956957314
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2454845798
Short name T240
Test name
Test status
Simulation time 916202970 ps
CPU time 3 seconds
Started Dec 24 01:53:20 PM PST 23
Finished Dec 24 01:53:32 PM PST 23
Peak memory 229536 kb
Host smart-76bc3a47-ff37-4beb-92e2-50c6d9fae8b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454845798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.2454845798
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1440338891
Short name T224
Test name
Test status
Simulation time 175202117 ps
CPU time 5.11 seconds
Started Dec 24 01:53:22 PM PST 23
Finished Dec 24 01:53:37 PM PST 23
Peak memory 237640 kb
Host smart-d780b6a2-40c9-4310-a24e-4c15f09dfff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440338891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1440338891
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.805091640
Short name T204
Test name
Test status
Simulation time 1751649945 ps
CPU time 18.33 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:46 PM PST 23
Peak memory 229644 kb
Host smart-20b1060f-eb75-4dcf-995f-2d4aa74e41ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805091640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_in
tg_err.805091640
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1709542575
Short name T181
Test name
Test status
Simulation time 126985024 ps
CPU time 1.91 seconds
Started Dec 24 01:53:24 PM PST 23
Finished Dec 24 01:53:34 PM PST 23
Peak memory 237844 kb
Host smart-6ca6505c-592e-46bd-885d-110eb3591c51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709542575 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1709542575
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.78324826
Short name T360
Test name
Test status
Simulation time 36704853 ps
CPU time 1.38 seconds
Started Dec 24 01:53:16 PM PST 23
Finished Dec 24 01:53:23 PM PST 23
Peak memory 229520 kb
Host smart-54a6f5be-9bcc-45c8-aa61-78e7d1c332fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78324826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.78324826
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.705596429
Short name T378
Test name
Test status
Simulation time 54229859 ps
CPU time 2.11 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 229548 kb
Host smart-61497f35-fcb0-4a95-b73b-d030c7732bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705596429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c
trl_same_csr_outstanding.705596429
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1725091525
Short name T293
Test name
Test status
Simulation time 329257615 ps
CPU time 6.04 seconds
Started Dec 24 01:53:16 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 237860 kb
Host smart-9f32b77c-174d-4bb0-b6b9-f683d3457777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725091525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1725091525
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3275764120
Short name T1302
Test name
Test status
Simulation time 247762686 ps
CPU time 1.9 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:22 PM PST 23
Peak memory 237804 kb
Host smart-b8dba710-5d9d-42e5-811b-ca79fb2ffde9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275764120 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.3275764120
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.183808296
Short name T115
Test name
Test status
Simulation time 98709992 ps
CPU time 1.44 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229608 kb
Host smart-e38e559d-90d3-4878-9d31-35962f866e6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183808296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.183808296
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2350454890
Short name T269
Test name
Test status
Simulation time 42124657 ps
CPU time 1.41 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 229432 kb
Host smart-ce7a3f13-0eca-4d2b-967a-891c2af11d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350454890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2350454890
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3772607064
Short name T1314
Test name
Test status
Simulation time 103700777 ps
CPU time 1.71 seconds
Started Dec 24 01:53:22 PM PST 23
Finished Dec 24 01:53:33 PM PST 23
Peak memory 229444 kb
Host smart-5ab8b85b-d2b1-4034-82a7-785dfc2dd7f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772607064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.3772607064
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2299474580
Short name T1306
Test name
Test status
Simulation time 145657432 ps
CPU time 5.69 seconds
Started Dec 24 01:53:13 PM PST 23
Finished Dec 24 01:53:24 PM PST 23
Peak memory 237852 kb
Host smart-49cffa6f-da39-4a4b-9b63-02a70f06230b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299474580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.2299474580
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2347256243
Short name T374
Test name
Test status
Simulation time 9714536143 ps
CPU time 24.42 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:43 PM PST 23
Peak memory 229808 kb
Host smart-b7491caa-bd00-440d-9c4f-deb4dcf732d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347256243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.2347256243
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1298336875
Short name T362
Test name
Test status
Simulation time 284990884 ps
CPU time 3.21 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:32 PM PST 23
Peak memory 237240 kb
Host smart-03fa733d-bfe6-4265-a4e6-bb5b9b581530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298336875 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1298336875
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3811826400
Short name T356
Test name
Test status
Simulation time 81413362 ps
CPU time 1.53 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229568 kb
Host smart-550f57c5-cb48-4040-9b59-c19a14b2b668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811826400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3811826400
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.97074632
Short name T388
Test name
Test status
Simulation time 142448596 ps
CPU time 1.24 seconds
Started Dec 24 01:53:16 PM PST 23
Finished Dec 24 01:53:23 PM PST 23
Peak memory 229124 kb
Host smart-86be211f-d3ea-4ad0-a5c6-44fbeab2f7d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97074632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.97074632
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3189664932
Short name T1301
Test name
Test status
Simulation time 213982114 ps
CPU time 2.98 seconds
Started Dec 24 01:53:13 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 229624 kb
Host smart-57082e62-3403-4035-bc6b-a43a38a76d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189664932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.3189664932
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.770162658
Short name T1321
Test name
Test status
Simulation time 2354892354 ps
CPU time 19.03 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:38 PM PST 23
Peak memory 240672 kb
Host smart-62ffe8db-feb9-4cdc-9790-46f328b94a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770162658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_in
tg_err.770162658
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3967926836
Short name T367
Test name
Test status
Simulation time 182647604 ps
CPU time 2.97 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:23 PM PST 23
Peak memory 237840 kb
Host smart-4d21df54-72c1-4c29-a3f4-b8a1ee4cee56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967926836 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.3967926836
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1975377898
Short name T175
Test name
Test status
Simulation time 96987401 ps
CPU time 1.41 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229496 kb
Host smart-4c6d745b-fe4f-4486-afb2-ac60cc370e80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975377898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1975377898
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1680970271
Short name T251
Test name
Test status
Simulation time 546270973 ps
CPU time 2.22 seconds
Started Dec 24 01:53:10 PM PST 23
Finished Dec 24 01:53:19 PM PST 23
Peak memory 229128 kb
Host smart-95702890-f1c2-4c51-b421-96abb08bc87b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680970271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1680970271
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.442551941
Short name T238
Test name
Test status
Simulation time 219381403 ps
CPU time 2.71 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 229608 kb
Host smart-58be5e63-fec1-49c7-88a7-cdb2900c0fb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442551941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_c
trl_same_csr_outstanding.442551941
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2041766203
Short name T1332
Test name
Test status
Simulation time 172230032 ps
CPU time 3.3 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 237660 kb
Host smart-f473f92a-ecee-458f-887a-6627c159166f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041766203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2041766203
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3876843770
Short name T390
Test name
Test status
Simulation time 1223244110 ps
CPU time 16.12 seconds
Started Dec 24 01:53:12 PM PST 23
Finished Dec 24 01:53:34 PM PST 23
Peak memory 237736 kb
Host smart-6f7aa6b3-a365-4c35-b8db-1b02e168bf2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876843770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.3876843770
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.473184412
Short name T110
Test name
Test status
Simulation time 276955091 ps
CPU time 5.17 seconds
Started Dec 24 01:52:48 PM PST 23
Finished Dec 24 01:53:00 PM PST 23
Peak memory 229528 kb
Host smart-7c54f41c-6f9f-4ea8-b478-be807fe8141e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473184412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b
ash.473184412
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.97563067
Short name T117
Test name
Test status
Simulation time 290413379 ps
CPU time 2.36 seconds
Started Dec 24 01:52:48 PM PST 23
Finished Dec 24 01:52:57 PM PST 23
Peak memory 229596 kb
Host smart-c9ff036d-2c23-4faf-954a-7c27b9d84365
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97563067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_res
et.97563067
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.4182498289
Short name T1303
Test name
Test status
Simulation time 234745739 ps
CPU time 2.42 seconds
Started Dec 24 01:52:46 PM PST 23
Finished Dec 24 01:52:50 PM PST 23
Peak memory 237780 kb
Host smart-63ad4768-2e9e-44a7-a846-dc05cc592a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182498289 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.4182498289
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.231167241
Short name T365
Test name
Test status
Simulation time 36777372 ps
CPU time 1.5 seconds
Started Dec 24 01:52:53 PM PST 23
Finished Dec 24 01:53:03 PM PST 23
Peak memory 229560 kb
Host smart-a92356d8-7c0a-4132-90b7-d46179ddc304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231167241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.231167241
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.793179826
Short name T389
Test name
Test status
Simulation time 54841217 ps
CPU time 1.29 seconds
Started Dec 24 01:52:45 PM PST 23
Finished Dec 24 01:52:47 PM PST 23
Peak memory 229196 kb
Host smart-1a2302fd-1aee-4b7f-888a-81070b311854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793179826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.793179826
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1401337973
Short name T1307
Test name
Test status
Simulation time 70488129 ps
CPU time 1.33 seconds
Started Dec 24 01:52:45 PM PST 23
Finished Dec 24 01:52:48 PM PST 23
Peak memory 229220 kb
Host smart-55c2c8b5-04d1-41fd-a155-ea47e12228eb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401337973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.1401337973
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.621298623
Short name T1324
Test name
Test status
Simulation time 123954856 ps
CPU time 1.45 seconds
Started Dec 24 01:52:49 PM PST 23
Finished Dec 24 01:52:58 PM PST 23
Peak memory 229236 kb
Host smart-505ff3f0-f7bb-4842-aad0-d27bf371929a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621298623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.
621298623
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1045410713
Short name T176
Test name
Test status
Simulation time 137044857 ps
CPU time 3.07 seconds
Started Dec 24 01:52:49 PM PST 23
Finished Dec 24 01:53:00 PM PST 23
Peak memory 229612 kb
Host smart-3b4fbf18-3117-4aef-a8c4-e6f005eaa70e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045410713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.1045410713
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.540544376
Short name T359
Test name
Test status
Simulation time 140304312 ps
CPU time 5.32 seconds
Started Dec 24 01:52:47 PM PST 23
Finished Dec 24 01:52:57 PM PST 23
Peak memory 241776 kb
Host smart-97b74037-327f-497d-bf00-f197ce061001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540544376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.540544376
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1281324520
Short name T312
Test name
Test status
Simulation time 1015540648 ps
CPU time 10.75 seconds
Started Dec 24 01:52:50 PM PST 23
Finished Dec 24 01:53:11 PM PST 23
Peak memory 229520 kb
Host smart-361a4ea5-8253-484d-ab74-823546b4422b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281324520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.1281324520
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1677637843
Short name T370
Test name
Test status
Simulation time 37640661 ps
CPU time 1.31 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:26 PM PST 23
Peak memory 229260 kb
Host smart-25c8c1d8-59f5-4264-b8c3-06e9ca2de455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677637843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1677637843
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.964608824
Short name T187
Test name
Test status
Simulation time 68570189 ps
CPU time 1.37 seconds
Started Dec 24 01:53:13 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229564 kb
Host smart-07d61a73-5ad1-4986-b262-7dd763aafbe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964608824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.964608824
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.283275962
Short name T252
Test name
Test status
Simulation time 72593932 ps
CPU time 1.41 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:29 PM PST 23
Peak memory 229308 kb
Host smart-860af89d-b9e0-44c5-8567-263a75116d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283275962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.283275962
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1000273803
Short name T399
Test name
Test status
Simulation time 574277045 ps
CPU time 1.57 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 229296 kb
Host smart-655bb389-88ea-4c86-a9f6-ec50022160ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000273803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1000273803
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3027587420
Short name T363
Test name
Test status
Simulation time 47443512 ps
CPU time 1.37 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229212 kb
Host smart-4bfbccd6-da78-4cc6-a69a-983ea19a8e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027587420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3027587420
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1528581650
Short name T384
Test name
Test status
Simulation time 39634241 ps
CPU time 1.41 seconds
Started Dec 24 01:53:13 PM PST 23
Finished Dec 24 01:53:19 PM PST 23
Peak memory 229440 kb
Host smart-2d058084-3fb6-48c7-a184-7a40ea007b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528581650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1528581650
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.74981745
Short name T385
Test name
Test status
Simulation time 38422639 ps
CPU time 1.35 seconds
Started Dec 24 01:53:13 PM PST 23
Finished Dec 24 01:53:19 PM PST 23
Peak memory 229424 kb
Host smart-e76d89dd-82cf-4a7c-b999-697211be5af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74981745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.74981745
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1968010948
Short name T398
Test name
Test status
Simulation time 48420811 ps
CPU time 1.35 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229144 kb
Host smart-0858ab21-9ae5-4fe0-9c80-8f04621de16d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968010948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1968010948
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.4034678651
Short name T272
Test name
Test status
Simulation time 142173608 ps
CPU time 1.29 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 228748 kb
Host smart-c568d818-7536-403c-bbc3-86aee66ccf4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034678651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.4034678651
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.825822419
Short name T354
Test name
Test status
Simulation time 57735822 ps
CPU time 1.41 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:26 PM PST 23
Peak memory 229252 kb
Host smart-f26b02d5-92da-4a06-b619-a7f42dec5d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825822419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.825822419
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1634408991
Short name T243
Test name
Test status
Simulation time 234757819 ps
CPU time 3.28 seconds
Started Dec 24 01:52:50 PM PST 23
Finished Dec 24 01:53:04 PM PST 23
Peak memory 229392 kb
Host smart-e599d64d-7d58-44a1-9dbb-08958a828e70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634408991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.1634408991
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2540132658
Short name T377
Test name
Test status
Simulation time 4350612416 ps
CPU time 9.45 seconds
Started Dec 24 01:52:47 PM PST 23
Finished Dec 24 01:53:04 PM PST 23
Peak memory 229628 kb
Host smart-b380bad5-abea-4e37-aebe-fb834b047ddc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540132658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.2540132658
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2795766619
Short name T254
Test name
Test status
Simulation time 178580629 ps
CPU time 2.07 seconds
Started Dec 24 01:52:53 PM PST 23
Finished Dec 24 01:53:04 PM PST 23
Peak memory 229468 kb
Host smart-7f636199-ecc3-4d3f-abaf-336e8a0393d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795766619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.2795766619
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3226929447
Short name T1317
Test name
Test status
Simulation time 71343200 ps
CPU time 2.16 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:13 PM PST 23
Peak memory 237808 kb
Host smart-b71b01d6-0f48-4cad-8906-1fa724abcc2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226929447 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.3226929447
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2021644477
Short name T244
Test name
Test status
Simulation time 142380504 ps
CPU time 1.69 seconds
Started Dec 24 01:52:48 PM PST 23
Finished Dec 24 01:52:58 PM PST 23
Peak memory 229468 kb
Host smart-230d0e2c-e41c-4231-814f-3a618cde979f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021644477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2021644477
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.160080976
Short name T393
Test name
Test status
Simulation time 49474584 ps
CPU time 1.5 seconds
Started Dec 24 01:52:47 PM PST 23
Finished Dec 24 01:52:56 PM PST 23
Peak memory 229380 kb
Host smart-699c5ec0-1fc1-42fa-b451-478c041ee08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160080976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.160080976
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3729869073
Short name T1315
Test name
Test status
Simulation time 39133434 ps
CPU time 1.29 seconds
Started Dec 24 01:52:59 PM PST 23
Finished Dec 24 01:53:11 PM PST 23
Peak memory 229128 kb
Host smart-8d8a60a1-5352-406c-944b-8ff0ccb56e02
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729869073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.3729869073
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1170658095
Short name T1319
Test name
Test status
Simulation time 1428459903 ps
CPU time 5 seconds
Started Dec 24 01:53:00 PM PST 23
Finished Dec 24 01:53:16 PM PST 23
Peak memory 229576 kb
Host smart-b6d1a08d-9a63-49d6-9583-a15ce8c14cf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170658095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.1170658095
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.4128020706
Short name T225
Test name
Test status
Simulation time 256786530 ps
CPU time 5.11 seconds
Started Dec 24 01:52:50 PM PST 23
Finished Dec 24 01:53:06 PM PST 23
Peak memory 237672 kb
Host smart-32ae51ed-503c-41ef-ad8d-ed8af49c8976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128020706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.4128020706
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2733213731
Short name T311
Test name
Test status
Simulation time 9361589130 ps
CPU time 19.02 seconds
Started Dec 24 01:52:47 PM PST 23
Finished Dec 24 01:53:13 PM PST 23
Peak memory 237956 kb
Host smart-e166ec80-5186-4fe3-920c-98217d5a158f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733213731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.2733213731
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.4221355820
Short name T1327
Test name
Test status
Simulation time 40097077 ps
CPU time 1.3 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229156 kb
Host smart-9173efca-41a3-4efa-9fd0-ca35dc909994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221355820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.4221355820
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1412626770
Short name T250
Test name
Test status
Simulation time 38214610 ps
CPU time 1.38 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229380 kb
Host smart-e627111d-e461-4e06-bbbd-7d3ed589da1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412626770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1412626770
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.443578851
Short name T1323
Test name
Test status
Simulation time 79660662 ps
CPU time 1.45 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229396 kb
Host smart-448ab7b7-8478-41b1-a0da-d51070731186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443578851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.443578851
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.245079116
Short name T1308
Test name
Test status
Simulation time 136696070 ps
CPU time 1.38 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 229140 kb
Host smart-1215612e-d054-4a82-93b4-a2da65b044f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245079116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.245079116
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3364581694
Short name T357
Test name
Test status
Simulation time 531276705 ps
CPU time 1.36 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 229448 kb
Host smart-17cb3180-ffd9-46f0-a994-07677d60dc28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364581694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3364581694
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1674245055
Short name T369
Test name
Test status
Simulation time 55324348 ps
CPU time 1.39 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:29 PM PST 23
Peak memory 229236 kb
Host smart-2126168e-1150-4fc5-a284-55da3ad69be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674245055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1674245055
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2110900733
Short name T1320
Test name
Test status
Simulation time 125892019 ps
CPU time 1.4 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229316 kb
Host smart-11d589ae-4225-4777-94f3-2dcfb90d2b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110900733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2110900733
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2932363579
Short name T233
Test name
Test status
Simulation time 128038167 ps
CPU time 1.35 seconds
Started Dec 24 01:53:18 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 229156 kb
Host smart-08b813f6-e15e-4466-957c-54b34139841b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932363579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2932363579
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.299699528
Short name T1325
Test name
Test status
Simulation time 501405328 ps
CPU time 1.55 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229200 kb
Host smart-428215da-6ddb-4596-a314-2eb0d9a3dfad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299699528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.299699528
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2410280395
Short name T235
Test name
Test status
Simulation time 1121934278 ps
CPU time 3.53 seconds
Started Dec 24 01:52:50 PM PST 23
Finished Dec 24 01:53:04 PM PST 23
Peak memory 229600 kb
Host smart-5036eb98-103f-42dd-a3f7-5e27a782255d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410280395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.2410280395
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.343021707
Short name T255
Test name
Test status
Simulation time 1029347564 ps
CPU time 10.06 seconds
Started Dec 24 01:52:58 PM PST 23
Finished Dec 24 01:53:19 PM PST 23
Peak memory 229488 kb
Host smart-fdd7a36b-f16e-4685-b759-d4a9b6a0771c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343021707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.343021707
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3435522502
Short name T116
Test name
Test status
Simulation time 69295207 ps
CPU time 1.72 seconds
Started Dec 24 01:52:58 PM PST 23
Finished Dec 24 01:53:11 PM PST 23
Peak memory 229420 kb
Host smart-ae3bf443-bfd7-4148-9626-f7d5bde3ab44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435522502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.3435522502
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.256328838
Short name T394
Test name
Test status
Simulation time 1116379189 ps
CPU time 3.34 seconds
Started Dec 24 01:53:12 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 237772 kb
Host smart-2ae259c4-73ad-4bc9-87b9-4d7e51e593b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256328838 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.256328838
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.712837479
Short name T113
Test name
Test status
Simulation time 42245808 ps
CPU time 1.31 seconds
Started Dec 24 01:52:57 PM PST 23
Finished Dec 24 01:53:11 PM PST 23
Peak memory 229096 kb
Host smart-5d1dd8e9-bf52-41e2-be3e-b7ed7decc759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712837479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.712837479
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1718413897
Short name T1313
Test name
Test status
Simulation time 38736710 ps
CPU time 1.3 seconds
Started Dec 24 01:52:48 PM PST 23
Finished Dec 24 01:52:57 PM PST 23
Peak memory 229200 kb
Host smart-0c61c832-b299-45ed-9d02-4bc48d415190
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718413897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.1718413897
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2934727952
Short name T1316
Test name
Test status
Simulation time 506220129 ps
CPU time 1.6 seconds
Started Dec 24 01:53:00 PM PST 23
Finished Dec 24 01:53:11 PM PST 23
Peak memory 229292 kb
Host smart-d98ef7eb-9a7d-4ed9-9f69-5a1f6b0482d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934727952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2934727952
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3322414407
Short name T188
Test name
Test status
Simulation time 147428716 ps
CPU time 2.46 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:14 PM PST 23
Peak memory 229532 kb
Host smart-6b1d0cfb-fb7f-45fa-a4d3-341271ab2eca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322414407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.3322414407
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3839724247
Short name T1311
Test name
Test status
Simulation time 500535076 ps
CPU time 6.26 seconds
Started Dec 24 01:52:59 PM PST 23
Finished Dec 24 01:53:16 PM PST 23
Peak memory 237940 kb
Host smart-d1208efb-5ea0-4e5f-8b07-4a7d721e3abf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839724247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3839724247
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2152746522
Short name T400
Test name
Test status
Simulation time 40957371 ps
CPU time 1.35 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229440 kb
Host smart-56d30995-bbb8-40e9-b0c2-9994fcdb47c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152746522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2152746522
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3293142121
Short name T111
Test name
Test status
Simulation time 516665067 ps
CPU time 1.32 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 229492 kb
Host smart-79ecc6de-65e8-4782-bcb9-6062adfea48d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293142121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3293142121
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2475869540
Short name T190
Test name
Test status
Simulation time 42649406 ps
CPU time 1.38 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229308 kb
Host smart-873041e5-3094-44f0-8839-eb334c7b7225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475869540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2475869540
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1324002690
Short name T361
Test name
Test status
Simulation time 78378093 ps
CPU time 1.4 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229488 kb
Host smart-4e78c249-2cac-4368-a349-34368615f239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324002690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1324002690
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3634217927
Short name T1331
Test name
Test status
Simulation time 75488112 ps
CPU time 1.4 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:22 PM PST 23
Peak memory 229112 kb
Host smart-7c6d2210-3bf1-41d2-9fd5-0167fe435730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634217927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3634217927
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.963573848
Short name T270
Test name
Test status
Simulation time 75298153 ps
CPU time 1.38 seconds
Started Dec 24 01:53:19 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 229212 kb
Host smart-4d74c448-0b35-472e-a537-812f633d4d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963573848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.963573848
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3958133918
Short name T373
Test name
Test status
Simulation time 553105845 ps
CPU time 1.97 seconds
Started Dec 24 01:53:20 PM PST 23
Finished Dec 24 01:53:31 PM PST 23
Peak memory 229376 kb
Host smart-a4e92206-a050-4f95-991f-371943c1280b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958133918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.3958133918
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.992654784
Short name T353
Test name
Test status
Simulation time 73433446 ps
CPU time 1.36 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:20 PM PST 23
Peak memory 229232 kb
Host smart-d04c3807-0ef0-43a4-91e9-d03e5e67f862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992654784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.992654784
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.881558530
Short name T1330
Test name
Test status
Simulation time 550985175 ps
CPU time 1.56 seconds
Started Dec 24 01:53:21 PM PST 23
Finished Dec 24 01:53:32 PM PST 23
Peak memory 229320 kb
Host smart-bc83875a-0e4d-47af-9fc8-8992c9845c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881558530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.881558530
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3777229094
Short name T262
Test name
Test status
Simulation time 399152126 ps
CPU time 2.65 seconds
Started Dec 24 01:53:00 PM PST 23
Finished Dec 24 01:53:14 PM PST 23
Peak memory 237984 kb
Host smart-179ebc6c-68e8-4e80-a5ef-882ed6bc1fc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777229094 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.3777229094
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3314343032
Short name T246
Test name
Test status
Simulation time 38827434 ps
CPU time 1.54 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:13 PM PST 23
Peak memory 229460 kb
Host smart-23e5d569-b3b4-4ca5-84e7-1adb8fe09148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314343032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3314343032
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.4038026208
Short name T1310
Test name
Test status
Simulation time 140024610 ps
CPU time 1.41 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 229256 kb
Host smart-2442ed15-08c7-49c7-baf1-ecd667523f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038026208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.4038026208
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1544969050
Short name T1312
Test name
Test status
Simulation time 944297644 ps
CPU time 1.99 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229664 kb
Host smart-8289ab7d-85bf-4ed9-8892-4e9104931b6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544969050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1544969050
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3397836231
Short name T185
Test name
Test status
Simulation time 70303734 ps
CPU time 4.97 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:16 PM PST 23
Peak memory 237840 kb
Host smart-a5ae4ca8-ff13-4ca4-8eaf-2c50eb3ee9be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397836231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3397836231
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.29782729
Short name T307
Test name
Test status
Simulation time 2980983297 ps
CPU time 24.66 seconds
Started Dec 24 01:52:59 PM PST 23
Finished Dec 24 01:53:34 PM PST 23
Peak memory 230124 kb
Host smart-e575bd50-0e0f-4928-b69e-ffb1a8998d66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29782729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg
_err.29782729
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3953544876
Short name T358
Test name
Test status
Simulation time 77215583 ps
CPU time 2.03 seconds
Started Dec 24 01:52:57 PM PST 23
Finished Dec 24 01:53:11 PM PST 23
Peak memory 237800 kb
Host smart-53ec07b8-5182-41e6-8d4f-eb1932c0c585
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953544876 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.3953544876
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.240067859
Short name T191
Test name
Test status
Simulation time 164012448 ps
CPU time 1.56 seconds
Started Dec 24 01:52:59 PM PST 23
Finished Dec 24 01:53:11 PM PST 23
Peak memory 229456 kb
Host smart-9fadfd13-cc6f-4aaa-8f25-4172d1fec43e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240067859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.240067859
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2353935215
Short name T381
Test name
Test status
Simulation time 129667054 ps
CPU time 1.31 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:13 PM PST 23
Peak memory 229220 kb
Host smart-0174f61b-1ae9-40e9-a303-49ab35cae38b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353935215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2353935215
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3830361136
Short name T259
Test name
Test status
Simulation time 43931688 ps
CPU time 1.81 seconds
Started Dec 24 01:53:02 PM PST 23
Finished Dec 24 01:53:15 PM PST 23
Peak memory 229524 kb
Host smart-34292145-f5ce-4eb7-9b29-309f17958be0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830361136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.3830361136
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.605632021
Short name T266
Test name
Test status
Simulation time 506957704 ps
CPU time 5.13 seconds
Started Dec 24 01:52:59 PM PST 23
Finished Dec 24 01:53:15 PM PST 23
Peak memory 241880 kb
Host smart-8965a786-ffdd-42f5-ab71-014d030a7cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605632021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.605632021
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1688628077
Short name T313
Test name
Test status
Simulation time 1233487720 ps
CPU time 8.67 seconds
Started Dec 24 01:53:00 PM PST 23
Finished Dec 24 01:53:18 PM PST 23
Peak memory 229668 kb
Host smart-2064e384-c82c-48cb-9949-a0cc92299016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688628077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.1688628077
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.760447633
Short name T249
Test name
Test status
Simulation time 38919689 ps
CPU time 1.54 seconds
Started Dec 24 01:53:20 PM PST 23
Finished Dec 24 01:53:31 PM PST 23
Peak memory 229500 kb
Host smart-e67949ef-ae7d-4c0e-92b0-df753e2d88db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760447633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.760447633
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.904070752
Short name T379
Test name
Test status
Simulation time 41315952 ps
CPU time 1.33 seconds
Started Dec 24 01:53:11 PM PST 23
Finished Dec 24 01:53:19 PM PST 23
Peak memory 229168 kb
Host smart-fc071fcd-57fb-4d48-a673-d392a42424c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904070752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.904070752
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2594598182
Short name T260
Test name
Test status
Simulation time 213135187 ps
CPU time 2.1 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:13 PM PST 23
Peak memory 229532 kb
Host smart-f40af88b-d615-4354-8601-7320244f29d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594598182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.2594598182
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.4079284383
Short name T182
Test name
Test status
Simulation time 199573266 ps
CPU time 3.47 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:15 PM PST 23
Peak memory 237768 kb
Host smart-b432c462-1121-4bb3-bc40-4c91a6df4c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079284383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.4079284383
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.261712586
Short name T351
Test name
Test status
Simulation time 223597049 ps
CPU time 2.09 seconds
Started Dec 24 01:53:14 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 237900 kb
Host smart-ccf4e088-bf0b-4f45-8ba2-1c3825fdab1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261712586 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.261712586
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.644212857
Short name T1329
Test name
Test status
Simulation time 513356276 ps
CPU time 1.99 seconds
Started Dec 24 01:53:17 PM PST 23
Finished Dec 24 01:53:27 PM PST 23
Peak memory 229552 kb
Host smart-288a3ce4-7d1c-4786-8983-d2556310e984
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644212857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.644212857
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.393038567
Short name T1299
Test name
Test status
Simulation time 36945145 ps
CPU time 1.33 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:12 PM PST 23
Peak memory 229508 kb
Host smart-6cc9bae8-a7bb-4c8a-9c49-4b8cb71384d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393038567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.393038567
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.340168526
Short name T383
Test name
Test status
Simulation time 83510019 ps
CPU time 1.73 seconds
Started Dec 24 01:53:01 PM PST 23
Finished Dec 24 01:53:13 PM PST 23
Peak memory 229576 kb
Host smart-15214a92-9bcd-43fc-af43-803b44876983
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340168526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct
rl_same_csr_outstanding.340168526
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3078804595
Short name T226
Test name
Test status
Simulation time 641994413 ps
CPU time 6.5 seconds
Started Dec 24 01:53:04 PM PST 23
Finished Dec 24 01:53:21 PM PST 23
Peak memory 237756 kb
Host smart-d6a031ad-cc84-4e36-a945-3c9e409a1532
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078804595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3078804595
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1085765876
Short name T232
Test name
Test status
Simulation time 19083347795 ps
CPU time 36.93 seconds
Started Dec 24 01:53:03 PM PST 23
Finished Dec 24 01:53:51 PM PST 23
Peak memory 229756 kb
Host smart-4430f33c-c920-41aa-af9c-64829170385e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085765876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.1085765876
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3271611352
Short name T1300
Test name
Test status
Simulation time 69006745 ps
CPU time 2.79 seconds
Started Dec 24 01:53:15 PM PST 23
Finished Dec 24 01:53:22 PM PST 23
Peak memory 237868 kb
Host smart-9112cdbd-07cb-447e-8383-3af7a5d70b03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271611352 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.3271611352
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3938531537
Short name T242
Test name
Test status
Simulation time 38926343 ps
CPU time 1.5 seconds
Started Dec 24 01:53:12 PM PST 23
Finished Dec 24 01:53:19 PM PST 23
Peak memory 229536 kb
Host smart-2b45e439-bb75-4912-898f-8c0c11065216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938531537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3938531537
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.2968302086
Short name T1322
Test name
Test status
Simulation time 532649460 ps
CPU time 1.66 seconds
Started Dec 24 01:53:12 PM PST 23
Finished Dec 24 01:53:19 PM PST 23
Peak memory 229140 kb
Host smart-0527e8fe-80c8-489f-8fb4-16ad3eb037bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968302086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.2968302086
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2961879915
Short name T253
Test name
Test status
Simulation time 404474218 ps
CPU time 3.07 seconds
Started Dec 24 01:53:16 PM PST 23
Finished Dec 24 01:53:26 PM PST 23
Peak memory 229636 kb
Host smart-8d0ba8d4-5f8d-44a0-aa16-3e2519d2a272
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961879915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.2961879915
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1316010194
Short name T387
Test name
Test status
Simulation time 1013362145 ps
CPU time 4.8 seconds
Started Dec 24 01:53:13 PM PST 23
Finished Dec 24 01:53:23 PM PST 23
Peak memory 237664 kb
Host smart-01500cc1-857c-40b4-b39a-f656bb2b1516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316010194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1316010194
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1504214643
Short name T386
Test name
Test status
Simulation time 2266415815 ps
CPU time 9.72 seconds
Started Dec 24 01:53:22 PM PST 23
Finished Dec 24 01:53:41 PM PST 23
Peak memory 229956 kb
Host smart-b0b6c6de-b0bb-4f5b-b6ac-74021e54e6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504214643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.1504214643
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.2017462640
Short name T100
Test name
Test status
Simulation time 1308807457 ps
CPU time 14.31 seconds
Started Dec 24 02:06:08 PM PST 23
Finished Dec 24 02:06:27 PM PST 23
Peak memory 238584 kb
Host smart-104a1d3a-893f-43a9-adb9-6d61abfc35dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017462640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.2017462640
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.1735448374
Short name T483
Test name
Test status
Simulation time 7558375382 ps
CPU time 15.02 seconds
Started Dec 24 02:06:08 PM PST 23
Finished Dec 24 02:06:29 PM PST 23
Peak memory 238576 kb
Host smart-9e967121-b46f-418c-a42a-cac2fad73d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735448374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1735448374
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.574417946
Short name T285
Test name
Test status
Simulation time 175819675 ps
CPU time 6.36 seconds
Started Dec 24 02:06:06 PM PST 23
Finished Dec 24 02:06:16 PM PST 23
Peak memory 243116 kb
Host smart-891463ef-0ae2-4382-9416-65a3cde71f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574417946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.574417946
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.1676494706
Short name T739
Test name
Test status
Simulation time 551296156 ps
CPU time 7.28 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 02:06:26 PM PST 23
Peak memory 243392 kb
Host smart-01f4f235-7309-4802-acd3-f3972e1704f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676494706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1676494706
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.1284214996
Short name T623
Test name
Test status
Simulation time 3427890218 ps
CPU time 13.36 seconds
Started Dec 24 02:05:58 PM PST 23
Finished Dec 24 02:06:14 PM PST 23
Peak memory 229800 kb
Host smart-a7ef8238-1ea8-47bd-aad6-b04da752582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284214996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1284214996
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.3912172240
Short name T891
Test name
Test status
Simulation time 3687607614 ps
CPU time 29.53 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 02:06:48 PM PST 23
Peak memory 245768 kb
Host smart-6b147c0a-3cf4-4bf8-b035-151b1467fb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912172240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3912172240
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.1784837240
Short name T1200
Test name
Test status
Simulation time 3748399412 ps
CPU time 22.32 seconds
Started Dec 24 02:06:07 PM PST 23
Finished Dec 24 02:06:35 PM PST 23
Peak memory 238584 kb
Host smart-9585bbb0-2700-4ae3-b350-e1aed5e09e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784837240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1784837240
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.2905124372
Short name T440
Test name
Test status
Simulation time 109076971 ps
CPU time 3.73 seconds
Started Dec 24 02:05:58 PM PST 23
Finished Dec 24 02:06:04 PM PST 23
Peak memory 238344 kb
Host smart-28fc8a57-24de-4450-a09d-34c188284c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905124372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2905124372
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.1913639411
Short name T820
Test name
Test status
Simulation time 3549888510 ps
CPU time 21.85 seconds
Started Dec 24 02:06:08 PM PST 23
Finished Dec 24 02:06:35 PM PST 23
Peak memory 238596 kb
Host smart-793a3c51-d965-4ede-ad1d-d08e28e4301e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913639411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.1913639411
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.1384786131
Short name T401
Test name
Test status
Simulation time 1287830816 ps
CPU time 17.16 seconds
Started Dec 24 02:05:58 PM PST 23
Finished Dec 24 02:06:18 PM PST 23
Peak memory 241116 kb
Host smart-c95e8a31-8609-4262-9634-a41a16efa5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384786131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1384786131
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.2143255805
Short name T25
Test name
Test status
Simulation time 8714650532 ps
CPU time 145.95 seconds
Started Dec 24 02:06:07 PM PST 23
Finished Dec 24 02:08:38 PM PST 23
Peak memory 264376 kb
Host smart-84fe529e-af6e-47c8-89f5-f6ec591041f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143255805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.2143255805
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.850046055
Short name T781
Test name
Test status
Simulation time 354323698 ps
CPU time 5.88 seconds
Started Dec 24 02:06:00 PM PST 23
Finished Dec 24 02:06:09 PM PST 23
Peak memory 242980 kb
Host smart-e5fa4b13-06c7-4031-ac86-eba7821e2953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850046055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.850046055
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.16170642
Short name T647
Test name
Test status
Simulation time 143069922940 ps
CPU time 3112.13 seconds
Started Dec 24 02:06:08 PM PST 23
Finished Dec 24 02:58:05 PM PST 23
Peak memory 271700 kb
Host smart-adda3245-7148-4072-a26a-410effff2d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16170642 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.16170642
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.3531477507
Short name T754
Test name
Test status
Simulation time 849337843 ps
CPU time 11.1 seconds
Started Dec 24 02:06:07 PM PST 23
Finished Dec 24 02:06:23 PM PST 23
Peak memory 237572 kb
Host smart-7c1b4b6a-cf9c-46f6-9919-c4aad451ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531477507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3531477507
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.3443570112
Short name T1204
Test name
Test status
Simulation time 147930655 ps
CPU time 1.78 seconds
Started Dec 24 02:06:02 PM PST 23
Finished Dec 24 02:06:07 PM PST 23
Peak memory 229932 kb
Host smart-e0c9be62-0e8e-4d52-85c1-7733f626c53d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3443570112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3443570112
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.270831546
Short name T597
Test name
Test status
Simulation time 140627086 ps
CPU time 1.93 seconds
Started Dec 24 02:06:10 PM PST 23
Finished Dec 24 02:06:18 PM PST 23
Peak memory 238720 kb
Host smart-03d55930-d7cd-4672-837c-36b926abd094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270831546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.270831546
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.1188993451
Short name T1256
Test name
Test status
Simulation time 6828328890 ps
CPU time 18.03 seconds
Started Dec 24 02:06:02 PM PST 23
Finished Dec 24 02:06:24 PM PST 23
Peak memory 244580 kb
Host smart-b4c3a9d4-c6ae-4c18-9c33-751efa049b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188993451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1188993451
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.3682341246
Short name T589
Test name
Test status
Simulation time 1188200804 ps
CPU time 11.7 seconds
Started Dec 24 02:06:18 PM PST 23
Finished Dec 24 02:06:36 PM PST 23
Peak memory 246400 kb
Host smart-6fcfcf12-0f66-4cf1-8c1e-0140af071c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682341246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3682341246
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.3662803562
Short name T1173
Test name
Test status
Simulation time 599528333 ps
CPU time 9.31 seconds
Started Dec 24 02:06:08 PM PST 23
Finished Dec 24 02:06:22 PM PST 23
Peak memory 237540 kb
Host smart-ca783f08-94c6-41fe-abbd-611a939ff631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662803562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3662803562
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.2515915215
Short name T1165
Test name
Test status
Simulation time 2046278636 ps
CPU time 4.29 seconds
Started Dec 24 02:06:08 PM PST 23
Finished Dec 24 02:06:18 PM PST 23
Peak memory 238412 kb
Host smart-5e37a651-f5ca-4a04-a120-2dba914b3692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515915215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2515915215
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.1483371755
Short name T822
Test name
Test status
Simulation time 1082463530 ps
CPU time 8.37 seconds
Started Dec 24 02:06:22 PM PST 23
Finished Dec 24 02:06:34 PM PST 23
Peak memory 238504 kb
Host smart-dacbe9da-b0df-4f72-b480-22fd45bb82d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483371755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.1483371755
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.788695986
Short name T1085
Test name
Test status
Simulation time 1134094320 ps
CPU time 10.67 seconds
Started Dec 24 02:06:18 PM PST 23
Finished Dec 24 02:06:35 PM PST 23
Peak memory 238588 kb
Host smart-87bef414-8022-4bc8-b143-1f851f7839d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788695986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.788695986
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.1688399788
Short name T1154
Test name
Test status
Simulation time 105569725 ps
CPU time 3.25 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 02:06:22 PM PST 23
Peak memory 241572 kb
Host smart-8cd5c91b-e2a9-432e-b16f-b3a8d13d4a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688399788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1688399788
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.2600477474
Short name T626
Test name
Test status
Simulation time 7496552814 ps
CPU time 14.81 seconds
Started Dec 24 02:06:08 PM PST 23
Finished Dec 24 02:06:27 PM PST 23
Peak memory 238604 kb
Host smart-420dfcfd-de58-4e6d-8549-4ccecbf46d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600477474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.2600477474
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.2965608828
Short name T1230
Test name
Test status
Simulation time 206543263 ps
CPU time 3.4 seconds
Started Dec 24 02:06:16 PM PST 23
Finished Dec 24 02:06:26 PM PST 23
Peak memory 241120 kb
Host smart-98b4b8d4-5d56-4ffa-a076-d515c7d8a9c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965608828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2965608828
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.3461006152
Short name T622
Test name
Test status
Simulation time 331497334 ps
CPU time 4.5 seconds
Started Dec 24 02:06:30 PM PST 23
Finished Dec 24 02:06:39 PM PST 23
Peak memory 241492 kb
Host smart-cfbdbaad-5fde-4e3c-acb0-0e9b6444d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461006152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3461006152
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3928567600
Short name T541
Test name
Test status
Simulation time 5549875000 ps
CPU time 61.82 seconds
Started Dec 24 02:06:13 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 239872 kb
Host smart-5742ee12-6b03-4823-82aa-ab41ac20bca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928567600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3928567600
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.759203820
Short name T595
Test name
Test status
Simulation time 2009872150574 ps
CPU time 8252.55 seconds
Started Dec 24 02:06:10 PM PST 23
Finished Dec 24 04:23:50 PM PST 23
Peak memory 274844 kb
Host smart-1eb75402-bddf-4d65-9d64-4eb2a3f4c244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759203820 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.759203820
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3894599729
Short name T906
Test name
Test status
Simulation time 394033598 ps
CPU time 6.28 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 02:06:25 PM PST 23
Peak memory 243436 kb
Host smart-15dfe8b3-0b2f-416a-b7d7-eab069cec9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894599729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3894599729
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.2694856274
Short name T556
Test name
Test status
Simulation time 157461211 ps
CPU time 1.61 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:03 PM PST 23
Peak memory 238424 kb
Host smart-5ff5e53c-84d8-458c-8905-74895e911a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694856274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2694856274
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.4284987852
Short name T303
Test name
Test status
Simulation time 6323190244 ps
CPU time 20.16 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 239868 kb
Host smart-15ae7b2c-c56f-4b40-81c3-d1438b094b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284987852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.4284987852
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.3328977111
Short name T976
Test name
Test status
Simulation time 1485781086 ps
CPU time 8.79 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 238504 kb
Host smart-8a146de8-f4de-449a-9642-c2e76cf81c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328977111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.3328977111
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.4080483426
Short name T65
Test name
Test status
Simulation time 458768989 ps
CPU time 4.5 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 240572 kb
Host smart-636ab953-a17c-4777-9335-7c63b07a6c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080483426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.4080483426
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.2988040213
Short name T522
Test name
Test status
Simulation time 259763871 ps
CPU time 2.68 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:02 PM PST 23
Peak memory 241124 kb
Host smart-424352ca-0c13-4c96-b1cd-bea1102f65ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988040213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.2988040213
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.792091651
Short name T696
Test name
Test status
Simulation time 5546493994 ps
CPU time 15.12 seconds
Started Dec 24 02:06:47 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 246816 kb
Host smart-336be935-2e9f-4907-9e37-31912b697c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792091651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.792091651
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.2167513995
Short name T680
Test name
Test status
Simulation time 151929159 ps
CPU time 4.09 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:10 PM PST 23
Peak memory 238324 kb
Host smart-d10f57ea-f1ac-4a84-ab69-4159383eda24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167513995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2167513995
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.1296021637
Short name T421
Test name
Test status
Simulation time 418471103 ps
CPU time 3.82 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 02:06:56 PM PST 23
Peak memory 241196 kb
Host smart-68f81277-397c-4c71-b34a-59cf63af0680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296021637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.1296021637
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.2618560257
Short name T983
Test name
Test status
Simulation time 122211589 ps
CPU time 3.87 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:06 PM PST 23
Peak memory 241124 kb
Host smart-2e6c7bfe-8250-4030-85ca-2343d6a6813f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618560257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2618560257
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.1288542074
Short name T1070
Test name
Test status
Simulation time 4492504755 ps
CPU time 11.1 seconds
Started Dec 24 02:06:47 PM PST 23
Finished Dec 24 02:07:04 PM PST 23
Peak memory 238648 kb
Host smart-6feb6bd6-96aa-462c-92f8-16243b904622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288542074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1288542074
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.2228491837
Short name T1287
Test name
Test status
Simulation time 25388551970 ps
CPU time 69.25 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:08:08 PM PST 23
Peak memory 240356 kb
Host smart-bf560551-a331-4366-937d-4bbead20c78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228491837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.2228491837
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.3659105128
Short name T1174
Test name
Test status
Simulation time 415084319231 ps
CPU time 2621.61 seconds
Started Dec 24 02:06:52 PM PST 23
Finished Dec 24 02:50:38 PM PST 23
Peak memory 304248 kb
Host smart-c566f394-500b-4a59-81dd-7d09ec7f9361
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659105128 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.3659105128
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.331584241
Short name T1053
Test name
Test status
Simulation time 1871241117 ps
CPU time 24.51 seconds
Started Dec 24 02:06:44 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 246716 kb
Host smart-4695b2e2-f46d-4fa9-b7e6-338b0b55bbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331584241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.331584241
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.2001760420
Short name T1266
Test name
Test status
Simulation time 473698754 ps
CPU time 4.09 seconds
Started Dec 24 02:08:38 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 246632 kb
Host smart-bc351f74-890e-4329-a59e-aa0af8928a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001760420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2001760420
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.1855383909
Short name T1148
Test name
Test status
Simulation time 165478630 ps
CPU time 3.56 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 238336 kb
Host smart-24aa2457-a093-4376-a1d0-e37569b9936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855383909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1855383909
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.53935357
Short name T914
Test name
Test status
Simulation time 166422004 ps
CPU time 4.27 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 238428 kb
Host smart-53222db1-dd0c-4451-98c8-bdf0843652d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53935357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.53935357
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.3504087622
Short name T916
Test name
Test status
Simulation time 221972947 ps
CPU time 4.65 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 238432 kb
Host smart-3839dcaa-52ce-4c55-a986-bc65b7cd4ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504087622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.3504087622
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2185659806
Short name T1206
Test name
Test status
Simulation time 158669149 ps
CPU time 5.08 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 238404 kb
Host smart-251c4f6d-fcf8-4546-84d1-0438ff4325e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185659806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2185659806
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.3403524143
Short name T637
Test name
Test status
Simulation time 1812591845 ps
CPU time 4.24 seconds
Started Dec 24 02:08:49 PM PST 23
Finished Dec 24 02:09:06 PM PST 23
Peak memory 240972 kb
Host smart-988f65f9-f93a-4c4a-bcdb-3b98553cb05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403524143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.3403524143
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1244307826
Short name T950
Test name
Test status
Simulation time 1673014701 ps
CPU time 5.28 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 238524 kb
Host smart-375f0524-830a-43c4-8873-612c5ea1df5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244307826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1244307826
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.1600365517
Short name T166
Test name
Test status
Simulation time 1529054153 ps
CPU time 5.13 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 241160 kb
Host smart-6e81aace-fabc-4a06-a2dc-d161636c49ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600365517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1600365517
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.147993261
Short name T692
Test name
Test status
Simulation time 210020675 ps
CPU time 4.14 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 241472 kb
Host smart-80f04c32-2322-480a-8d72-c4ff5ba6ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147993261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.147993261
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.3777260944
Short name T753
Test name
Test status
Simulation time 425867508 ps
CPU time 4.35 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 241168 kb
Host smart-21a6fd37-ef4d-4ae8-a9d1-1e60cad7ac95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777260944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.3777260944
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3177521442
Short name T1136
Test name
Test status
Simulation time 235797009 ps
CPU time 4.72 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 238376 kb
Host smart-9bb9b2d8-ff3d-4a9f-857c-5a3db2984bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177521442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3177521442
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.2895699299
Short name T1269
Test name
Test status
Simulation time 217845022 ps
CPU time 3.82 seconds
Started Dec 24 02:08:40 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 238368 kb
Host smart-0486ed00-22e8-460a-92aa-20ffd8505424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895699299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.2895699299
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3793466164
Short name T1135
Test name
Test status
Simulation time 162325730 ps
CPU time 6.2 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 242844 kb
Host smart-51f18ab8-2e3f-4258-a7d7-f3a9c43be877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793466164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3793466164
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.2423840718
Short name T762
Test name
Test status
Simulation time 299249388 ps
CPU time 4.25 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 238396 kb
Host smart-b015a9a4-7574-432e-a0bb-0b1019f5a3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423840718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2423840718
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.4036024421
Short name T167
Test name
Test status
Simulation time 4732102952 ps
CPU time 11.89 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 245148 kb
Host smart-557f4532-847b-4bda-b511-6c80c83e24a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036024421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.4036024421
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.2653680020
Short name T765
Test name
Test status
Simulation time 365655157 ps
CPU time 4.58 seconds
Started Dec 24 02:08:36 PM PST 23
Finished Dec 24 02:08:56 PM PST 23
Peak memory 241072 kb
Host smart-1e46864f-bfd4-4b3a-8135-70495ea9973d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653680020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2653680020
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3936823166
Short name T438
Test name
Test status
Simulation time 188426363 ps
CPU time 4.69 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 238408 kb
Host smart-45292bb0-e379-43c2-a8f9-63bc9ef5b54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936823166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3936823166
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.467066966
Short name T587
Test name
Test status
Simulation time 161454534 ps
CPU time 3.86 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 246552 kb
Host smart-938c06bd-1a8d-4a20-b371-5bcc32c3aa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467066966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.467066966
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.1878111230
Short name T996
Test name
Test status
Simulation time 526385779 ps
CPU time 7.57 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:53 PM PST 23
Peak memory 238468 kb
Host smart-12fa95ac-00a0-4c20-bbaf-f6162f26f1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878111230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.1878111230
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.1478520993
Short name T280
Test name
Test status
Simulation time 183559012 ps
CPU time 1.91 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:02 PM PST 23
Peak memory 238564 kb
Host smart-88350718-6176-48cb-8a42-80205e9b3adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478520993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.1478520993
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.614824129
Short name T44
Test name
Test status
Simulation time 1377640763 ps
CPU time 11.77 seconds
Started Dec 24 02:06:44 PM PST 23
Finished Dec 24 02:06:58 PM PST 23
Peak memory 246620 kb
Host smart-540be1c0-4fbb-47a3-b40b-a27fcd1bc0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614824129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.614824129
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1138681897
Short name T1082
Test name
Test status
Simulation time 299455181 ps
CPU time 8.79 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:12 PM PST 23
Peak memory 244484 kb
Host smart-dac8554a-3f22-479c-b439-81f0b17ca264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138681897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1138681897
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.2124165763
Short name T728
Test name
Test status
Simulation time 11014369431 ps
CPU time 17.21 seconds
Started Dec 24 02:06:42 PM PST 23
Finished Dec 24 02:07:00 PM PST 23
Peak memory 237772 kb
Host smart-13bd58a8-731a-462b-8eea-5dddbc7a67cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124165763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.2124165763
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.2044421636
Short name T860
Test name
Test status
Simulation time 414788046 ps
CPU time 3.13 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:02 PM PST 23
Peak memory 240764 kb
Host smart-e07bbba8-a0e0-4b45-98f6-3bd8b12a999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044421636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.2044421636
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.1494371367
Short name T493
Test name
Test status
Simulation time 369099864 ps
CPU time 7.07 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:06:52 PM PST 23
Peak memory 244184 kb
Host smart-0f6156b3-57a5-44b8-96e8-f8c363dbab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494371367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1494371367
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.3470348476
Short name T878
Test name
Test status
Simulation time 1545856449 ps
CPU time 8.39 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:19 PM PST 23
Peak memory 243568 kb
Host smart-a2e6ec6a-c47f-4f6d-993e-5503d3aeb850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470348476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.3470348476
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.2404928364
Short name T296
Test name
Test status
Simulation time 3229902470 ps
CPU time 11.15 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:14 PM PST 23
Peak memory 238528 kb
Host smart-e09fab99-29f1-48a9-84df-97811e2e7b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404928364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2404928364
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.2211737270
Short name T343
Test name
Test status
Simulation time 855792942 ps
CPU time 11.15 seconds
Started Dec 24 02:06:41 PM PST 23
Finished Dec 24 02:06:53 PM PST 23
Peak memory 238516 kb
Host smart-9b8fb99f-c813-4928-aa47-f6fb045d7b67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211737270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.2211737270
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.3200535848
Short name T1226
Test name
Test status
Simulation time 187395848 ps
CPU time 5.09 seconds
Started Dec 24 02:06:44 PM PST 23
Finished Dec 24 02:06:51 PM PST 23
Peak memory 238568 kb
Host smart-93124f08-f530-476e-b1d9-d9f86c0fd084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3200535848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.3200535848
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.4123892266
Short name T602
Test name
Test status
Simulation time 334841891 ps
CPU time 5.21 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:06:54 PM PST 23
Peak memory 243380 kb
Host smart-bb84855c-2f8d-42ba-b616-6446e1a131fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123892266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.4123892266
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.543503447
Short name T323
Test name
Test status
Simulation time 19082320427 ps
CPU time 135.43 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:09:18 PM PST 23
Peak memory 240472 kb
Host smart-1a88160c-6e61-4c9d-a8b2-83fd7ebc4159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543503447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.
543503447
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.4179617553
Short name T779
Test name
Test status
Simulation time 517801341678 ps
CPU time 8144.59 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 04:22:30 PM PST 23
Peak memory 309768 kb
Host smart-e7ba08a5-d678-456a-97a6-c466390f946f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179617553 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.4179617553
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.869472046
Short name T980
Test name
Test status
Simulation time 4453047666 ps
CPU time 25.41 seconds
Started Dec 24 02:06:47 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 244696 kb
Host smart-8d0a89d0-5a34-4d80-b7e6-5beede1f40bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869472046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.869472046
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.234339664
Short name T1067
Test name
Test status
Simulation time 515092361 ps
CPU time 4.05 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 238596 kb
Host smart-7368a030-dc02-4d43-baf4-a76329d097cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234339664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.234339664
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.4098320601
Short name T1160
Test name
Test status
Simulation time 121217964 ps
CPU time 2.99 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 240896 kb
Host smart-2e723f69-b83c-4528-b54c-620b9e120b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098320601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.4098320601
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.1052284628
Short name T1234
Test name
Test status
Simulation time 615519486 ps
CPU time 4.43 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 238476 kb
Host smart-8da5f329-4fc9-4c25-b519-276c197efd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052284628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.1052284628
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.2756812469
Short name T404
Test name
Test status
Simulation time 2746532675 ps
CPU time 5.18 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 242928 kb
Host smart-8d60998a-516f-42b5-aa93-2552532c2c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756812469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2756812469
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.2968915548
Short name T766
Test name
Test status
Simulation time 551417170 ps
CPU time 3.77 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 240856 kb
Host smart-7e8d1ef6-8490-423e-9379-424ef84566a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968915548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.2968915548
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.4050836985
Short name T952
Test name
Test status
Simulation time 241630744 ps
CPU time 4.23 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 242508 kb
Host smart-d9c87be4-0864-4363-a44f-0a0121f525d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050836985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.4050836985
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3514036399
Short name T59
Test name
Test status
Simulation time 136258881 ps
CPU time 3.99 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 241112 kb
Host smart-e272c4e7-134b-42a2-9441-9d98ada608d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514036399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3514036399
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.19278142
Short name T485
Test name
Test status
Simulation time 167897060 ps
CPU time 3.97 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 238452 kb
Host smart-b17d9919-d160-4638-8e03-b3f350833581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19278142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.19278142
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.1965006136
Short name T135
Test name
Test status
Simulation time 301633071 ps
CPU time 4.62 seconds
Started Dec 24 02:08:49 PM PST 23
Finished Dec 24 02:09:06 PM PST 23
Peak memory 240956 kb
Host smart-f8668f1e-9395-4e08-bef4-97c70e36e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965006136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.1965006136
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.1479547024
Short name T1035
Test name
Test status
Simulation time 166891746 ps
CPU time 3.95 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 237884 kb
Host smart-97e8e667-b7ac-43e1-a1eb-b22c05ff97f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479547024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.1479547024
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.2305900447
Short name T1252
Test name
Test status
Simulation time 299691198 ps
CPU time 3.28 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:40 PM PST 23
Peak memory 240892 kb
Host smart-98968c57-f5f3-41a1-acee-ad3123a23173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305900447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2305900447
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3077635094
Short name T441
Test name
Test status
Simulation time 188985925 ps
CPU time 4.64 seconds
Started Dec 24 02:08:46 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 241672 kb
Host smart-d5562af2-4175-40fd-ac21-464f1cd05747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077635094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3077635094
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.1158020708
Short name T708
Test name
Test status
Simulation time 314012439 ps
CPU time 3.36 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 238508 kb
Host smart-af48a83d-8c63-4be9-84e6-40664345a975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158020708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1158020708
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.2053453151
Short name T641
Test name
Test status
Simulation time 149172552 ps
CPU time 3.23 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 242852 kb
Host smart-761872b0-808a-45dc-ac0a-48eb8a7df953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053453151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.2053453151
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.1042150586
Short name T464
Test name
Test status
Simulation time 214104992 ps
CPU time 3.41 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 238372 kb
Host smart-3bbced12-f0e6-47c7-a2dc-544c5ac69b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042150586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.1042150586
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.2856529358
Short name T1293
Test name
Test status
Simulation time 200568911 ps
CPU time 4.04 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 238516 kb
Host smart-942a41f8-e640-45b1-a1c1-2fd1a3eef85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856529358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.2856529358
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2110859194
Short name T557
Test name
Test status
Simulation time 84950399 ps
CPU time 2.47 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 240864 kb
Host smart-8759a16b-1ec5-4e3c-8720-8520d1940fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110859194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2110859194
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.685751093
Short name T1286
Test name
Test status
Simulation time 757837646 ps
CPU time 4.2 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 238448 kb
Host smart-c675ea43-b7a3-4ca2-87cf-824f80fbab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685751093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.685751093
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.3185045250
Short name T794
Test name
Test status
Simulation time 2122504885 ps
CPU time 6.59 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:50 PM PST 23
Peak memory 238252 kb
Host smart-cae515af-441a-4d80-9eea-31e4d7be444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185045250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.3185045250
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.2707707762
Short name T450
Test name
Test status
Simulation time 119964219 ps
CPU time 1.42 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:03 PM PST 23
Peak memory 238232 kb
Host smart-b5262149-7af9-4309-9df4-0e0df350d193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707707762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.2707707762
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.1730605918
Short name T76
Test name
Test status
Simulation time 2457775069 ps
CPU time 19.18 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 238668 kb
Host smart-acb055c4-8f97-4c4c-af1e-ce41aca7abc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730605918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.1730605918
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.384075077
Short name T731
Test name
Test status
Simulation time 207515220 ps
CPU time 4.55 seconds
Started Dec 24 02:06:40 PM PST 23
Finished Dec 24 02:06:46 PM PST 23
Peak memory 238424 kb
Host smart-175d77e3-e407-46ab-9639-b27a06e6b0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384075077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.384075077
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.136586538
Short name T1270
Test name
Test status
Simulation time 346700505 ps
CPU time 9.07 seconds
Started Dec 24 02:06:42 PM PST 23
Finished Dec 24 02:06:51 PM PST 23
Peak memory 245756 kb
Host smart-d8ef0db4-f94e-4595-9819-377d67673122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136586538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.136586538
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.3659878470
Short name T769
Test name
Test status
Simulation time 143265032 ps
CPU time 3.88 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 02:06:55 PM PST 23
Peak memory 238384 kb
Host smart-5065cf08-cc7c-42c5-be0c-a38a3c3b6974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659878470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3659878470
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.995914036
Short name T620
Test name
Test status
Simulation time 3675801854 ps
CPU time 7.83 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 238516 kb
Host smart-0d7d6147-729a-4485-a4ee-c6ed7d4290be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995914036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.995914036
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.3101902008
Short name T510
Test name
Test status
Simulation time 264943065 ps
CPU time 6.91 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:07:04 PM PST 23
Peak memory 238580 kb
Host smart-df6deef7-0956-487d-91cf-b6517e40c7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101902008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3101902008
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.3148082012
Short name T661
Test name
Test status
Simulation time 1360777171 ps
CPU time 9.49 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 02:07:02 PM PST 23
Peak memory 238456 kb
Host smart-c5dfd23b-6b32-4ca0-a0b6-4fe042cee723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148082012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.3148082012
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.1386776586
Short name T96
Test name
Test status
Simulation time 6487326300 ps
CPU time 11.66 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:13 PM PST 23
Peak memory 244476 kb
Host smart-9d50cf29-0090-4c4e-b7c6-b71b920d1522
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386776586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1386776586
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1297537844
Short name T576
Test name
Test status
Simulation time 682145211 ps
CPU time 9.94 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 02:07:01 PM PST 23
Peak memory 246716 kb
Host smart-2c047d08-5840-46ea-b0bf-fafac93addc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1297537844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1297537844
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.1936162914
Short name T474
Test name
Test status
Simulation time 1165488850 ps
CPU time 7.23 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:06:51 PM PST 23
Peak memory 243512 kb
Host smart-77272deb-873d-4773-95e6-6728b34cadce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936162914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1936162914
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.431105274
Short name T1190
Test name
Test status
Simulation time 1486000337 ps
CPU time 23.87 seconds
Started Dec 24 02:06:53 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 244496 kb
Host smart-c8a8b70e-2765-464e-90c7-935c2071ed96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431105274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.
431105274
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.132230054
Short name T463
Test name
Test status
Simulation time 1788873558 ps
CPU time 10.27 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 238400 kb
Host smart-c0b0a6a4-2393-4578-86fe-851609beb11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132230054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.132230054
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.4090385003
Short name T866
Test name
Test status
Simulation time 218211803 ps
CPU time 4.39 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 238512 kb
Host smart-d09f8077-ee45-4379-8b05-fdace4c5361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090385003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.4090385003
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.2082672710
Short name T1163
Test name
Test status
Simulation time 3514021035 ps
CPU time 10.47 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 243728 kb
Host smart-090f3dea-a1cb-4617-b655-e11c703504bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082672710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2082672710
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.4003016710
Short name T745
Test name
Test status
Simulation time 496082221 ps
CPU time 4.11 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:08:38 PM PST 23
Peak memory 242136 kb
Host smart-11a650bb-afab-4440-b423-f6689c611dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003016710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.4003016710
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.946855797
Short name T80
Test name
Test status
Simulation time 203982304 ps
CPU time 4.82 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 238524 kb
Host smart-66f43932-9058-4881-ad69-6ff6f3bc4f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946855797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.946855797
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.874325144
Short name T1240
Test name
Test status
Simulation time 2902569092 ps
CPU time 5.14 seconds
Started Dec 24 02:08:34 PM PST 23
Finished Dec 24 02:08:54 PM PST 23
Peak memory 238588 kb
Host smart-cbe9e0d7-7bd1-487d-be89-6b4dbd4b24d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874325144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.874325144
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.3581326152
Short name T1145
Test name
Test status
Simulation time 149214554 ps
CPU time 3.76 seconds
Started Dec 24 02:08:47 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 238480 kb
Host smart-b7413f3e-1b82-4459-9e7e-c422b2f4c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581326152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3581326152
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.97221128
Short name T347
Test name
Test status
Simulation time 219063255 ps
CPU time 3.33 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 238388 kb
Host smart-c3405906-a938-46f3-af78-268609dbd616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97221128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.97221128
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.1201835030
Short name T525
Test name
Test status
Simulation time 111557217 ps
CPU time 3.34 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 238416 kb
Host smart-eb6916d4-fcf2-44b0-91e9-91b28e3ca36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201835030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1201835030
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.354234255
Short name T736
Test name
Test status
Simulation time 142832431 ps
CPU time 4.5 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 240364 kb
Host smart-a989eba7-b1c5-47c4-9d13-52d5647f52e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354234255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.354234255
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1400761655
Short name T406
Test name
Test status
Simulation time 610662997 ps
CPU time 4.06 seconds
Started Dec 24 02:08:17 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 238460 kb
Host smart-07a2d638-8d69-4ff8-b883-8b3f6c29e521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400761655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1400761655
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.14000781
Short name T1212
Test name
Test status
Simulation time 431456944 ps
CPU time 6.04 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 238360 kb
Host smart-f4ee5ade-209a-4934-bd1d-57df8a41205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14000781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.14000781
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.4075352235
Short name T1225
Test name
Test status
Simulation time 149730906 ps
CPU time 3.46 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 241064 kb
Host smart-82e7d958-e28b-46b1-9c7e-2c708a812377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075352235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.4075352235
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.1873102586
Short name T1008
Test name
Test status
Simulation time 2767671430 ps
CPU time 7.76 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 238592 kb
Host smart-02c3504f-5df9-4580-8658-24291b34aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873102586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.1873102586
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.4204041054
Short name T452
Test name
Test status
Simulation time 1810069829 ps
CPU time 4.21 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 238344 kb
Host smart-bd1803a8-55f5-486e-886f-61682249badc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204041054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.4204041054
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3853802230
Short name T615
Test name
Test status
Simulation time 966012609 ps
CPU time 6.07 seconds
Started Dec 24 02:08:25 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 238320 kb
Host smart-f3e33612-956c-4711-a0aa-06eaa791f417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853802230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3853802230
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.218180894
Short name T1087
Test name
Test status
Simulation time 189291902 ps
CPU time 4.21 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:08:39 PM PST 23
Peak memory 238452 kb
Host smart-a8f3c8e0-fdff-44ce-954b-7b908e38f882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218180894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.218180894
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.3608067308
Short name T151
Test name
Test status
Simulation time 257165994 ps
CPU time 4.98 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 246724 kb
Host smart-3e33c1a2-ec84-4bd4-bf2e-e42426bf9a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608067308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.3608067308
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.1822576344
Short name T12
Test name
Test status
Simulation time 147964147 ps
CPU time 2.06 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:10 PM PST 23
Peak memory 238800 kb
Host smart-0ba7cfb5-ccdf-4fd1-923d-9c0ec7f6d758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822576344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1822576344
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.13612566
Short name T624
Test name
Test status
Simulation time 129816320 ps
CPU time 3.28 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 244524 kb
Host smart-8422400c-b144-406e-aebf-817ce4eb4844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13612566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.13612566
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.425820657
Short name T276
Test name
Test status
Simulation time 819785447 ps
CPU time 6.02 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:06 PM PST 23
Peak memory 241792 kb
Host smart-86e9ee44-2f0c-4fe7-a688-2886b844a9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425820657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.425820657
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.109909223
Short name T1241
Test name
Test status
Simulation time 704977586 ps
CPU time 3.86 seconds
Started Dec 24 02:06:42 PM PST 23
Finished Dec 24 02:06:47 PM PST 23
Peak memory 243800 kb
Host smart-6045440f-477e-466a-977f-d4ff22366d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109909223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.109909223
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.3479849482
Short name T1041
Test name
Test status
Simulation time 489940485 ps
CPU time 4.75 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:06:53 PM PST 23
Peak memory 238384 kb
Host smart-5a241764-dcc1-41f7-8f69-8765b55c602d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479849482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.3479849482
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.467158030
Short name T420
Test name
Test status
Simulation time 2061994834 ps
CPU time 20.81 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 246808 kb
Host smart-8bbf88c3-ab91-4ac3-b617-faf35e6ece50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467158030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.467158030
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.601986929
Short name T1115
Test name
Test status
Simulation time 1596225897 ps
CPU time 9.35 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:13 PM PST 23
Peak memory 238656 kb
Host smart-f46e1508-69d7-4a7c-9932-a002a9f77b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601986929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.601986929
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.4032979872
Short name T832
Test name
Test status
Simulation time 109183466 ps
CPU time 3.49 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 02:06:56 PM PST 23
Peak memory 241580 kb
Host smart-bf71a229-81f1-4c42-b485-c35e0f3c98ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032979872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.4032979872
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.2959986246
Short name T1131
Test name
Test status
Simulation time 774358510 ps
CPU time 6.29 seconds
Started Dec 24 02:06:42 PM PST 23
Finished Dec 24 02:06:50 PM PST 23
Peak memory 238496 kb
Host smart-bffc786e-6668-43bd-bd7b-9215472bc94c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2959986246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2959986246
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.3715400117
Short name T931
Test name
Test status
Simulation time 205006654 ps
CPU time 6.66 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:07 PM PST 23
Peak memory 243576 kb
Host smart-9a6abc35-e1b0-40b3-9127-82404f6b8d77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715400117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.3715400117
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.1668535324
Short name T458
Test name
Test status
Simulation time 600179266 ps
CPU time 5.91 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 02:06:58 PM PST 23
Peak memory 238516 kb
Host smart-1a52e25c-54f9-4d45-8d7e-21e43f67a2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668535324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1668535324
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.2646008245
Short name T1072
Test name
Test status
Simulation time 27957168370 ps
CPU time 136.05 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 260608 kb
Host smart-b22fd07e-d507-41a6-bd77-4685aa457bb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646008245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.2646008245
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.1501223502
Short name T1187
Test name
Test status
Simulation time 2299481849675 ps
CPU time 4166.51 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 03:16:36 PM PST 23
Peak memory 543216 kb
Host smart-368619b5-a3b9-4362-bb53-63ebb2c68e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501223502 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.1501223502
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.303161395
Short name T1022
Test name
Test status
Simulation time 553008828 ps
CPU time 15.3 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:19 PM PST 23
Peak memory 237580 kb
Host smart-9b5fbc78-57f7-4756-acb3-2c1d14361eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303161395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.303161395
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.2941235665
Short name T1171
Test name
Test status
Simulation time 305857029 ps
CPU time 4.23 seconds
Started Dec 24 02:08:20 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 238392 kb
Host smart-12abb437-6f85-4b7d-84f2-9795fe1176ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941235665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2941235665
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.324339306
Short name T201
Test name
Test status
Simulation time 179141535 ps
CPU time 7.07 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 238308 kb
Host smart-cbe36979-5a32-44c4-8554-f32075939835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324339306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.324339306
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.611744744
Short name T491
Test name
Test status
Simulation time 315239100 ps
CPU time 3.96 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 240948 kb
Host smart-918ad273-e3f9-49ee-8a0e-9bec50f8699f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611744744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.611744744
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.2858011232
Short name T1213
Test name
Test status
Simulation time 1974765224 ps
CPU time 5.73 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 238416 kb
Host smart-4e9a9c63-f53e-42f1-b9b4-072c19cbcfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858011232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.2858011232
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.1653804464
Short name T536
Test name
Test status
Simulation time 1783641229 ps
CPU time 4.76 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 240568 kb
Host smart-1f2eac8b-c91d-4c57-bb41-05a65a000309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653804464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1653804464
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.2652826037
Short name T870
Test name
Test status
Simulation time 503110206 ps
CPU time 6.83 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 243228 kb
Host smart-4af0b5fc-d30b-44a5-b8b8-3345df534ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652826037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2652826037
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.2986166441
Short name T1192
Test name
Test status
Simulation time 143983670 ps
CPU time 3.63 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 241060 kb
Host smart-4e1748c4-c797-4271-b013-f126527f0f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986166441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2986166441
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.1221611496
Short name T999
Test name
Test status
Simulation time 302326992 ps
CPU time 2.89 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 238444 kb
Host smart-86fa18f4-fbf0-4dc5-85d6-f71557d79bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221611496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1221611496
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.512398865
Short name T1147
Test name
Test status
Simulation time 158128544 ps
CPU time 3.65 seconds
Started Dec 24 02:08:40 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 238348 kb
Host smart-028ff3d5-0e50-4069-ad3c-553683c3baae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512398865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.512398865
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.4203162234
Short name T793
Test name
Test status
Simulation time 326184812 ps
CPU time 4.44 seconds
Started Dec 24 02:08:24 PM PST 23
Finished Dec 24 02:08:40 PM PST 23
Peak memory 242400 kb
Host smart-f95b7e80-c553-4b69-95c3-2e45bcc8022f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203162234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.4203162234
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.411736883
Short name T880
Test name
Test status
Simulation time 177006282 ps
CPU time 3.23 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 241044 kb
Host smart-dac6ff3c-c0ec-4c82-a2c3-83cc7a09362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411736883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.411736883
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.2231988449
Short name T88
Test name
Test status
Simulation time 534889535 ps
CPU time 6.82 seconds
Started Dec 24 02:08:36 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 238508 kb
Host smart-22e4dd73-99f4-419e-b40b-a01c598e51a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231988449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2231988449
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.1285001960
Short name T1277
Test name
Test status
Simulation time 190913720 ps
CPU time 3.45 seconds
Started Dec 24 02:08:42 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 240944 kb
Host smart-26fe68de-3803-4578-8d2a-c37b7d65f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285001960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1285001960
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.2733253630
Short name T1029
Test name
Test status
Simulation time 255243765 ps
CPU time 3.65 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 242048 kb
Host smart-27e219e4-849f-48bf-aa37-a2547413bd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733253630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2733253630
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.2825333296
Short name T1282
Test name
Test status
Simulation time 204151626 ps
CPU time 4.02 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 238392 kb
Host smart-c1f2f3be-687b-4b4e-bbb2-d70190ce75b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825333296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2825333296
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.2709689978
Short name T1028
Test name
Test status
Simulation time 1213533451 ps
CPU time 2.95 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 240916 kb
Host smart-2c0858b1-2aa9-4a32-bffa-622676390719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709689978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2709689978
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.2837517918
Short name T669
Test name
Test status
Simulation time 165398805 ps
CPU time 3.95 seconds
Started Dec 24 02:08:52 PM PST 23
Finished Dec 24 02:09:08 PM PST 23
Peak memory 238400 kb
Host smart-6f358e46-3f08-4d27-a049-3ec67bfc3b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837517918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2837517918
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.738705122
Short name T345
Test name
Test status
Simulation time 157607926 ps
CPU time 3.53 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:50 PM PST 23
Peak memory 246592 kb
Host smart-e28588c4-1818-4b4d-bde5-92aebf55aeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738705122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.738705122
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.1977149242
Short name T908
Test name
Test status
Simulation time 149792775 ps
CPU time 3.67 seconds
Started Dec 24 02:08:40 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 238448 kb
Host smart-9fe1415b-21dc-401f-aaad-3143ce7bcc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977149242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1977149242
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.218047148
Short name T887
Test name
Test status
Simulation time 157974893 ps
CPU time 4.05 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 246560 kb
Host smart-99f512cc-faa8-4b74-a0e3-417d804bd4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218047148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.218047148
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.3100987505
Short name T631
Test name
Test status
Simulation time 209328107 ps
CPU time 1.85 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:06:59 PM PST 23
Peak memory 238744 kb
Host smart-b7a29c2e-a261-47c8-a4b9-03dd617a7890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100987505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3100987505
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.2709230325
Short name T671
Test name
Test status
Simulation time 597027015 ps
CPU time 7.96 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 244464 kb
Host smart-3092a552-dc86-469c-91eb-46e6464038d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709230325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.2709230325
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.406249086
Short name T872
Test name
Test status
Simulation time 1001095757 ps
CPU time 15.46 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 238528 kb
Host smart-e65f030b-5329-47bb-adfb-a326d130ffba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406249086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.406249086
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.27173279
Short name T601
Test name
Test status
Simulation time 891438879 ps
CPU time 11.55 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 245448 kb
Host smart-149935f7-3084-4f03-b47d-5624352ceb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27173279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.27173279
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.205130773
Short name T871
Test name
Test status
Simulation time 325787507 ps
CPU time 7.03 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 239820 kb
Host smart-3f613619-9a50-4fa7-bb18-2a78ccf99f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205130773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.205130773
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.63781376
Short name T297
Test name
Test status
Simulation time 350776925 ps
CPU time 4.3 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:14 PM PST 23
Peak memory 242544 kb
Host smart-9270653d-80f0-41ea-9bf9-1e11dbf93dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63781376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.63781376
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.4221713398
Short name T543
Test name
Test status
Simulation time 1627157413 ps
CPU time 11.03 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:12 PM PST 23
Peak memory 238540 kb
Host smart-0e4439e1-51fd-4904-9a7d-aee0664e1a48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221713398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.4221713398
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.1166296463
Short name T317
Test name
Test status
Simulation time 834256886 ps
CPU time 5.65 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:04 PM PST 23
Peak memory 238464 kb
Host smart-2ca26db9-5bc8-4523-a6bc-4182390ea446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166296463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1166296463
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.4244860615
Short name T657
Test name
Test status
Simulation time 276012021 ps
CPU time 4.05 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:04 PM PST 23
Peak memory 246736 kb
Host smart-9eb6097d-664c-4c09-a980-063a6d5e13ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244860615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.4244860615
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.2186655141
Short name T499
Test name
Test status
Simulation time 10676680555 ps
CPU time 72.3 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:08:10 PM PST 23
Peak memory 246896 kb
Host smart-b54a9c94-75b6-4ad5-86f3-4c7600203563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186655141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.2186655141
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.2621994041
Short name T907
Test name
Test status
Simulation time 338400716576 ps
CPU time 1811.19 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:37:09 PM PST 23
Peak memory 324240 kb
Host smart-c2a237f1-6d95-498d-94c6-f6512bb395b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621994041 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.2621994041
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.1467137749
Short name T869
Test name
Test status
Simulation time 703779962 ps
CPU time 10.59 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 238524 kb
Host smart-2f6898f5-3bda-437d-af8e-dab416394a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467137749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1467137749
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.1330339319
Short name T773
Test name
Test status
Simulation time 185511819 ps
CPU time 4.29 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 238448 kb
Host smart-474ead99-2bad-4024-94b2-17acf49120b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330339319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.1330339319
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.530475307
Short name T542
Test name
Test status
Simulation time 86895025 ps
CPU time 3.06 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 242212 kb
Host smart-1b8df7dc-0833-4b8b-bcb2-ad1bc53691a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530475307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.530475307
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.219285897
Short name T578
Test name
Test status
Simulation time 2559012863 ps
CPU time 6.11 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 241844 kb
Host smart-39680979-8750-4d69-89a7-c60641865235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219285897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.219285897
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.2075793023
Short name T328
Test name
Test status
Simulation time 431871757 ps
CPU time 4.13 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:49 PM PST 23
Peak memory 242900 kb
Host smart-274badd3-c9b0-44a4-9539-68685a7c18dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075793023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2075793023
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.2354679403
Short name T1264
Test name
Test status
Simulation time 646201279 ps
CPU time 4.14 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 238476 kb
Host smart-d4d7e39e-25ee-4537-bbe2-a760343e6991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354679403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2354679403
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.3145188455
Short name T969
Test name
Test status
Simulation time 123493798 ps
CPU time 3.91 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 238432 kb
Host smart-7661f067-7a89-4954-a573-c674d79f2dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145188455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3145188455
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3621071047
Short name T564
Test name
Test status
Simulation time 350204071 ps
CPU time 6.45 seconds
Started Dec 24 02:08:36 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 243064 kb
Host smart-531b4d5b-1ea3-4487-ab6b-82a789998230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621071047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3621071047
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.129914140
Short name T146
Test name
Test status
Simulation time 614356174 ps
CPU time 4.09 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 238456 kb
Host smart-48ee1c8d-c4c6-4803-b5a5-3dac0860d7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129914140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.129914140
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1229439875
Short name T1227
Test name
Test status
Simulation time 1284725364 ps
CPU time 4.93 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 238456 kb
Host smart-b68ed828-47cd-4405-8f1b-d3250360eb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229439875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1229439875
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.1677812443
Short name T829
Test name
Test status
Simulation time 298763232 ps
CPU time 4.17 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 238468 kb
Host smart-5294ffea-4b77-4512-be2c-d1b874e69a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677812443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.1677812443
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.1733876649
Short name T423
Test name
Test status
Simulation time 193646937 ps
CPU time 4.91 seconds
Started Dec 24 02:08:42 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 242600 kb
Host smart-50338abc-b003-46b2-8ae9-cd146f38fb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733876649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.1733876649
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.3580302001
Short name T681
Test name
Test status
Simulation time 346525480 ps
CPU time 4.26 seconds
Started Dec 24 02:08:47 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 241252 kb
Host smart-f890c85d-4e68-4a3b-bb15-a34b8463842d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580302001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3580302001
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.180281535
Short name T344
Test name
Test status
Simulation time 258800652 ps
CPU time 3.07 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 241228 kb
Host smart-0db45d17-a221-4071-bfc0-8eb645267c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180281535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.180281535
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.3291928574
Short name T1014
Test name
Test status
Simulation time 242135800 ps
CPU time 3.36 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 238516 kb
Host smart-c0298653-9a2d-4cab-ad87-40cb659e8b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291928574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3291928574
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.2327051692
Short name T407
Test name
Test status
Simulation time 5650686150 ps
CPU time 13.65 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 246452 kb
Host smart-4d215689-2611-4609-b65d-794b9bf8f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327051692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2327051692
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.506267051
Short name T78
Test name
Test status
Simulation time 2530324869 ps
CPU time 5.58 seconds
Started Dec 24 02:08:34 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 241712 kb
Host smart-60c760d9-5779-480c-a89a-eb2882a7e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506267051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.506267051
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2404255563
Short name T813
Test name
Test status
Simulation time 194269007 ps
CPU time 2.54 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 238464 kb
Host smart-2188c010-62e7-4ac4-87a8-4a23125a0403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404255563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2404255563
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.2014258244
Short name T633
Test name
Test status
Simulation time 355019867 ps
CPU time 3.84 seconds
Started Dec 24 02:08:45 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 238460 kb
Host smart-edcd7c28-d9fe-47b7-9e58-d3fa9e86abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014258244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2014258244
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.591994761
Short name T856
Test name
Test status
Simulation time 490247159 ps
CPU time 4.28 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 243328 kb
Host smart-0796a434-6b11-4424-88f9-125c4d065da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591994761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.591994761
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.1852343483
Short name T514
Test name
Test status
Simulation time 62406062 ps
CPU time 1.63 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 239336 kb
Host smart-320bf3a8-4ca5-4ad1-bcb3-7904db2e959c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852343483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1852343483
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.1202094605
Short name T77
Test name
Test status
Simulation time 3567637825 ps
CPU time 14.94 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:15 PM PST 23
Peak memory 238668 kb
Host smart-da10b313-809e-495d-9c9b-71fffa47154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202094605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1202094605
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.2601394086
Short name T1263
Test name
Test status
Simulation time 325394756 ps
CPU time 9.03 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:13 PM PST 23
Peak memory 238276 kb
Host smart-25ba3f9f-7caa-4b79-9e70-b95effff54c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601394086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2601394086
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.3176697796
Short name T735
Test name
Test status
Simulation time 538277090 ps
CPU time 7.81 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 237600 kb
Host smart-cba0634c-e1f7-4724-b76c-86f75a68d0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176697796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.3176697796
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.1098132522
Short name T43
Test name
Test status
Simulation time 494907263 ps
CPU time 3.75 seconds
Started Dec 24 02:07:09 PM PST 23
Finished Dec 24 02:07:22 PM PST 23
Peak memory 238508 kb
Host smart-5894306b-e9b7-4335-8e5b-d86b5e05636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098132522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1098132522
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.978638581
Short name T546
Test name
Test status
Simulation time 2332096135 ps
CPU time 20.72 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:28 PM PST 23
Peak memory 245988 kb
Host smart-592a4b5e-3500-4305-96f7-f7471c2b1548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978638581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.978638581
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.1346893149
Short name T1141
Test name
Test status
Simulation time 2466499315 ps
CPU time 9.51 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:12 PM PST 23
Peak memory 245992 kb
Host smart-04465aa1-5d7a-4b4f-b661-754bd45b68df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346893149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1346893149
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.3073896673
Short name T750
Test name
Test status
Simulation time 4066178118 ps
CPU time 7.38 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 238636 kb
Host smart-0e9947b8-d0ae-419e-88e2-99cd14ba755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073896673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.3073896673
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.2934924642
Short name T1189
Test name
Test status
Simulation time 8544380959 ps
CPU time 23.94 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 238636 kb
Host smart-00fe34a7-d414-4024-a1a4-c063426878c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934924642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.2934924642
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.3584369780
Short name T439
Test name
Test status
Simulation time 594571847 ps
CPU time 7.99 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 244764 kb
Host smart-da615ef7-5a37-4cc4-a6fb-0f7cf0fa286c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584369780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3584369780
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.649514762
Short name T105
Test name
Test status
Simulation time 627864210 ps
CPU time 4.9 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:04 PM PST 23
Peak memory 238540 kb
Host smart-c088e84f-5247-433f-ba48-8dac15ae7fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649514762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.649514762
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.1461656283
Short name T814
Test name
Test status
Simulation time 9244787387 ps
CPU time 78.66 seconds
Started Dec 24 02:07:03 PM PST 23
Finished Dec 24 02:08:32 PM PST 23
Peak memory 240356 kb
Host smart-6ffdc234-07aa-4b4a-ab34-fd7e6cd960f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461656283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.1461656283
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.4147150657
Short name T1292
Test name
Test status
Simulation time 1291294264716 ps
CPU time 4890.18 seconds
Started Dec 24 02:07:06 PM PST 23
Finished Dec 24 03:28:46 PM PST 23
Peak memory 742704 kb
Host smart-ba3ef3dc-89a7-450c-9257-2fd36c216cc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147150657 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.4147150657
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.804191776
Short name T616
Test name
Test status
Simulation time 713165376 ps
CPU time 11.06 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:14 PM PST 23
Peak memory 244928 kb
Host smart-8b585d53-8e28-4eaa-90f2-81f947db9110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804191776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.804191776
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.448307429
Short name T559
Test name
Test status
Simulation time 426234120 ps
CPU time 3.77 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 246648 kb
Host smart-468a0850-442a-4780-8ed2-7a0484349b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448307429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.448307429
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.1844669218
Short name T767
Test name
Test status
Simulation time 187697088 ps
CPU time 2.68 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 238264 kb
Host smart-118ba127-0b9f-4b73-9095-d5e02936dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844669218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.1844669218
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.1617240387
Short name T1279
Test name
Test status
Simulation time 1645466247 ps
CPU time 3.96 seconds
Started Dec 24 02:08:35 PM PST 23
Finished Dec 24 02:08:54 PM PST 23
Peak memory 238444 kb
Host smart-76f2e0b3-bdf3-42a4-b07d-2a2a29dc161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617240387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1617240387
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.799261805
Short name T1157
Test name
Test status
Simulation time 626592455 ps
CPU time 5.83 seconds
Started Dec 24 02:08:35 PM PST 23
Finished Dec 24 02:08:56 PM PST 23
Peak memory 246712 kb
Host smart-eb634ff5-c731-4283-aeeb-3688e768725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799261805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.799261805
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.1449406670
Short name T531
Test name
Test status
Simulation time 196303870 ps
CPU time 3.53 seconds
Started Dec 24 02:08:47 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 240792 kb
Host smart-ca9e6660-8575-441b-8dd5-4508a251dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449406670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1449406670
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.3340916522
Short name T3
Test name
Test status
Simulation time 257674856 ps
CPU time 3.34 seconds
Started Dec 24 02:08:34 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 241212 kb
Host smart-a9a7f6d7-129c-4c4d-bd5d-051b8fd63d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340916522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3340916522
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.1576108018
Short name T921
Test name
Test status
Simulation time 311698217 ps
CPU time 4.25 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 241256 kb
Host smart-03d1c11d-6308-42ea-b476-ae4fcf02ed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576108018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1576108018
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.2156523215
Short name T1246
Test name
Test status
Simulation time 306729120 ps
CPU time 3.56 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 238408 kb
Host smart-e48f39d7-10af-4ccc-8282-d921d3b58698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156523215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2156523215
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.3137020059
Short name T865
Test name
Test status
Simulation time 317350843 ps
CPU time 3.85 seconds
Started Dec 24 02:08:36 PM PST 23
Finished Dec 24 02:08:54 PM PST 23
Peak memory 240936 kb
Host smart-c752068c-8f6d-47a1-8e6c-af442d8aaab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137020059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.3137020059
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.3416597325
Short name T38
Test name
Test status
Simulation time 448139592 ps
CPU time 4.7 seconds
Started Dec 24 02:08:48 PM PST 23
Finished Dec 24 02:09:06 PM PST 23
Peak memory 238420 kb
Host smart-f24080cb-b85f-4f6f-b966-366b7f42d05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416597325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.3416597325
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.1142037288
Short name T402
Test name
Test status
Simulation time 129495588 ps
CPU time 3.78 seconds
Started Dec 24 02:08:34 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 238312 kb
Host smart-011e6169-21f0-45e3-a135-cd962e7ad7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142037288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1142037288
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.815798201
Short name T1184
Test name
Test status
Simulation time 616192964 ps
CPU time 6.63 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 241296 kb
Host smart-cb009429-6738-4c18-9403-3b4ca76bad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815798201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.815798201
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.2891671717
Short name T143
Test name
Test status
Simulation time 154928374 ps
CPU time 3.72 seconds
Started Dec 24 02:08:48 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 238328 kb
Host smart-515b8f9e-2fcc-4b86-86f7-8ccfb100714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891671717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.2891671717
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.408648916
Short name T444
Test name
Test status
Simulation time 1258497686 ps
CPU time 9.41 seconds
Started Dec 24 02:08:35 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 244396 kb
Host smart-379495d7-89b1-422a-974a-2afd9d8c3581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408648916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.408648916
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.3544761041
Short name T1002
Test name
Test status
Simulation time 126723423 ps
CPU time 3.61 seconds
Started Dec 24 02:08:47 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 238292 kb
Host smart-3a1634d1-efbd-4d9f-a487-63edacfc6c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544761041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3544761041
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.2379878436
Short name T403
Test name
Test status
Simulation time 205820353 ps
CPU time 4.21 seconds
Started Dec 24 02:08:47 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 238256 kb
Host smart-be106e36-986c-4976-955f-276dc1d690ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379878436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.2379878436
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.277793063
Short name T1239
Test name
Test status
Simulation time 351859786 ps
CPU time 4.5 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 240940 kb
Host smart-7c3ef870-9335-436f-94d5-ed8a8bdfa243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277793063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.277793063
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1859063617
Short name T519
Test name
Test status
Simulation time 209419581 ps
CPU time 5.08 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 238440 kb
Host smart-de6a3284-7232-4f7b-83f6-accc84148087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859063617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1859063617
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.840829060
Short name T1162
Test name
Test status
Simulation time 155690690 ps
CPU time 1.8 seconds
Started Dec 24 02:07:05 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 239348 kb
Host smart-da75d32c-80cd-4a8b-81bb-dbe7bb5ba651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840829060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.840829060
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.1507840589
Short name T74
Test name
Test status
Simulation time 1933336997 ps
CPU time 4.04 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:27 PM PST 23
Peak memory 238412 kb
Host smart-005d4e97-e188-454c-87ac-69c55434b8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507840589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1507840589
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.4041569352
Short name T512
Test name
Test status
Simulation time 358121941 ps
CPU time 9.59 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 244788 kb
Host smart-1f157a3c-4ddb-4012-8b10-1b7abab7d503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041569352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.4041569352
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.2104860550
Short name T1197
Test name
Test status
Simulation time 188740165 ps
CPU time 3.05 seconds
Started Dec 24 02:07:10 PM PST 23
Finished Dec 24 02:07:24 PM PST 23
Peak memory 238496 kb
Host smart-1f7cbe82-9a64-41ee-9b8b-ebd117cf310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104860550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2104860550
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.192383038
Short name T847
Test name
Test status
Simulation time 2715755770 ps
CPU time 5.13 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:10 PM PST 23
Peak memory 238616 kb
Host smart-c93626d4-0f7f-4424-b9a9-7536e5b22ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192383038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.192383038
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.321709655
Short name T846
Test name
Test status
Simulation time 3360972709 ps
CPU time 18.17 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:28 PM PST 23
Peak memory 238608 kb
Host smart-28858965-9791-4398-9a26-a714bf9aea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321709655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.321709655
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.4083577973
Short name T800
Test name
Test status
Simulation time 905453584 ps
CPU time 15.56 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:25 PM PST 23
Peak memory 245412 kb
Host smart-c7ec6ebd-b3eb-41d1-ab99-b7907fc749ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083577973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.4083577973
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.2050074721
Short name T709
Test name
Test status
Simulation time 3541914222 ps
CPU time 7.99 seconds
Started Dec 24 02:07:11 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 244072 kb
Host smart-122c5339-7365-40ac-b32b-d46a0879e554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050074721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.2050074721
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.942627058
Short name T212
Test name
Test status
Simulation time 608682505 ps
CPU time 6.37 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:09 PM PST 23
Peak memory 242736 kb
Host smart-3be46f67-81f3-4b10-83a2-af6eb69eda90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=942627058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.942627058
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.839741251
Short name T1055
Test name
Test status
Simulation time 127747409 ps
CPU time 4.06 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 243020 kb
Host smart-5d120451-8b03-4589-aada-ee4997108d00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839741251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.839741251
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2975479813
Short name T221
Test name
Test status
Simulation time 167943993 ps
CPU time 3.8 seconds
Started Dec 24 02:07:09 PM PST 23
Finished Dec 24 02:07:22 PM PST 23
Peak memory 238416 kb
Host smart-f59c8d83-cd2d-44c3-b9d8-165d539c6de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975479813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2975479813
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.3303179530
Short name T1110
Test name
Test status
Simulation time 4552632441 ps
CPU time 58.59 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:08:09 PM PST 23
Peak memory 246892 kb
Host smart-7b32a6fa-5f5b-4870-8bc7-6131678fd488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303179530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.3303179530
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.2833925612
Short name T577
Test name
Test status
Simulation time 1130213426696 ps
CPU time 5839.4 seconds
Started Dec 24 02:07:08 PM PST 23
Finished Dec 24 03:44:38 PM PST 23
Peak memory 836740 kb
Host smart-e42b3f9c-36fb-490b-903f-cb7d556a952a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833925612 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.2833925612
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.2435935802
Short name T16
Test name
Test status
Simulation time 315404596 ps
CPU time 6.44 seconds
Started Dec 24 02:07:09 PM PST 23
Finished Dec 24 02:07:25 PM PST 23
Peak memory 238556 kb
Host smart-50e2011d-5ec5-4d05-918b-c5d341eb9f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435935802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2435935802
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.3804187002
Short name T725
Test name
Test status
Simulation time 340845807 ps
CPU time 2.64 seconds
Started Dec 24 02:08:35 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 240596 kb
Host smart-7ed83a96-6d48-4094-9ece-f317d43f45f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804187002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.3804187002
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.2003803642
Short name T1
Test name
Test status
Simulation time 145928254 ps
CPU time 2.76 seconds
Started Dec 24 02:08:48 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 241148 kb
Host smart-fe8221a6-1ffe-46b1-8d98-96a698971f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003803642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2003803642
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.3404739611
Short name T801
Test name
Test status
Simulation time 242801442 ps
CPU time 3.59 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 246640 kb
Host smart-b2523e1a-fbd8-4b9e-806a-489a7f711405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404739611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3404739611
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.3706521392
Short name T925
Test name
Test status
Simulation time 3273175360 ps
CPU time 6.84 seconds
Started Dec 24 02:08:42 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 238644 kb
Host smart-63a2a71f-c0b7-4a71-aa96-2e388c6f35af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706521392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.3706521392
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.2566198145
Short name T768
Test name
Test status
Simulation time 628944648 ps
CPU time 5.26 seconds
Started Dec 24 02:08:35 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 243000 kb
Host smart-61d1a48e-cf1a-4b7d-9180-6896b155fd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566198145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2566198145
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.2647465621
Short name T1059
Test name
Test status
Simulation time 467002223 ps
CPU time 4.52 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 240624 kb
Host smart-33968a13-4ece-4687-8a08-3ef3f076e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647465621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2647465621
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.2273803881
Short name T1086
Test name
Test status
Simulation time 355625455 ps
CPU time 4.85 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 238388 kb
Host smart-53033137-e061-4829-9331-773a452c9ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273803881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2273803881
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.4201820769
Short name T481
Test name
Test status
Simulation time 304909915 ps
CPU time 5.2 seconds
Started Dec 24 02:08:47 PM PST 23
Finished Dec 24 02:09:05 PM PST 23
Peak memory 238432 kb
Host smart-c7745526-1149-41a3-9fd2-a284f1477abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201820769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.4201820769
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.2984369568
Short name T1133
Test name
Test status
Simulation time 475318719 ps
CPU time 6.19 seconds
Started Dec 24 02:08:34 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 243008 kb
Host smart-776165ed-8f67-4090-8475-8be4a5bb2b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984369568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2984369568
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2376166207
Short name T502
Test name
Test status
Simulation time 141546921 ps
CPU time 4.57 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 240572 kb
Host smart-284a22d7-949d-4afe-91c2-eea20d514a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376166207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2376166207
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.1217185646
Short name T1118
Test name
Test status
Simulation time 2268012122 ps
CPU time 6.21 seconds
Started Dec 24 02:08:42 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 238552 kb
Host smart-19400dfc-f8bc-4558-899d-b4d1807a753b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217185646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.1217185646
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.2836908448
Short name T468
Test name
Test status
Simulation time 163000236 ps
CPU time 4.93 seconds
Started Dec 24 02:08:38 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 238388 kb
Host smart-b9386f48-9a27-49da-b325-65e62212e68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836908448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.2836908448
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.3834677810
Short name T490
Test name
Test status
Simulation time 512203684 ps
CPU time 4.24 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:08:56 PM PST 23
Peak memory 238424 kb
Host smart-9e82aacc-897e-4abe-8cdb-ae2f74b88fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834677810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3834677810
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.4195169075
Short name T771
Test name
Test status
Simulation time 268980501 ps
CPU time 3.68 seconds
Started Dec 24 02:08:40 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 238484 kb
Host smart-66f89673-e7fe-42a0-8217-396a569a25e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195169075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.4195169075
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.3352484398
Short name T1013
Test name
Test status
Simulation time 119806195 ps
CPU time 3.16 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 240764 kb
Host smart-664e3315-f42d-4e36-b4e4-073a4b0f23c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352484398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.3352484398
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.719991962
Short name T551
Test name
Test status
Simulation time 322768446 ps
CPU time 4.75 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 238456 kb
Host smart-bb8bb112-3005-48cd-99e6-4c2fe3324aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719991962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.719991962
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.102559883
Short name T1105
Test name
Test status
Simulation time 122099615 ps
CPU time 3.53 seconds
Started Dec 24 02:08:38 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 240968 kb
Host smart-8d4eff21-6a14-4f22-a3e4-f99d3260018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102559883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.102559883
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.2487408859
Short name T530
Test name
Test status
Simulation time 525899772 ps
CPU time 6.85 seconds
Started Dec 24 02:08:53 PM PST 23
Finished Dec 24 02:09:12 PM PST 23
Peak memory 243120 kb
Host smart-0fa68243-6f94-4abd-a42f-1e2878715489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487408859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2487408859
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.321788758
Short name T1139
Test name
Test status
Simulation time 671450356 ps
CPU time 1.82 seconds
Started Dec 24 02:07:03 PM PST 23
Finished Dec 24 02:07:15 PM PST 23
Peak memory 239304 kb
Host smart-2fc5ae42-fbb5-407d-a427-a1d8234a3c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321788758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.321788758
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.3639430257
Short name T659
Test name
Test status
Simulation time 119475664 ps
CPU time 4.07 seconds
Started Dec 24 02:07:09 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 238468 kb
Host smart-86ce6f28-3d1d-4049-a4df-cf1b7ee15ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639430257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.3639430257
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.3041010803
Short name T301
Test name
Test status
Simulation time 450390336 ps
CPU time 13.27 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:39 PM PST 23
Peak memory 238316 kb
Host smart-ed8a0d4c-1850-4d7b-82ea-e294bd27cb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041010803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.3041010803
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.2437301619
Short name T469
Test name
Test status
Simulation time 3246092000 ps
CPU time 16.2 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:42 PM PST 23
Peak memory 245752 kb
Host smart-127ff36e-4003-4fe5-9ce4-25affc0358c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437301619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2437301619
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.3711122503
Short name T1257
Test name
Test status
Simulation time 256038576 ps
CPU time 3.47 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:10 PM PST 23
Peak memory 238420 kb
Host smart-9ee2aa38-cc2f-42d6-a7ab-8c0938d39586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711122503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3711122503
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.1020612938
Short name T120
Test name
Test status
Simulation time 594298202 ps
CPU time 14.94 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:26 PM PST 23
Peak memory 238632 kb
Host smart-6c561724-946f-43dc-a013-c28bdb82f1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020612938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1020612938
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.1276156039
Short name T598
Test name
Test status
Simulation time 9414667005 ps
CPU time 22.89 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:26 PM PST 23
Peak memory 238644 kb
Host smart-9ae104d2-f1e9-4537-a758-368364285c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276156039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.1276156039
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.2765694650
Short name T515
Test name
Test status
Simulation time 175265432 ps
CPU time 2.86 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 241108 kb
Host smart-b4d2115d-e319-43b4-a67d-2dd20ccfcb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765694650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.2765694650
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.424062854
Short name T715
Test name
Test status
Simulation time 577485504 ps
CPU time 7.2 seconds
Started Dec 24 02:07:08 PM PST 23
Finished Dec 24 02:07:26 PM PST 23
Peak memory 243324 kb
Host smart-1133dc0f-73d7-47c1-9949-3997c036d3f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424062854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.424062854
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.1257651885
Short name T461
Test name
Test status
Simulation time 217628974 ps
CPU time 5.26 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 238588 kb
Host smart-706c1a01-bc71-4da9-8f5b-cb0f48317aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257651885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1257651885
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.3434921101
Short name T867
Test name
Test status
Simulation time 833333514 ps
CPU time 6.78 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 243164 kb
Host smart-c6d98d50-14b2-46cd-ac86-78c6b87fdf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434921101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3434921101
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.3712345054
Short name T1033
Test name
Test status
Simulation time 6694702537 ps
CPU time 108.78 seconds
Started Dec 24 02:07:11 PM PST 23
Finished Dec 24 02:09:11 PM PST 23
Peak memory 241716 kb
Host smart-8f657349-fe2f-4ee2-8987-df343201a601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712345054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.3712345054
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.4251282432
Short name T258
Test name
Test status
Simulation time 3694915832238 ps
CPU time 5253.92 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 03:34:57 PM PST 23
Peak memory 820388 kb
Host smart-4869f975-e30e-4a58-aa4a-73c7d63b5f59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251282432 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.4251282432
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.1583878921
Short name T94
Test name
Test status
Simulation time 662860648 ps
CPU time 13.51 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:24 PM PST 23
Peak memory 238560 kb
Host smart-fb314ebf-c4e7-40d9-b272-b77172e0e234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583878921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1583878921
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.3356583843
Short name T1104
Test name
Test status
Simulation time 170166582 ps
CPU time 4.19 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 238440 kb
Host smart-3db02ef5-e4d9-4768-85fa-babac6d40a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356583843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3356583843
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.2482362630
Short name T562
Test name
Test status
Simulation time 269951705 ps
CPU time 3.21 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 242512 kb
Host smart-444f13fb-1bc7-4ef0-b766-dd52347f2cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482362630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2482362630
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.319820064
Short name T1233
Test name
Test status
Simulation time 266774526 ps
CPU time 3.78 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 238456 kb
Host smart-1bc8333f-af23-4c69-b848-505770ed43ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319820064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.319820064
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2182854781
Short name T874
Test name
Test status
Simulation time 217144506 ps
CPU time 5.48 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 238464 kb
Host smart-7cc0ccd3-328b-4e0d-871e-b7cf3c20e31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182854781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2182854781
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.1890692454
Short name T39
Test name
Test status
Simulation time 460247532 ps
CPU time 4.78 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 241384 kb
Host smart-418c83cd-0de2-499e-914d-15e8da26213e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890692454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1890692454
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.1433092696
Short name T667
Test name
Test status
Simulation time 494199230 ps
CPU time 5.97 seconds
Started Dec 24 02:08:53 PM PST 23
Finished Dec 24 02:09:11 PM PST 23
Peak memory 238508 kb
Host smart-ad946b67-6f16-40cc-943c-47f9badaf4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433092696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1433092696
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.3117869961
Short name T927
Test name
Test status
Simulation time 2700660544 ps
CPU time 6.78 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:05 PM PST 23
Peak memory 241548 kb
Host smart-b8dcc5ca-1130-406a-8e90-ea1e3894b6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117869961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3117869961
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.1176200016
Short name T505
Test name
Test status
Simulation time 214423937 ps
CPU time 3.42 seconds
Started Dec 24 02:08:56 PM PST 23
Finished Dec 24 02:09:10 PM PST 23
Peak memory 243376 kb
Host smart-517bdcb3-069e-47a3-874e-471fa40b10d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176200016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.1176200016
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.287823729
Short name T717
Test name
Test status
Simulation time 108123844 ps
CPU time 3.69 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 238400 kb
Host smart-610b7b56-14b6-40cc-9a5b-866872882fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287823729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.287823729
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1769715562
Short name T488
Test name
Test status
Simulation time 487209907 ps
CPU time 6.16 seconds
Started Dec 24 02:08:56 PM PST 23
Finished Dec 24 02:09:13 PM PST 23
Peak memory 238508 kb
Host smart-0c98c56c-2d89-46ef-ba3d-37faf2ae6784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769715562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1769715562
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.1736300819
Short name T1023
Test name
Test status
Simulation time 509047180 ps
CPU time 3.77 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 238512 kb
Host smart-6af72020-484f-4175-b452-af23322f917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736300819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1736300819
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.104318122
Short name T325
Test name
Test status
Simulation time 415372526 ps
CPU time 8.55 seconds
Started Dec 24 02:09:14 PM PST 23
Finished Dec 24 02:09:29 PM PST 23
Peak memory 243708 kb
Host smart-79c33b68-190c-471e-85a6-d99271013ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104318122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.104318122
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.521160395
Short name T581
Test name
Test status
Simulation time 489802236 ps
CPU time 4.62 seconds
Started Dec 24 02:09:07 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 241212 kb
Host smart-1074d0cd-7542-4051-b870-a73bbe69fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521160395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.521160395
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.471327487
Short name T968
Test name
Test status
Simulation time 187183356 ps
CPU time 2.78 seconds
Started Dec 24 02:08:58 PM PST 23
Finished Dec 24 02:09:10 PM PST 23
Peak memory 238360 kb
Host smart-b1776b29-f112-4e6f-bdff-b0a0537f0b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471327487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.471327487
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.4140284020
Short name T1273
Test name
Test status
Simulation time 605234439 ps
CPU time 4.59 seconds
Started Dec 24 02:09:03 PM PST 23
Finished Dec 24 02:09:12 PM PST 23
Peak memory 238464 kb
Host smart-4af495e1-7467-48e7-b536-d6a9c612af62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140284020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.4140284020
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.2752516248
Short name T748
Test name
Test status
Simulation time 224495323 ps
CPU time 3.44 seconds
Started Dec 24 02:08:59 PM PST 23
Finished Dec 24 02:09:10 PM PST 23
Peak memory 241400 kb
Host smart-35899138-4993-4c62-b3f9-9e12547fecde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752516248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2752516248
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.1168462180
Short name T1012
Test name
Test status
Simulation time 234054002 ps
CPU time 3.04 seconds
Started Dec 24 02:09:07 PM PST 23
Finished Dec 24 02:09:12 PM PST 23
Peak memory 238424 kb
Host smart-d83e7960-0c3b-44e0-b3d4-e03be08836dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168462180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.1168462180
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.4224908474
Short name T87
Test name
Test status
Simulation time 255272222 ps
CPU time 2.69 seconds
Started Dec 24 02:08:57 PM PST 23
Finished Dec 24 02:09:09 PM PST 23
Peak memory 241464 kb
Host smart-560797a3-638e-45d6-b3ff-43a1be717e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224908474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.4224908474
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.2507675226
Short name T875
Test name
Test status
Simulation time 139728113 ps
CPU time 3.76 seconds
Started Dec 24 02:08:59 PM PST 23
Finished Dec 24 02:09:11 PM PST 23
Peak memory 238512 kb
Host smart-62eaf355-9e30-43db-bf0e-847f599e02c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507675226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.2507675226
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.2837989831
Short name T991
Test name
Test status
Simulation time 376170449 ps
CPU time 4.84 seconds
Started Dec 24 02:09:08 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 242632 kb
Host smart-9b86dad3-0df1-4219-902c-63e5cbbab4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837989831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2837989831
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.3923399175
Short name T574
Test name
Test status
Simulation time 172902257 ps
CPU time 2.01 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 238732 kb
Host smart-a863cec0-992b-4fc5-ba5a-93a5e725fdb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923399175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3923399175
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.289971910
Short name T511
Test name
Test status
Simulation time 426237941 ps
CPU time 10.32 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:15 PM PST 23
Peak memory 238304 kb
Host smart-a6ee6b0a-938b-4a28-bb4b-836b74633903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289971910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.289971910
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.1696976599
Short name T722
Test name
Test status
Simulation time 419587674 ps
CPU time 10.81 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:19 PM PST 23
Peak memory 244428 kb
Host smart-a1b716d2-f209-4e68-ad88-81b38059b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696976599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1696976599
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.3151762939
Short name T640
Test name
Test status
Simulation time 697828488 ps
CPU time 5.11 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 238400 kb
Host smart-29b77fb5-774e-4fc5-bb42-a9a9a8696f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151762939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3151762939
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.313252326
Short name T284
Test name
Test status
Simulation time 6824785582 ps
CPU time 12.56 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 246812 kb
Host smart-9511c4d9-ae1e-4864-ad52-7f3802e47802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313252326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.313252326
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.1474288083
Short name T790
Test name
Test status
Simulation time 145942295 ps
CPU time 3.92 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:27 PM PST 23
Peak memory 230292 kb
Host smart-7a5700a2-7a09-4a8b-be25-35bc8a8cd54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474288083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1474288083
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.1143016812
Short name T621
Test name
Test status
Simulation time 123695319 ps
CPU time 3.29 seconds
Started Dec 24 02:07:03 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 241156 kb
Host smart-c5e219fc-0a46-4e8a-aa9d-47cce9b5843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143016812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.1143016812
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.580266311
Short name T752
Test name
Test status
Simulation time 298416147 ps
CPU time 8.21 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:09 PM PST 23
Peak memory 243736 kb
Host smart-f8dcdac5-c164-4c82-8de7-709ee89a9493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580266311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.580266311
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1643681169
Short name T316
Test name
Test status
Simulation time 3100965279 ps
CPU time 7.13 seconds
Started Dec 24 02:07:05 PM PST 23
Finished Dec 24 02:07:22 PM PST 23
Peak memory 238652 kb
Host smart-d6b5e936-d53c-44eb-a154-d0bffc4ce465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643681169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1643681169
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.720045210
Short name T1004
Test name
Test status
Simulation time 203677449 ps
CPU time 4.56 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 238512 kb
Host smart-afcfdca8-a6b3-46f2-a80d-609cdd770206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720045210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.720045210
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.2652403505
Short name T547
Test name
Test status
Simulation time 40663608530 ps
CPU time 125.11 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:09:12 PM PST 23
Peak memory 246852 kb
Host smart-74a94324-7fc4-4622-b8e3-5203fba44530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652403505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.2652403505
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.1926434737
Short name T1020
Test name
Test status
Simulation time 212047020444 ps
CPU time 3183.25 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 03:00:07 PM PST 23
Peak memory 257856 kb
Host smart-81947dd5-5627-479d-95a7-24a07bbd901c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926434737 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.1926434737
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.1460794460
Short name T1179
Test name
Test status
Simulation time 1114095046 ps
CPU time 15.09 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 238396 kb
Host smart-e5a39b30-c76b-4147-affe-5fbe0c2372aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460794460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1460794460
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.3061107686
Short name T593
Test name
Test status
Simulation time 121765182 ps
CPU time 4.55 seconds
Started Dec 24 02:09:08 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 238468 kb
Host smart-9fdc4fef-9b94-42c3-bc98-d4017e4fa5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061107686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3061107686
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3942396265
Short name T614
Test name
Test status
Simulation time 447721706 ps
CPU time 5.41 seconds
Started Dec 24 02:09:08 PM PST 23
Finished Dec 24 02:09:16 PM PST 23
Peak memory 238372 kb
Host smart-dee7e690-0547-4558-86b0-de058755f5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942396265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3942396265
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.2672299162
Short name T848
Test name
Test status
Simulation time 119944874 ps
CPU time 3.71 seconds
Started Dec 24 02:08:54 PM PST 23
Finished Dec 24 02:09:10 PM PST 23
Peak memory 246500 kb
Host smart-bcbcfb76-f8e8-4b52-b8e8-2f77d5f4fd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672299162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2672299162
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2969811165
Short name T294
Test name
Test status
Simulation time 543314042 ps
CPU time 5.51 seconds
Started Dec 24 02:08:58 PM PST 23
Finished Dec 24 02:09:12 PM PST 23
Peak memory 242464 kb
Host smart-8cbf2342-9e9b-4b4f-ac7f-9ff8bbcf14ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969811165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2969811165
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.1288360231
Short name T632
Test name
Test status
Simulation time 2846315813 ps
CPU time 7.82 seconds
Started Dec 24 02:08:59 PM PST 23
Finished Dec 24 02:09:15 PM PST 23
Peak memory 243456 kb
Host smart-7e5a1481-1cef-4a09-9d55-1d8e65f15aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288360231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1288360231
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.1683699955
Short name T780
Test name
Test status
Simulation time 164687050 ps
CPU time 4.33 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:20 PM PST 23
Peak memory 238376 kb
Host smart-6221f77e-2248-4460-8e10-d3ca3773b426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683699955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.1683699955
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1782670394
Short name T644
Test name
Test status
Simulation time 1020557117 ps
CPU time 6.61 seconds
Started Dec 24 02:09:03 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 243096 kb
Host smart-eca8b86c-79fc-4da7-99ec-a40f0477f8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782670394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1782670394
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.2701831369
Short name T785
Test name
Test status
Simulation time 2022002212 ps
CPU time 4.67 seconds
Started Dec 24 02:09:13 PM PST 23
Finished Dec 24 02:09:24 PM PST 23
Peak memory 246676 kb
Host smart-17d92524-10fa-4217-a1cf-e4c37a44b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701831369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.2701831369
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.2042596948
Short name T673
Test name
Test status
Simulation time 296836899 ps
CPU time 6.39 seconds
Started Dec 24 02:08:56 PM PST 23
Finished Dec 24 02:09:13 PM PST 23
Peak memory 243700 kb
Host smart-a65b63f0-7e38-4e33-92c3-f41590e47e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042596948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2042596948
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.1219449152
Short name T518
Test name
Test status
Simulation time 2218735309 ps
CPU time 4.15 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:20 PM PST 23
Peak memory 238448 kb
Host smart-67b7a634-b4c6-4d76-82fb-c9535d0bfd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219449152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1219449152
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.2325308057
Short name T942
Test name
Test status
Simulation time 450937269 ps
CPU time 6.96 seconds
Started Dec 24 02:08:57 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 243908 kb
Host smart-d7f08252-a9d4-4c37-89d0-a62fe7b77aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325308057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2325308057
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.2239905990
Short name T649
Test name
Test status
Simulation time 391955944 ps
CPU time 5.06 seconds
Started Dec 24 02:08:58 PM PST 23
Finished Dec 24 02:09:12 PM PST 23
Peak memory 238468 kb
Host smart-4ea579c6-f0de-44ed-b748-cad4e802e7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239905990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2239905990
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.3586181019
Short name T1167
Test name
Test status
Simulation time 313377021 ps
CPU time 3.25 seconds
Started Dec 24 02:08:53 PM PST 23
Finished Dec 24 02:09:09 PM PST 23
Peak memory 238460 kb
Host smart-d76058f3-d73f-4110-9dd9-8300ec9afde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586181019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3586181019
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.1973585260
Short name T606
Test name
Test status
Simulation time 313433082 ps
CPU time 4.26 seconds
Started Dec 24 02:09:15 PM PST 23
Finished Dec 24 02:09:31 PM PST 23
Peak memory 238444 kb
Host smart-2bfb3bf2-d992-425a-9dcf-b1fd8cab382d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973585260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1973585260
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.786010860
Short name T295
Test name
Test status
Simulation time 168458586 ps
CPU time 3.08 seconds
Started Dec 24 02:08:54 PM PST 23
Finished Dec 24 02:09:09 PM PST 23
Peak memory 238440 kb
Host smart-91a272a7-7b6c-4979-8bcf-0cdf052ff456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786010860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.786010860
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.1288824021
Short name T676
Test name
Test status
Simulation time 154000061 ps
CPU time 4.04 seconds
Started Dec 24 02:09:07 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 238364 kb
Host smart-325f9759-57a1-4163-81d0-fd52f5ce1d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288824021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1288824021
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.3276404451
Short name T1281
Test name
Test status
Simulation time 793997948 ps
CPU time 5.35 seconds
Started Dec 24 02:09:07 PM PST 23
Finished Dec 24 02:09:15 PM PST 23
Peak memory 238452 kb
Host smart-ede37813-6283-4052-888c-f196036fa3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276404451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3276404451
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.835149639
Short name T594
Test name
Test status
Simulation time 500666454 ps
CPU time 4.79 seconds
Started Dec 24 02:09:07 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 240712 kb
Host smart-48d588bb-ca8d-4000-a311-7cc17e3dc62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835149639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.835149639
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.1973328379
Short name T299
Test name
Test status
Simulation time 117510753 ps
CPU time 3.86 seconds
Started Dec 24 02:09:07 PM PST 23
Finished Dec 24 02:09:13 PM PST 23
Peak memory 238376 kb
Host smart-88f05795-2c15-49da-a23f-3c81f176a5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973328379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.1973328379
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.2978780602
Short name T946
Test name
Test status
Simulation time 53102273 ps
CPU time 1.63 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:10 PM PST 23
Peak memory 238228 kb
Host smart-ad45578a-276f-4e02-a2fe-f06ab93ba28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978780602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2978780602
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.2477081532
Short name T1001
Test name
Test status
Simulation time 1878075297 ps
CPU time 12.5 seconds
Started Dec 24 02:07:08 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 238620 kb
Host smart-6d2015c3-d4fd-4f26-9f6e-291a26f5da1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477081532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2477081532
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.707845614
Short name T434
Test name
Test status
Simulation time 191038064 ps
CPU time 7.5 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 243228 kb
Host smart-bd3e74d4-2303-4599-97a8-0caeeb97f2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707845614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.707845614
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.4015878802
Short name T1047
Test name
Test status
Simulation time 652407736 ps
CPU time 9.59 seconds
Started Dec 24 02:07:11 PM PST 23
Finished Dec 24 02:07:31 PM PST 23
Peak memory 238536 kb
Host smart-ae5d5c56-1f1c-4270-ade0-2780e9d1eec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015878802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.4015878802
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.2970299649
Short name T789
Test name
Test status
Simulation time 269577154 ps
CPU time 4.64 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 241180 kb
Host smart-81609329-d4c7-469c-8b65-d49c9e1674ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970299649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.2970299649
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.966832219
Short name T424
Test name
Test status
Simulation time 2000038684 ps
CPU time 14.49 seconds
Started Dec 24 02:07:06 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 246744 kb
Host smart-b439493f-80f5-41a0-be9d-8b745eb3572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966832219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.966832219
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.4125726406
Short name T630
Test name
Test status
Simulation time 1349860697 ps
CPU time 17.34 seconds
Started Dec 24 02:07:09 PM PST 23
Finished Dec 24 02:07:36 PM PST 23
Peak memory 246600 kb
Host smart-0374eb50-4f36-42b3-b542-9bac2c10d3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125726406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.4125726406
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.1202116579
Short name T798
Test name
Test status
Simulation time 362225260 ps
CPU time 5.31 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:14 PM PST 23
Peak memory 242000 kb
Host smart-b50c6992-d810-4b8d-b04b-5fa14ac813f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202116579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1202116579
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.1551644495
Short name T433
Test name
Test status
Simulation time 688106118 ps
CPU time 9.06 seconds
Started Dec 24 02:07:10 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 243416 kb
Host smart-ec64658a-dd41-404e-aa1f-73d9fa524603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551644495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.1551644495
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.3891809030
Short name T544
Test name
Test status
Simulation time 115570122 ps
CPU time 3.86 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 243152 kb
Host smart-a5983b22-b78b-4d86-8623-be6b71309e71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891809030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3891809030
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.3069182912
Short name T918
Test name
Test status
Simulation time 443445385 ps
CPU time 7.38 seconds
Started Dec 24 02:07:09 PM PST 23
Finished Dec 24 02:07:27 PM PST 23
Peak memory 242860 kb
Host smart-3a84e33d-af07-482e-9164-6ac2713c687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069182912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3069182912
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.2281390350
Short name T686
Test name
Test status
Simulation time 2085349547 ps
CPU time 60.17 seconds
Started Dec 24 02:07:08 PM PST 23
Finished Dec 24 02:08:18 PM PST 23
Peak memory 239596 kb
Host smart-9b304b4c-5a89-41b7-8b68-bdef5d33d20d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281390350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.2281390350
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1290975634
Short name T1025
Test name
Test status
Simulation time 424848147067 ps
CPU time 4795.57 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 03:27:06 PM PST 23
Peak memory 277980 kb
Host smart-b2f04575-2845-406b-b08c-cef94d36a30d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290975634 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.1290975634
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.3492029735
Short name T926
Test name
Test status
Simulation time 777336904 ps
CPU time 14.79 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:41 PM PST 23
Peak memory 246764 kb
Host smart-999059b3-159d-4f68-8f15-33e4ae020321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492029735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3492029735
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.2773792454
Short name T1040
Test name
Test status
Simulation time 499576595 ps
CPU time 5.26 seconds
Started Dec 24 02:08:55 PM PST 23
Finished Dec 24 02:09:11 PM PST 23
Peak memory 240620 kb
Host smart-1012666f-295f-4e99-97aa-cd20d38437eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773792454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2773792454
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.2469112863
Short name T1049
Test name
Test status
Simulation time 372708755 ps
CPU time 3.29 seconds
Started Dec 24 02:09:14 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 240904 kb
Host smart-1487d3b3-f26a-4986-a3bc-cd3c07765d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469112863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.2469112863
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.847309543
Short name T449
Test name
Test status
Simulation time 545582483 ps
CPU time 3.71 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 240840 kb
Host smart-557216c0-d6ad-4636-b86c-3bed48af8165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847309543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.847309543
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2634671898
Short name T730
Test name
Test status
Simulation time 2511257821 ps
CPU time 4.94 seconds
Started Dec 24 02:09:09 PM PST 23
Finished Dec 24 02:09:17 PM PST 23
Peak memory 246828 kb
Host smart-ba1b777d-efdf-4d37-8bb6-262a1b889831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634671898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2634671898
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.583263017
Short name T1045
Test name
Test status
Simulation time 346141566 ps
CPU time 3.9 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:18 PM PST 23
Peak memory 238412 kb
Host smart-64a6e3fe-3291-4684-9bda-98df632798ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583263017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.583263017
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.2965776378
Short name T457
Test name
Test status
Simulation time 365847566 ps
CPU time 4.98 seconds
Started Dec 24 02:09:13 PM PST 23
Finished Dec 24 02:09:24 PM PST 23
Peak memory 242384 kb
Host smart-93fb347b-4ee7-4836-983d-c98019e3bede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965776378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2965776378
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.573982201
Short name T840
Test name
Test status
Simulation time 206222327 ps
CPU time 4.25 seconds
Started Dec 24 02:09:11 PM PST 23
Finished Dec 24 02:09:21 PM PST 23
Peak memory 241140 kb
Host smart-7ff3c2c0-5cd8-4574-b4bb-c832de1c2826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573982201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.573982201
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.688751634
Short name T889
Test name
Test status
Simulation time 6583399410 ps
CPU time 11.1 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:25 PM PST 23
Peak memory 238632 kb
Host smart-abcca232-a2ce-4c9b-b761-81e01f9cadb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688751634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.688751634
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.2773975104
Short name T855
Test name
Test status
Simulation time 219053004 ps
CPU time 3.3 seconds
Started Dec 24 02:09:22 PM PST 23
Finished Dec 24 02:09:36 PM PST 23
Peak memory 238376 kb
Host smart-cf00dd5b-aea2-42fb-a529-d7eca94e2d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773975104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.2773975104
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.2950649279
Short name T808
Test name
Test status
Simulation time 408901013 ps
CPU time 3.89 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:18 PM PST 23
Peak memory 246692 kb
Host smart-3be7143c-e758-4107-92fa-08d9d7addbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950649279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2950649279
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.3495037747
Short name T213
Test name
Test status
Simulation time 373842141 ps
CPU time 3.77 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:22 PM PST 23
Peak memory 241148 kb
Host smart-b1131caa-0de9-4027-af08-05b037ccae96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495037747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3495037747
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.15160566
Short name T8
Test name
Test status
Simulation time 238712390 ps
CPU time 4.8 seconds
Started Dec 24 02:09:17 PM PST 23
Finished Dec 24 02:09:34 PM PST 23
Peak memory 246516 kb
Host smart-a798e1e7-c3e7-481e-b881-6c904b2589ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15160566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.15160566
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.469911207
Short name T134
Test name
Test status
Simulation time 303854803 ps
CPU time 3.59 seconds
Started Dec 24 02:09:09 PM PST 23
Finished Dec 24 02:09:16 PM PST 23
Peak memory 241320 kb
Host smart-2521787d-4b03-4b74-89c9-65663a092c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469911207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.469911207
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.3232397459
Short name T1158
Test name
Test status
Simulation time 153460399 ps
CPU time 4.36 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:19 PM PST 23
Peak memory 242404 kb
Host smart-5e9f8376-16d2-4c71-9a06-6645722d35b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232397459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3232397459
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.1761764062
Short name T890
Test name
Test status
Simulation time 531631627 ps
CPU time 4.47 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:20 PM PST 23
Peak memory 238436 kb
Host smart-3312eb49-83b1-43ad-820f-2b48d60f7eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761764062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1761764062
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.4204311577
Short name T975
Test name
Test status
Simulation time 85605510 ps
CPU time 2.54 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:18 PM PST 23
Peak memory 240708 kb
Host smart-d5a78848-2b63-49cb-8f90-8b4ec484027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204311577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.4204311577
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.490863991
Short name T517
Test name
Test status
Simulation time 112307443 ps
CPU time 3.56 seconds
Started Dec 24 02:09:13 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 241020 kb
Host smart-fb71b0a3-aba2-4d82-af00-124ba0d00093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490863991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.490863991
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.1675619529
Short name T642
Test name
Test status
Simulation time 221102988 ps
CPU time 2.83 seconds
Started Dec 24 02:09:16 PM PST 23
Finished Dec 24 02:09:31 PM PST 23
Peak memory 240988 kb
Host smart-91679af8-09a8-4236-84aa-168a71cc968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675619529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.1675619529
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.2769413774
Short name T32
Test name
Test status
Simulation time 180069306 ps
CPU time 4.39 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:20 PM PST 23
Peak memory 238440 kb
Host smart-f72602e6-71b7-47d9-9914-816628ea6db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769413774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2769413774
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.164924812
Short name T727
Test name
Test status
Simulation time 168976735 ps
CPU time 3.43 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:22 PM PST 23
Peak memory 246608 kb
Host smart-3778744a-ca41-489f-bb8e-6bacb64a4329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164924812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.164924812
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.2091488054
Short name T573
Test name
Test status
Simulation time 65657418 ps
CPU time 1.5 seconds
Started Dec 24 02:06:20 PM PST 23
Finished Dec 24 02:06:27 PM PST 23
Peak memory 238116 kb
Host smart-a896a74e-0779-4672-ae92-58ae951d67b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091488054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2091488054
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.3539475908
Short name T1101
Test name
Test status
Simulation time 661080683 ps
CPU time 7.38 seconds
Started Dec 24 02:06:20 PM PST 23
Finished Dec 24 02:06:33 PM PST 23
Peak memory 238388 kb
Host smart-60da4eb5-1122-4b65-a28a-3f9d77f5f361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539475908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3539475908
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.3604888533
Short name T283
Test name
Test status
Simulation time 209512708 ps
CPU time 3.89 seconds
Started Dec 24 02:06:17 PM PST 23
Finished Dec 24 02:06:28 PM PST 23
Peak memory 238572 kb
Host smart-6fc568e4-5262-43a9-b8e5-f3e30a0014cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604888533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3604888533
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1478323060
Short name T784
Test name
Test status
Simulation time 392595297 ps
CPU time 9.05 seconds
Started Dec 24 02:06:18 PM PST 23
Finished Dec 24 02:06:34 PM PST 23
Peak memory 244920 kb
Host smart-2fda426c-a2fe-465d-adaf-b77cb5ced94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478323060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1478323060
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.3200161071
Short name T690
Test name
Test status
Simulation time 667742894 ps
CPU time 13.3 seconds
Started Dec 24 02:06:20 PM PST 23
Finished Dec 24 02:06:39 PM PST 23
Peak memory 245348 kb
Host smart-b5564c3d-8f93-4695-8d33-3efeb93a9187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200161071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3200161071
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.883094974
Short name T842
Test name
Test status
Simulation time 323399911 ps
CPU time 4.77 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 02:06:23 PM PST 23
Peak memory 240600 kb
Host smart-0a49347e-21a9-4240-90cc-1aaaba628acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883094974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.883094974
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.3684967680
Short name T1123
Test name
Test status
Simulation time 313006447 ps
CPU time 6.01 seconds
Started Dec 24 02:06:10 PM PST 23
Finished Dec 24 02:06:23 PM PST 23
Peak memory 246708 kb
Host smart-9d006529-9461-4b7a-b948-b19dc4c0be99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684967680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3684967680
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.3094263961
Short name T552
Test name
Test status
Simulation time 1311582749 ps
CPU time 9.69 seconds
Started Dec 24 02:06:21 PM PST 23
Finished Dec 24 02:06:36 PM PST 23
Peak memory 241744 kb
Host smart-3143b716-06d3-4561-be59-d2db7dc5dff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094263961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3094263961
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2796973758
Short name T1093
Test name
Test status
Simulation time 206852653 ps
CPU time 3.85 seconds
Started Dec 24 02:06:18 PM PST 23
Finished Dec 24 02:06:28 PM PST 23
Peak memory 238524 kb
Host smart-45349062-cab4-48be-a0b3-a4d2efaf4470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796973758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2796973758
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.2789288108
Short name T1090
Test name
Test status
Simulation time 607117414 ps
CPU time 4.17 seconds
Started Dec 24 02:06:18 PM PST 23
Finished Dec 24 02:06:29 PM PST 23
Peak memory 238508 kb
Host smart-fdfb18d9-4493-4da0-b9ec-a57458094490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789288108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2789288108
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.2020419296
Short name T320
Test name
Test status
Simulation time 321476624 ps
CPU time 6.89 seconds
Started Dec 24 02:06:19 PM PST 23
Finished Dec 24 02:06:32 PM PST 23
Peak memory 238432 kb
Host smart-75a5880f-4b0e-4947-9210-766c1e20080a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020419296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2020419296
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.3839401261
Short name T24
Test name
Test status
Simulation time 131472404029 ps
CPU time 318.07 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 02:11:37 PM PST 23
Peak memory 267272 kb
Host smart-a3bad74f-4eda-46e4-b613-467f52c3e079
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839401261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3839401261
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.3415424505
Short name T883
Test name
Test status
Simulation time 310927991 ps
CPU time 5.04 seconds
Started Dec 24 02:06:20 PM PST 23
Finished Dec 24 02:06:30 PM PST 23
Peak memory 238392 kb
Host smart-c05b2730-cd75-4be9-addb-d0f4afaaa771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415424505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3415424505
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.4151921259
Short name T1151
Test name
Test status
Simulation time 2016730832741 ps
CPU time 7678.82 seconds
Started Dec 24 02:06:12 PM PST 23
Finished Dec 24 04:14:18 PM PST 23
Peak memory 309380 kb
Host smart-138735c9-72d9-425d-8afb-a9a346fb1ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151921259 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.4151921259
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.1676927207
Short name T843
Test name
Test status
Simulation time 1506430203 ps
CPU time 13.91 seconds
Started Dec 24 02:06:11 PM PST 23
Finished Dec 24 02:06:31 PM PST 23
Peak memory 237672 kb
Host smart-00fbef19-8a8e-4f68-b924-c23b479beb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676927207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.1676927207
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.3332423916
Short name T473
Test name
Test status
Simulation time 701956903 ps
CPU time 1.79 seconds
Started Dec 24 02:07:10 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 238176 kb
Host smart-8caa70b8-b6f0-4670-b4e1-c794c5ac7573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332423916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3332423916
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.374594579
Short name T73
Test name
Test status
Simulation time 271313316 ps
CPU time 3.77 seconds
Started Dec 24 02:07:09 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 241020 kb
Host smart-4870909d-da57-40af-a4f4-56a1f3f6413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374594579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.374594579
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.2248505053
Short name T749
Test name
Test status
Simulation time 5482062606 ps
CPU time 11.16 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 246348 kb
Host smart-7b6620a1-e83f-44ae-85bb-2330ad86d362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248505053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2248505053
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.975274790
Short name T1237
Test name
Test status
Simulation time 1406907612 ps
CPU time 15.58 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 238584 kb
Host smart-5a83819a-3789-432c-a448-085aeccc3edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975274790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.975274790
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.1342874046
Short name T796
Test name
Test status
Simulation time 117986189 ps
CPU time 4.06 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 240976 kb
Host smart-cf883d13-1bea-4c0d-bd2c-3b3ba710607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342874046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1342874046
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.837204191
Short name T720
Test name
Test status
Simulation time 234792851 ps
CPU time 6.99 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 238648 kb
Host smart-e0f01843-fa72-45fa-a2e8-b5858960e683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837204191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.837204191
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.2871528557
Short name T901
Test name
Test status
Simulation time 1171124002 ps
CPU time 5.98 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 238500 kb
Host smart-08a21ab8-84e9-4ce5-94c7-7bb639a6ca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871528557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2871528557
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.2011400979
Short name T660
Test name
Test status
Simulation time 97998513 ps
CPU time 3.49 seconds
Started Dec 24 02:07:06 PM PST 23
Finished Dec 24 02:07:19 PM PST 23
Peak memory 238472 kb
Host smart-e2336ab9-b81c-486e-93c4-c3feeab9f583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011400979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2011400979
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.2313140181
Short name T596
Test name
Test status
Simulation time 1502441960 ps
CPU time 10.64 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 238500 kb
Host smart-0f1d076f-5363-463a-90fc-3eeaedeaa03a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313140181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2313140181
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.2338983605
Short name T315
Test name
Test status
Simulation time 220193783 ps
CPU time 5.31 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 243628 kb
Host smart-69ad86c8-5e5c-4d40-978d-234ff83fc9da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338983605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.2338983605
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.3742449350
Short name T472
Test name
Test status
Simulation time 2585705938 ps
CPU time 7.11 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 245020 kb
Host smart-5ca8465e-ab44-4c41-9f15-8e7291a5c7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742449350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3742449350
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.1656207760
Short name T895
Test name
Test status
Simulation time 33674219441 ps
CPU time 94.73 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 246208 kb
Host smart-88bdbcea-0027-4675-af0e-22cbba0c514f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656207760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.1656207760
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.3647818070
Short name T956
Test name
Test status
Simulation time 1232401353658 ps
CPU time 6031.29 seconds
Started Dec 24 02:07:06 PM PST 23
Finished Dec 24 03:47:47 PM PST 23
Peak memory 291064 kb
Host smart-fcccee6a-8957-4665-82f6-cec10bbf5869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647818070 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.3647818070
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.1928719630
Short name T920
Test name
Test status
Simulation time 10499387655 ps
CPU time 12.69 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:22 PM PST 23
Peak memory 244364 kb
Host smart-6dfb1794-c754-4a09-bc76-18784965b96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928719630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1928719630
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3264923337
Short name T989
Test name
Test status
Simulation time 486922932 ps
CPU time 4.38 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:19 PM PST 23
Peak memory 240484 kb
Host smart-a71124ca-e2ef-4bcf-94cd-d19ae971e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264923337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3264923337
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.2527950274
Short name T141
Test name
Test status
Simulation time 95070615 ps
CPU time 3.07 seconds
Started Dec 24 02:09:25 PM PST 23
Finished Dec 24 02:09:36 PM PST 23
Peak memory 238444 kb
Host smart-c4aaa2f6-0c90-4ada-9795-cc30a5c3a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527950274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2527950274
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.3002255389
Short name T903
Test name
Test status
Simulation time 444253727 ps
CPU time 3.82 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:22 PM PST 23
Peak memory 238356 kb
Host smart-c9d6795b-b694-41be-b553-32c90cd9c26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002255389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3002255389
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.3798650041
Short name T496
Test name
Test status
Simulation time 246115857 ps
CPU time 3.42 seconds
Started Dec 24 02:09:13 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 240476 kb
Host smart-6bf5441f-9284-41fc-9a8e-cec8db24b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798650041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.3798650041
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.1712094387
Short name T938
Test name
Test status
Simulation time 2587959810 ps
CPU time 4.76 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:24 PM PST 23
Peak memory 238556 kb
Host smart-d31bb7a0-58d5-4059-a801-7bfebeabed4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712094387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1712094387
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.3928700494
Short name T1094
Test name
Test status
Simulation time 413579489 ps
CPU time 4.04 seconds
Started Dec 24 02:09:11 PM PST 23
Finished Dec 24 02:09:22 PM PST 23
Peak memory 238440 kb
Host smart-40154c97-9aa3-4836-b86d-2256b54136ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928700494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.3928700494
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.2234091767
Short name T28
Test name
Test status
Simulation time 293972451 ps
CPU time 3.69 seconds
Started Dec 24 02:09:27 PM PST 23
Finished Dec 24 02:09:38 PM PST 23
Peak memory 238372 kb
Host smart-877f7769-bd7e-4b0e-a1ed-e391e66ad805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234091767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2234091767
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.2441775561
Short name T459
Test name
Test status
Simulation time 245444688 ps
CPU time 4.33 seconds
Started Dec 24 02:09:09 PM PST 23
Finished Dec 24 02:09:16 PM PST 23
Peak memory 240632 kb
Host smart-9f0a4ef2-cc4f-4606-90b9-8b673ebd2ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441775561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2441775561
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.1900883964
Short name T1134
Test name
Test status
Simulation time 128588643 ps
CPU time 4.76 seconds
Started Dec 24 02:09:06 PM PST 23
Finished Dec 24 02:09:13 PM PST 23
Peak memory 241224 kb
Host smart-180d9879-5e95-4a0f-b328-1f17d39dbae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900883964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1900883964
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.3697468109
Short name T833
Test name
Test status
Simulation time 130932458 ps
CPU time 1.96 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 238724 kb
Host smart-997773a9-748a-42bc-aaf4-31c7fb5fa1bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697468109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3697468109
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.3772980036
Short name T291
Test name
Test status
Simulation time 616947051 ps
CPU time 4.37 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 246604 kb
Host smart-a4697850-b03a-4499-85c5-7ed132fc3d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772980036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3772980036
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3080261012
Short name T207
Test name
Test status
Simulation time 2569237025 ps
CPU time 9.23 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 238516 kb
Host smart-26f4cb47-d1fd-4148-b8d9-5240f13005e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080261012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3080261012
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.232804337
Short name T329
Test name
Test status
Simulation time 7934339130 ps
CPU time 11.88 seconds
Started Dec 24 02:07:10 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 238700 kb
Host smart-85f7422e-c14e-4470-86f0-3b3882c8ff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232804337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.232804337
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.2327838134
Short name T707
Test name
Test status
Simulation time 105154614 ps
CPU time 3.19 seconds
Started Dec 24 02:07:06 PM PST 23
Finished Dec 24 02:07:19 PM PST 23
Peak memory 238452 kb
Host smart-9148fcf4-04ed-4bcc-b52c-a533dcb41846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327838134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.2327838134
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.1644621683
Short name T994
Test name
Test status
Simulation time 4345008397 ps
CPU time 19.76 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 246816 kb
Host smart-956a78f2-7e04-4284-b9a8-0e3bb22d1562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644621683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1644621683
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.1296402893
Short name T333
Test name
Test status
Simulation time 3685734455 ps
CPU time 22.67 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:07:35 PM PST 23
Peak memory 238688 kb
Host smart-8e731b57-6ceb-4afe-bbbe-5b0a0dd0c041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296402893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1296402893
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.4014917313
Short name T93
Test name
Test status
Simulation time 224725405 ps
CPU time 6.89 seconds
Started Dec 24 02:07:06 PM PST 23
Finished Dec 24 02:07:22 PM PST 23
Peak memory 238440 kb
Host smart-6f8f9e04-e9ff-4789-a08f-a2437f7ce89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014917313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.4014917313
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.1066779451
Short name T756
Test name
Test status
Simulation time 374878689 ps
CPU time 10.79 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:13 PM PST 23
Peak memory 238368 kb
Host smart-436b8636-2d7c-4d02-8071-3440234ad572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066779451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.1066779451
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.502941813
Short name T548
Test name
Test status
Simulation time 426237079 ps
CPU time 5.43 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 238500 kb
Host smart-2cee277b-e497-479d-a5e4-5ddd5e6a26e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502941813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.502941813
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.1726922502
Short name T638
Test name
Test status
Simulation time 200934831 ps
CPU time 3.42 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:12 PM PST 23
Peak memory 246560 kb
Host smart-90e9a8a8-c6fc-43f2-9d6d-419c277b9475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726922502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1726922502
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.2973180750
Short name T913
Test name
Test status
Simulation time 4064672022 ps
CPU time 19.88 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 238000 kb
Host smart-c666c473-f9fd-4198-8691-255703232bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973180750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.2973180750
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2838323909
Short name T815
Test name
Test status
Simulation time 4284955419201 ps
CPU time 6987.02 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 04:03:37 PM PST 23
Peak memory 1239400 kb
Host smart-fda0d0ed-e5b6-473f-9ffe-36415c491322
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838323909 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.2838323909
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.1510892615
Short name T1099
Test name
Test status
Simulation time 822090370 ps
CPU time 16.43 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:26 PM PST 23
Peak memory 237676 kb
Host smart-df85c68a-edbd-40b9-bf04-3a043fb1c7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510892615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1510892615
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.2625091532
Short name T70
Test name
Test status
Simulation time 293475397 ps
CPU time 3.57 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:22 PM PST 23
Peak memory 240792 kb
Host smart-194ed12b-159d-4f6c-b535-ee6ba5f1564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625091532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2625091532
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.2558767447
Short name T933
Test name
Test status
Simulation time 138463315 ps
CPU time 3.44 seconds
Started Dec 24 02:09:08 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 238472 kb
Host smart-6ce77cc7-d8f9-42fb-9ff5-5273dd2e3a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558767447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.2558767447
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.1707974521
Short name T1096
Test name
Test status
Simulation time 174566950 ps
CPU time 3.32 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:22 PM PST 23
Peak memory 240876 kb
Host smart-3e33b600-8a76-49b1-8bdf-1e95f7f13fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707974521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1707974521
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.792618432
Short name T137
Test name
Test status
Simulation time 512166639 ps
CPU time 4.27 seconds
Started Dec 24 02:09:09 PM PST 23
Finished Dec 24 02:09:17 PM PST 23
Peak memory 240568 kb
Host smart-660f01fd-c10c-4e04-b921-a1aaea221003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792618432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.792618432
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3965734155
Short name T1285
Test name
Test status
Simulation time 139091356 ps
CPU time 4.76 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:21 PM PST 23
Peak memory 241152 kb
Host smart-94caceff-2b2d-47ac-bafe-7a4ff54b0b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965734155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3965734155
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.501853240
Short name T128
Test name
Test status
Simulation time 294210703 ps
CPU time 5.11 seconds
Started Dec 24 02:09:14 PM PST 23
Finished Dec 24 02:09:25 PM PST 23
Peak memory 238456 kb
Host smart-b45ebc33-8643-4c26-8e77-98d2fcb9948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501853240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.501853240
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.231097847
Short name T51
Test name
Test status
Simulation time 262618474 ps
CPU time 3.61 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:18 PM PST 23
Peak memory 240988 kb
Host smart-986c5701-b2f8-445a-989a-9f00f4b2d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231097847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.231097847
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.3062619717
Short name T761
Test name
Test status
Simulation time 453810331 ps
CPU time 3.16 seconds
Started Dec 24 02:09:13 PM PST 23
Finished Dec 24 02:09:22 PM PST 23
Peak memory 238332 kb
Host smart-c7cd05c4-674e-450f-9c15-386cda319495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062619717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.3062619717
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.3778041420
Short name T1019
Test name
Test status
Simulation time 80833328 ps
CPU time 1.6 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:13 PM PST 23
Peak memory 238140 kb
Host smart-d6303234-b1f1-4249-95f0-180f121d1434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778041420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3778041420
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.355215145
Short name T662
Test name
Test status
Simulation time 913223319 ps
CPU time 10.83 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:37 PM PST 23
Peak memory 238440 kb
Host smart-af275f67-0a58-4060-832b-77bbe1fe67cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355215145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.355215145
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.844414190
Short name T718
Test name
Test status
Simulation time 1573737549 ps
CPU time 5.55 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:12 PM PST 23
Peak memory 246616 kb
Host smart-3d3db163-8009-4126-b593-fc0c411c51ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844414190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.844414190
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2959379797
Short name T613
Test name
Test status
Simulation time 206204289 ps
CPU time 3.78 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 238508 kb
Host smart-ffdb0cb3-4192-4886-9bd7-8da92da94020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959379797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2959379797
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.1329367172
Short name T409
Test name
Test status
Simulation time 196051038 ps
CPU time 4.19 seconds
Started Dec 24 02:07:08 PM PST 23
Finished Dec 24 02:07:22 PM PST 23
Peak memory 238388 kb
Host smart-7648f2fb-b655-4457-a443-3c1fa426ba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329367172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1329367172
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.1247540737
Short name T1196
Test name
Test status
Simulation time 702289761 ps
CPU time 16.97 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:25 PM PST 23
Peak memory 246836 kb
Host smart-bed2894b-c866-4971-8755-97f5477ab92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247540737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.1247540737
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.3231357238
Short name T1255
Test name
Test status
Simulation time 1996565104 ps
CPU time 16.9 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 238544 kb
Host smart-db728377-0443-4494-93bc-99e50566d00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231357238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3231357238
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.3073396962
Short name T1161
Test name
Test status
Simulation time 109367544 ps
CPU time 5.72 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 244460 kb
Host smart-a4a3ce21-25f9-4725-a3e7-aed0e1211b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073396962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.3073396962
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.1426708220
Short name T342
Test name
Test status
Simulation time 516681793 ps
CPU time 13.43 seconds
Started Dec 24 02:07:00 PM PST 23
Finished Dec 24 02:07:24 PM PST 23
Peak memory 243392 kb
Host smart-ed8df911-9853-4fb5-9970-f689c0af1dae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426708220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1426708220
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.2515866151
Short name T1235
Test name
Test status
Simulation time 399503965 ps
CPU time 3.3 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 238480 kb
Host smart-0803e541-e0f4-423d-9cd6-b106e9131df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515866151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.2515866151
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.1914751514
Short name T697
Test name
Test status
Simulation time 903923935 ps
CPU time 7.26 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 238540 kb
Host smart-4936d117-9eb8-4ce1-8da7-b4b45c59f7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914751514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1914751514
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.1567929017
Short name T824
Test name
Test status
Simulation time 241339323226 ps
CPU time 2252.74 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:44:59 PM PST 23
Peak memory 290700 kb
Host smart-002b8224-9e74-45ec-9794-937cb608bac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567929017 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.1567929017
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.1181716167
Short name T701
Test name
Test status
Simulation time 1983742765 ps
CPU time 12.86 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:07:25 PM PST 23
Peak memory 238500 kb
Host smart-d891cec7-7d1e-4aa5-89c9-333772443de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181716167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1181716167
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.1117330882
Short name T909
Test name
Test status
Simulation time 367566216 ps
CPU time 4.58 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 243340 kb
Host smart-9d1d0dad-d6cf-43f9-901b-16f34cc88412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117330882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.1117330882
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.2238076292
Short name T864
Test name
Test status
Simulation time 493129864 ps
CPU time 3.93 seconds
Started Dec 24 02:09:16 PM PST 23
Finished Dec 24 02:09:32 PM PST 23
Peak memory 240900 kb
Host smart-3880a6e1-7742-46be-97bf-a721ffbb5694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238076292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.2238076292
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.634712268
Short name T698
Test name
Test status
Simulation time 690382627 ps
CPU time 4.67 seconds
Started Dec 24 02:09:14 PM PST 23
Finished Dec 24 02:09:25 PM PST 23
Peak memory 241204 kb
Host smart-b11905e6-5ce1-4867-84c7-e01d02d55fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634712268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.634712268
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.601086455
Short name T129
Test name
Test status
Simulation time 2054243754 ps
CPU time 4.29 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:20 PM PST 23
Peak memory 238324 kb
Host smart-3d6c5e6c-e021-47c5-aa0d-cbe04448a5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601086455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.601086455
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.2364930723
Short name T1203
Test name
Test status
Simulation time 351037125 ps
CPU time 4.63 seconds
Started Dec 24 02:09:15 PM PST 23
Finished Dec 24 02:09:31 PM PST 23
Peak memory 238496 kb
Host smart-d0920a4e-5cb6-45f2-aec8-e3315711191a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364930723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2364930723
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.2391262032
Short name T471
Test name
Test status
Simulation time 541084661 ps
CPU time 4.8 seconds
Started Dec 24 02:09:13 PM PST 23
Finished Dec 24 02:09:24 PM PST 23
Peak memory 238400 kb
Host smart-d6a50f12-c403-493c-976b-56b75ea41dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391262032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2391262032
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.1754752920
Short name T571
Test name
Test status
Simulation time 2074334000 ps
CPU time 4.63 seconds
Started Dec 24 02:09:09 PM PST 23
Finished Dec 24 02:09:16 PM PST 23
Peak memory 238448 kb
Host smart-0badfd9b-33a3-40f2-b5de-768010028df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754752920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.1754752920
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.1933086105
Short name T575
Test name
Test status
Simulation time 2615141213 ps
CPU time 5.4 seconds
Started Dec 24 02:09:11 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 241740 kb
Host smart-73c5588f-2e77-46ff-9c26-e7a4dd192af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933086105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1933086105
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.637403658
Short name T811
Test name
Test status
Simulation time 106898981 ps
CPU time 3.68 seconds
Started Dec 24 02:09:16 PM PST 23
Finished Dec 24 02:09:32 PM PST 23
Peak memory 238380 kb
Host smart-6869b47a-9f26-40df-ae15-191775fa574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637403658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.637403658
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.3458056725
Short name T936
Test name
Test status
Simulation time 333984500 ps
CPU time 3.87 seconds
Started Dec 24 02:09:11 PM PST 23
Finished Dec 24 02:09:21 PM PST 23
Peak memory 238576 kb
Host smart-c79fee8f-373c-4f99-bdb8-870bf991604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458056725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3458056725
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.564830232
Short name T15
Test name
Test status
Simulation time 96297537 ps
CPU time 1.63 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:15 PM PST 23
Peak memory 239300 kb
Host smart-8aebc591-720e-4d2a-b464-6d8704ef313b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564830232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.564830232
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.1680408500
Short name T47
Test name
Test status
Simulation time 4757408287 ps
CPU time 7.59 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 238668 kb
Host smart-997e5163-41da-4068-a00c-474d59ea1f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680408500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.1680408500
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.2869318005
Short name T939
Test name
Test status
Simulation time 1804779407 ps
CPU time 5.43 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 242172 kb
Host smart-8944e1be-12c3-4d8d-9a41-459404db885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869318005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.2869318005
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.2665526590
Short name T455
Test name
Test status
Simulation time 377625104 ps
CPU time 8.58 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:34 PM PST 23
Peak memory 238540 kb
Host smart-f618f0d5-8b10-4544-9aa6-7a87b3a60515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665526590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2665526590
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.2155176084
Short name T138
Test name
Test status
Simulation time 225929374 ps
CPU time 3.37 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 238428 kb
Host smart-38f090a9-0cdc-4473-9116-e3995efce942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155176084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2155176084
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.4285164378
Short name T1211
Test name
Test status
Simulation time 3472935563 ps
CPU time 17.09 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 241032 kb
Host smart-2b139c13-4574-4e96-b005-f87da8efbce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285164378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.4285164378
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.1702646188
Short name T6
Test name
Test status
Simulation time 13083141156 ps
CPU time 28.32 seconds
Started Dec 24 02:07:09 PM PST 23
Finished Dec 24 02:07:48 PM PST 23
Peak memory 238600 kb
Host smart-65094ce6-6875-4063-a1a1-9849f1f4ad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702646188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.1702646188
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.831251035
Short name T917
Test name
Test status
Simulation time 221866103 ps
CPU time 5.75 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 242932 kb
Host smart-239080e1-94e0-4cd1-8d8c-01bd1826df85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831251035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.831251035
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.2134867543
Short name T1074
Test name
Test status
Simulation time 773730920 ps
CPU time 19.37 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:31 PM PST 23
Peak memory 238380 kb
Host smart-625ac025-3dd7-44c0-af2f-7b551c124e9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134867543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2134867543
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.2705054632
Short name T1168
Test name
Test status
Simulation time 368301261 ps
CPU time 3.61 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 238504 kb
Host smart-372151e4-4557-4650-90b7-c80bf1ce9c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705054632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2705054632
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.2703057096
Short name T554
Test name
Test status
Simulation time 265310556 ps
CPU time 7.2 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:34 PM PST 23
Peak memory 242476 kb
Host smart-0b151721-1b13-4f71-93b7-6c6519c275ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703057096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2703057096
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.3202541854
Short name T704
Test name
Test status
Simulation time 122277097898 ps
CPU time 1501.13 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:32:08 PM PST 23
Peak memory 377148 kb
Host smart-f3a3f8cf-ecf3-4d48-8ac9-55ec2e19db99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202541854 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.3202541854
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.1346848094
Short name T741
Test name
Test status
Simulation time 2767186946 ps
CPU time 5.35 seconds
Started Dec 24 02:06:59 PM PST 23
Finished Dec 24 02:07:14 PM PST 23
Peak memory 241212 kb
Host smart-17db8889-2cc1-4b9c-abcd-f4c1c3548e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346848094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.1346848094
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.678795656
Short name T1205
Test name
Test status
Simulation time 1851793816 ps
CPU time 7.14 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:26 PM PST 23
Peak memory 241204 kb
Host smart-f226d1e5-8e63-43d3-9c25-39f1dd7692c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678795656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.678795656
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.192566975
Short name T960
Test name
Test status
Simulation time 149803337 ps
CPU time 3.71 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 238232 kb
Host smart-22a8591e-a1a7-4b0b-9b80-b4e786706c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192566975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.192566975
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.2081758800
Short name T1210
Test name
Test status
Simulation time 453300133 ps
CPU time 3.67 seconds
Started Dec 24 02:09:16 PM PST 23
Finished Dec 24 02:09:32 PM PST 23
Peak memory 241040 kb
Host smart-9370e246-32c8-4bd0-9a1e-9993ccb10c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081758800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2081758800
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.2518259331
Short name T1117
Test name
Test status
Simulation time 278846531 ps
CPU time 3.45 seconds
Started Dec 24 02:09:19 PM PST 23
Finished Dec 24 02:09:34 PM PST 23
Peak memory 238436 kb
Host smart-21a1bd3d-dc1c-4b42-89c4-f4be2de54227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518259331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2518259331
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.3756618076
Short name T465
Test name
Test status
Simulation time 569322661 ps
CPU time 4.67 seconds
Started Dec 24 02:09:09 PM PST 23
Finished Dec 24 02:09:19 PM PST 23
Peak memory 238372 kb
Host smart-8f9ce2b8-d103-48b7-beae-a8001c78bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756618076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3756618076
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.3798791996
Short name T675
Test name
Test status
Simulation time 1857641606 ps
CPU time 4.48 seconds
Started Dec 24 02:09:08 PM PST 23
Finished Dec 24 02:09:15 PM PST 23
Peak memory 241324 kb
Host smart-fe339f0d-847f-4f97-85ac-75c07989ef30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798791996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3798791996
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.2826067571
Short name T57
Test name
Test status
Simulation time 325005953 ps
CPU time 4.56 seconds
Started Dec 24 02:09:08 PM PST 23
Finished Dec 24 02:09:15 PM PST 23
Peak memory 238444 kb
Host smart-66751a2a-9bf4-49c9-9a5c-ef3f110e52ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826067571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2826067571
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.3025589952
Short name T144
Test name
Test status
Simulation time 129073603 ps
CPU time 3.87 seconds
Started Dec 24 02:09:08 PM PST 23
Finished Dec 24 02:09:15 PM PST 23
Peak memory 240984 kb
Host smart-9bedfaa4-a11d-4bee-8094-d91930266773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025589952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3025589952
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.1047733631
Short name T776
Test name
Test status
Simulation time 369876936 ps
CPU time 3.55 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:18 PM PST 23
Peak memory 241076 kb
Host smart-78e10693-f599-4178-baa0-89ca448e17bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047733631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1047733631
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.41408939
Short name T830
Test name
Test status
Simulation time 385906025 ps
CPU time 5.01 seconds
Started Dec 24 02:09:13 PM PST 23
Finished Dec 24 02:09:24 PM PST 23
Peak memory 238512 kb
Host smart-ee59500d-2b0b-42a6-b7f9-8fe9a3178dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41408939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.41408939
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.2703343809
Short name T500
Test name
Test status
Simulation time 164925656 ps
CPU time 1.65 seconds
Started Dec 24 02:07:17 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 238204 kb
Host smart-7bb05ce6-bdd1-48f3-89c4-7a251b8ed8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703343809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2703343809
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.3124917131
Short name T290
Test name
Test status
Simulation time 1116032698 ps
CPU time 6.04 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 241452 kb
Host smart-180e14f5-7339-4fc6-9e6e-77dacc411dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124917131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3124917131
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.2420386798
Short name T477
Test name
Test status
Simulation time 150179304 ps
CPU time 6.06 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 238320 kb
Host smart-a8e50ae8-6f97-4213-b439-cc546f3f5fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420386798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2420386798
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.1693455688
Short name T666
Test name
Test status
Simulation time 3068326303 ps
CPU time 21.88 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:07:34 PM PST 23
Peak memory 246184 kb
Host smart-5c4f3e2d-d25b-409b-873a-0161cef29bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693455688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.1693455688
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.3827745815
Short name T149
Test name
Test status
Simulation time 442673713 ps
CPU time 3.03 seconds
Started Dec 24 02:07:03 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 240776 kb
Host smart-f1dd628b-e222-49ca-9bdd-12e6392cc095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827745815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3827745815
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.463056196
Short name T1245
Test name
Test status
Simulation time 1248337858 ps
CPU time 7.38 seconds
Started Dec 24 02:07:03 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 238568 kb
Host smart-4ffbaeec-2adb-4e29-9f42-b0841ac3c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463056196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.463056196
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.4199854524
Short name T1188
Test name
Test status
Simulation time 803856121 ps
CPU time 10.01 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:07:22 PM PST 23
Peak memory 238436 kb
Host smart-8dc5640b-d09a-4d86-ac58-b8f3be9df1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199854524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.4199854524
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1611503672
Short name T174
Test name
Test status
Simulation time 169999802 ps
CPU time 6.28 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 238508 kb
Host smart-cefd5d42-b879-42d5-b8a8-a757bf965f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611503672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1611503672
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.1930454915
Short name T1195
Test name
Test status
Simulation time 821232607 ps
CPU time 6.39 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:07:19 PM PST 23
Peak memory 238496 kb
Host smart-482db0ac-4623-4f42-80c3-30e677de2e33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930454915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.1930454915
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.437770334
Short name T507
Test name
Test status
Simulation time 246540315 ps
CPU time 4.41 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 238636 kb
Host smart-2ea3e363-3cfa-4837-af36-47e7ea9d34d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=437770334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.437770334
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.1393215975
Short name T972
Test name
Test status
Simulation time 133452124 ps
CPU time 2.98 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:09 PM PST 23
Peak memory 238508 kb
Host smart-a8a965fe-0094-4f3a-939c-90ba0fe3863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393215975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1393215975
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.3205186903
Short name T608
Test name
Test status
Simulation time 567061743 ps
CPU time 5.02 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 242180 kb
Host smart-9f95963f-71a7-463e-b409-753fe7f02e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205186903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3205186903
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.3117385290
Short name T466
Test name
Test status
Simulation time 344379586 ps
CPU time 5.04 seconds
Started Dec 24 02:09:25 PM PST 23
Finished Dec 24 02:09:38 PM PST 23
Peak memory 238444 kb
Host smart-22a37504-966c-447c-9f6a-ab4e07cec091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117385290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3117385290
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.229783309
Short name T81
Test name
Test status
Simulation time 148838022 ps
CPU time 3.74 seconds
Started Dec 24 02:09:13 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 238484 kb
Host smart-fc69736b-b4bd-4989-b17c-5fe0b02b5ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229783309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.229783309
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.1981494577
Short name T435
Test name
Test status
Simulation time 144833230 ps
CPU time 3.24 seconds
Started Dec 24 02:09:08 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 238456 kb
Host smart-48da6889-31a0-40a5-92fe-fe8d40e1e380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981494577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1981494577
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.259147707
Short name T1010
Test name
Test status
Simulation time 281176894 ps
CPU time 4.82 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:38 PM PST 23
Peak memory 243160 kb
Host smart-2127e7e8-a562-4f24-892a-9d28f0a10753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259147707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.259147707
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.2272855301
Short name T888
Test name
Test status
Simulation time 121051841 ps
CPU time 3.36 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:36 PM PST 23
Peak memory 246628 kb
Host smart-4b60ed4c-61d8-408b-8184-914937808f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272855301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2272855301
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1322681164
Short name T131
Test name
Test status
Simulation time 231961494 ps
CPU time 3.59 seconds
Started Dec 24 02:09:24 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 238308 kb
Host smart-54b474bc-dc2d-4e86-880d-3982cf3d6624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322681164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1322681164
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.413720855
Short name T153
Test name
Test status
Simulation time 211532050 ps
CPU time 3.26 seconds
Started Dec 24 02:09:14 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 238440 kb
Host smart-74046532-f7c9-4135-bece-7ab6aaeb3caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413720855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.413720855
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.3587155149
Short name T553
Test name
Test status
Simulation time 280306747 ps
CPU time 3.52 seconds
Started Dec 24 02:09:24 PM PST 23
Finished Dec 24 02:09:36 PM PST 23
Peak memory 238500 kb
Host smart-eafcd93a-c9aa-43dd-9f40-bf3efa431571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587155149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3587155149
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.3833439935
Short name T413
Test name
Test status
Simulation time 755825265 ps
CPU time 1.69 seconds
Started Dec 24 02:07:16 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 238520 kb
Host smart-fbead85b-924c-49a4-b9f9-f05d2935ce6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833439935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.3833439935
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.534568395
Short name T668
Test name
Test status
Simulation time 202212550 ps
CPU time 3.74 seconds
Started Dec 24 02:07:19 PM PST 23
Finished Dec 24 02:07:34 PM PST 23
Peak memory 238532 kb
Host smart-7db03634-8dfd-494e-93ef-2487b1b59bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534568395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.534568395
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.2561714540
Short name T1060
Test name
Test status
Simulation time 525901138 ps
CPU time 6.82 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 244116 kb
Host smart-dc1d1c48-8509-43c6-be99-6501acc132f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561714540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2561714540
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.1416920964
Short name T700
Test name
Test status
Simulation time 1096096335 ps
CPU time 8.6 seconds
Started Dec 24 02:07:15 PM PST 23
Finished Dec 24 02:07:35 PM PST 23
Peak memory 238516 kb
Host smart-9eddad71-7e13-4192-a853-8cb22466fddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416920964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1416920964
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.704690831
Short name T838
Test name
Test status
Simulation time 282963590 ps
CPU time 4.14 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 241384 kb
Host smart-69fcd359-4a6a-4ced-867c-90aa3dd97de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704690831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.704690831
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.4193820812
Short name T948
Test name
Test status
Simulation time 3190789661 ps
CPU time 19.19 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:45 PM PST 23
Peak memory 241268 kb
Host smart-02244e13-3d7d-4b25-9f54-a4529a807b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193820812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.4193820812
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.3219867803
Short name T711
Test name
Test status
Simulation time 166125774 ps
CPU time 4.33 seconds
Started Dec 24 02:07:16 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 238528 kb
Host smart-03fa84a4-8928-49fb-8c39-9aeaa83ec674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219867803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3219867803
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2662272976
Short name T677
Test name
Test status
Simulation time 280363909 ps
CPU time 3.71 seconds
Started Dec 24 02:07:03 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 241272 kb
Host smart-982882a2-8de5-409f-85ab-b50762dbdcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662272976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2662272976
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.30161275
Short name T783
Test name
Test status
Simulation time 5609251209 ps
CPU time 11.09 seconds
Started Dec 24 02:07:09 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 244184 kb
Host smart-d4d44e52-feb8-4411-8af5-f368f05b4bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30161275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.30161275
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.1758909252
Short name T818
Test name
Test status
Simulation time 2246308050 ps
CPU time 7.02 seconds
Started Dec 24 02:07:11 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 238644 kb
Host smart-805e8c58-4525-41c2-a9cb-8954fdc02bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758909252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1758909252
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.4229819485
Short name T928
Test name
Test status
Simulation time 48471804524 ps
CPU time 91.02 seconds
Started Dec 24 02:07:19 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 243356 kb
Host smart-63f5fd0c-7ed5-42bd-9c70-a9c80fdcd560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229819485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.4229819485
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.2803254018
Short name T170
Test name
Test status
Simulation time 3902280453 ps
CPU time 19.67 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:44 PM PST 23
Peak memory 238080 kb
Host smart-6330f3d0-1947-4554-a8c5-792123090fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803254018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2803254018
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.2047864033
Short name T758
Test name
Test status
Simulation time 389792542 ps
CPU time 3.31 seconds
Started Dec 24 02:09:20 PM PST 23
Finished Dec 24 02:09:34 PM PST 23
Peak memory 238392 kb
Host smart-0bb8dcc0-2f25-4ff2-a89d-81ca855ae036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047864033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2047864033
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.2853999999
Short name T66
Test name
Test status
Simulation time 295713087 ps
CPU time 4.71 seconds
Started Dec 24 02:09:15 PM PST 23
Finished Dec 24 02:09:29 PM PST 23
Peak memory 241096 kb
Host smart-f312488d-4af2-4e54-a389-ab943044a59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853999999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2853999999
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.837593047
Short name T545
Test name
Test status
Simulation time 155413346 ps
CPU time 3.94 seconds
Started Dec 24 02:09:25 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 238420 kb
Host smart-6e31ffc4-85eb-405a-b81b-679fcbefd9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837593047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.837593047
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.3006932352
Short name T672
Test name
Test status
Simulation time 166274205 ps
CPU time 3.81 seconds
Started Dec 24 02:09:20 PM PST 23
Finished Dec 24 02:09:36 PM PST 23
Peak memory 240844 kb
Host smart-9fe5a3b6-6a9a-44d6-890f-5d1a8621e5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006932352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3006932352
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.605052047
Short name T646
Test name
Test status
Simulation time 237238401 ps
CPU time 4.78 seconds
Started Dec 24 02:09:23 PM PST 23
Finished Dec 24 02:09:38 PM PST 23
Peak memory 238360 kb
Host smart-30f35c52-5f30-4741-8a21-08269e6bffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605052047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.605052047
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.607767998
Short name T879
Test name
Test status
Simulation time 256025591 ps
CPU time 4.61 seconds
Started Dec 24 02:09:23 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 240268 kb
Host smart-efab6fd4-2f36-4953-a2a6-9df61f989077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607767998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.607767998
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.985445241
Short name T416
Test name
Test status
Simulation time 144938066 ps
CPU time 2.95 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:22 PM PST 23
Peak memory 246592 kb
Host smart-9b71d871-405a-4b01-995e-47c852720f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985445241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.985445241
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.3021342065
Short name T1288
Test name
Test status
Simulation time 2282322719 ps
CPU time 5.69 seconds
Started Dec 24 02:09:11 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 241592 kb
Host smart-303a5b93-fbf8-427a-86a9-d80ba248d029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021342065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.3021342065
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.2485942113
Short name T565
Test name
Test status
Simulation time 394504629 ps
CPU time 3.62 seconds
Started Dec 24 02:09:24 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 240724 kb
Host smart-6d44362a-8a60-45a8-93f9-4d8e8468c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485942113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2485942113
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.2942664096
Short name T1126
Test name
Test status
Simulation time 159816080 ps
CPU time 1.54 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:24 PM PST 23
Peak memory 238140 kb
Host smart-c44171a4-6b4f-4cc0-b615-af827bbaf374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942664096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2942664096
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.2359896884
Short name T54
Test name
Test status
Simulation time 726558310 ps
CPU time 12.78 seconds
Started Dec 24 02:07:05 PM PST 23
Finished Dec 24 02:07:28 PM PST 23
Peak memory 238512 kb
Host smart-a3ec9007-0763-448a-9904-34074d1e5d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359896884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.2359896884
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.1143633378
Short name T121
Test name
Test status
Simulation time 242170228 ps
CPU time 6.01 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:31 PM PST 23
Peak memory 242160 kb
Host smart-97a4524b-1670-4b3e-9d8c-5078ddc09a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143633378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1143633378
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.1528532978
Short name T1046
Test name
Test status
Simulation time 893563325 ps
CPU time 6.55 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 238516 kb
Host smart-62c01f9c-c63e-4e57-b1a1-c04539453f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528532978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1528532978
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.1084006104
Short name T133
Test name
Test status
Simulation time 201432965 ps
CPU time 3.55 seconds
Started Dec 24 02:07:08 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 246636 kb
Host smart-0c3308e9-3451-45fc-b76a-9b201a9be86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084006104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.1084006104
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.3142354789
Short name T862
Test name
Test status
Simulation time 372368116 ps
CPU time 2.95 seconds
Started Dec 24 02:07:05 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 243268 kb
Host smart-169720ee-12ec-4ad4-8713-1609b6b08736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142354789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3142354789
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.4158308675
Short name T643
Test name
Test status
Simulation time 1713695120 ps
CPU time 12.97 seconds
Started Dec 24 02:07:03 PM PST 23
Finished Dec 24 02:07:26 PM PST 23
Peak memory 238564 kb
Host smart-e85550e3-700c-4026-b553-b71061152ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158308675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.4158308675
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.4025839104
Short name T705
Test name
Test status
Simulation time 263058935 ps
CPU time 3.58 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:28 PM PST 23
Peak memory 238428 kb
Host smart-992e6537-e020-4241-a969-e716aa2bf8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025839104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.4025839104
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.4036808632
Short name T995
Test name
Test status
Simulation time 6480268716 ps
CPU time 12.78 seconds
Started Dec 24 02:07:05 PM PST 23
Finished Dec 24 02:07:28 PM PST 23
Peak memory 238564 kb
Host smart-96b5e1a0-ad29-45a6-87fe-8950e31270d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036808632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.4036808632
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.1077704653
Short name T526
Test name
Test status
Simulation time 1576541936 ps
CPU time 3.5 seconds
Started Dec 24 02:07:07 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 243220 kb
Host smart-4b58a638-9ccd-4319-8ae1-8ad12205b13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077704653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.1077704653
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.3213854874
Short name T1125
Test name
Test status
Simulation time 1593560415 ps
CPU time 17.25 seconds
Started Dec 24 02:07:03 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 245656 kb
Host smart-c5cc6e1b-c606-4454-8499-7a37aacdc026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213854874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.3213854874
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.4202539699
Short name T453
Test name
Test status
Simulation time 1929862539136 ps
CPU time 6814.18 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 04:00:58 PM PST 23
Peak memory 1030984 kb
Host smart-239aca35-4652-4333-99a1-590c34608517
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202539699 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.4202539699
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.513625617
Short name T91
Test name
Test status
Simulation time 8320412713 ps
CPU time 42.39 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:57 PM PST 23
Peak memory 238564 kb
Host smart-2b76848b-9c27-42ed-b51c-b3c5718cb498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513625617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.513625617
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.3492556881
Short name T682
Test name
Test status
Simulation time 401470143 ps
CPU time 3.03 seconds
Started Dec 24 02:09:15 PM PST 23
Finished Dec 24 02:09:31 PM PST 23
Peak memory 238468 kb
Host smart-be12f6bb-2f43-4bb7-87fa-9b52f9ac453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492556881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.3492556881
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.2890386134
Short name T1193
Test name
Test status
Simulation time 163851003 ps
CPU time 3.85 seconds
Started Dec 24 02:09:13 PM PST 23
Finished Dec 24 02:09:24 PM PST 23
Peak memory 238412 kb
Host smart-d14022e9-de1b-4345-9523-d5ba1aac904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890386134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2890386134
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.3608026386
Short name T1039
Test name
Test status
Simulation time 231413586 ps
CPU time 3.84 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 241040 kb
Host smart-8669b855-6f55-46b9-8bfe-635049fe70b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608026386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3608026386
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2656361658
Short name T1181
Test name
Test status
Simulation time 322613623 ps
CPU time 3.65 seconds
Started Dec 24 02:09:18 PM PST 23
Finished Dec 24 02:09:34 PM PST 23
Peak memory 238408 kb
Host smart-319bd2d8-51f5-452e-a476-b0b9138b9324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656361658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2656361658
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.1043676967
Short name T415
Test name
Test status
Simulation time 269154350 ps
CPU time 4.57 seconds
Started Dec 24 02:09:19 PM PST 23
Finished Dec 24 02:09:35 PM PST 23
Peak memory 241280 kb
Host smart-a97fd297-629f-41d6-b5a8-a3f5e16bf74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043676967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.1043676967
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.941976783
Short name T211
Test name
Test status
Simulation time 555946178 ps
CPU time 4.84 seconds
Started Dec 24 02:09:17 PM PST 23
Finished Dec 24 02:09:34 PM PST 23
Peak memory 246600 kb
Host smart-94ef628b-aa8d-4398-aaae-c2ca1acab039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941976783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.941976783
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.2857967153
Short name T934
Test name
Test status
Simulation time 147983248 ps
CPU time 3.75 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 238396 kb
Host smart-c4019d6e-9b89-45c1-bca1-88b7451f29c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857967153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.2857967153
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1853922245
Short name T163
Test name
Test status
Simulation time 573558509 ps
CPU time 4.58 seconds
Started Dec 24 02:09:12 PM PST 23
Finished Dec 24 02:09:23 PM PST 23
Peak memory 241044 kb
Host smart-7536af3a-c35c-4ba2-847a-661f390f9979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853922245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1853922245
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.3784944316
Short name T48
Test name
Test status
Simulation time 523157124 ps
CPU time 4.27 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 238516 kb
Host smart-91d61d3f-193e-4bb8-941e-a89bfa2e4c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784944316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3784944316
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.1450570616
Short name T537
Test name
Test status
Simulation time 352782589 ps
CPU time 4.46 seconds
Started Dec 24 02:09:10 PM PST 23
Finished Dec 24 02:09:20 PM PST 23
Peak memory 240996 kb
Host smart-d0c17926-52b8-47f3-b685-ec39d32b1ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450570616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1450570616
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.4188761014
Short name T634
Test name
Test status
Simulation time 978860132 ps
CPU time 2.5 seconds
Started Dec 24 02:07:17 PM PST 23
Finished Dec 24 02:07:31 PM PST 23
Peak memory 238920 kb
Host smart-78743a0a-d3c9-4a32-91f6-9368fa633f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188761014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.4188761014
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.729178028
Short name T63
Test name
Test status
Simulation time 838460463 ps
CPU time 8.14 seconds
Started Dec 24 02:07:22 PM PST 23
Finished Dec 24 02:07:41 PM PST 23
Peak memory 246720 kb
Host smart-c694d8b7-b067-409d-858d-e576643b379b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729178028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.729178028
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.2787748259
Short name T1124
Test name
Test status
Simulation time 422680432 ps
CPU time 9.96 seconds
Started Dec 24 02:07:05 PM PST 23
Finished Dec 24 02:07:25 PM PST 23
Peak memory 238540 kb
Host smart-a6af1503-22da-46f7-a2a9-e8b5c80d9852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787748259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.2787748259
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.746802401
Short name T977
Test name
Test status
Simulation time 3565085113 ps
CPU time 5.72 seconds
Started Dec 24 02:07:02 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 244372 kb
Host smart-77bb9fbb-d557-4c25-9e35-1302b3fb65cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746802401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.746802401
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.2147256428
Short name T9
Test name
Test status
Simulation time 141220428 ps
CPU time 3.42 seconds
Started Dec 24 02:07:06 PM PST 23
Finished Dec 24 02:07:19 PM PST 23
Peak memory 240824 kb
Host smart-db8807a6-b2fd-4e45-ab7c-11a16981bf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147256428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.2147256428
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.215630542
Short name T990
Test name
Test status
Simulation time 8077544827 ps
CPU time 14.42 seconds
Started Dec 24 02:07:03 PM PST 23
Finished Dec 24 02:07:28 PM PST 23
Peak memory 246728 kb
Host smart-df31c7ed-6234-4500-8ecd-198f5ed1182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215630542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.215630542
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.775066586
Short name T1065
Test name
Test status
Simulation time 1434758597 ps
CPU time 15.5 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 238444 kb
Host smart-70b6ff5f-170c-4644-b12d-21e5d0cf61ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775066586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.775066586
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.3704049947
Short name T935
Test name
Test status
Simulation time 131739329 ps
CPU time 4.21 seconds
Started Dec 24 02:07:07 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 238224 kb
Host smart-bc1233c9-7803-46dc-b777-16c48667866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704049947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3704049947
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2847739334
Short name T331
Test name
Test status
Simulation time 520714141 ps
CPU time 14 seconds
Started Dec 24 02:07:15 PM PST 23
Finished Dec 24 02:07:42 PM PST 23
Peak memory 238520 kb
Host smart-8cf56fa3-3bbb-4005-861f-95ffd2978ddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2847739334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2847739334
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.2784718077
Short name T1116
Test name
Test status
Simulation time 310152489 ps
CPU time 9.91 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:24 PM PST 23
Peak memory 237364 kb
Host smart-69c7c1fa-f66f-47c1-9582-e14b9027d09d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784718077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2784718077
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.1197758924
Short name T1262
Test name
Test status
Simulation time 3262105772 ps
CPU time 7.56 seconds
Started Dec 24 02:07:06 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 243300 kb
Host smart-e003f30b-d72f-43bf-86ac-ec5432c462eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197758924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.1197758924
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.415075302
Short name T712
Test name
Test status
Simulation time 234989464314 ps
CPU time 1728.14 seconds
Started Dec 24 02:07:06 PM PST 23
Finished Dec 24 02:36:04 PM PST 23
Peak memory 315296 kb
Host smart-ef69e4a5-03b8-427c-bf4d-02db34b086d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415075302 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.415075302
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.3724490678
Short name T1232
Test name
Test status
Simulation time 406982699 ps
CPU time 4.53 seconds
Started Dec 24 02:07:11 PM PST 23
Finished Dec 24 02:07:27 PM PST 23
Peak memory 243564 kb
Host smart-ef714995-2b5f-46ce-a86a-767728011321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724490678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.3724490678
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.183314381
Short name T592
Test name
Test status
Simulation time 474800571 ps
CPU time 4.79 seconds
Started Dec 24 02:09:15 PM PST 23
Finished Dec 24 02:09:30 PM PST 23
Peak memory 241244 kb
Host smart-3cb21c63-a2f1-41e8-8faf-36f27ccb94a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183314381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.183314381
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.714558971
Short name T656
Test name
Test status
Simulation time 2753267264 ps
CPU time 7.87 seconds
Started Dec 24 02:09:24 PM PST 23
Finished Dec 24 02:09:41 PM PST 23
Peak memory 238484 kb
Host smart-06fa8ed0-fa30-4961-9f85-21c2d81ea52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714558971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.714558971
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.1842506692
Short name T678
Test name
Test status
Simulation time 352767851 ps
CPU time 4.11 seconds
Started Dec 24 02:09:14 PM PST 23
Finished Dec 24 02:09:24 PM PST 23
Peak memory 238464 kb
Host smart-5d2bf918-9768-43ee-b8fc-e059e3f97c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842506692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1842506692
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.115620289
Short name T568
Test name
Test status
Simulation time 2500049875 ps
CPU time 7.47 seconds
Started Dec 24 02:09:24 PM PST 23
Finished Dec 24 02:09:41 PM PST 23
Peak memory 241168 kb
Host smart-398bebc3-b6f9-4cef-8178-ededef5d2854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115620289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.115620289
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.2664704485
Short name T1153
Test name
Test status
Simulation time 394358199 ps
CPU time 3.88 seconds
Started Dec 24 02:09:23 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 240760 kb
Host smart-f224ab80-afa1-4c76-b59a-e595bd39c041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664704485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2664704485
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.3084028299
Short name T953
Test name
Test status
Simulation time 260968386 ps
CPU time 3.78 seconds
Started Dec 24 02:09:20 PM PST 23
Finished Dec 24 02:09:35 PM PST 23
Peak memory 238472 kb
Host smart-ced417fd-1a02-4339-af87-af70d679269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084028299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.3084028299
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.205332802
Short name T1102
Test name
Test status
Simulation time 132692360 ps
CPU time 4.03 seconds
Started Dec 24 02:09:26 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 240356 kb
Host smart-cac80cbb-2ae2-4400-b290-0934f752067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205332802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.205332802
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.4262308972
Short name T1194
Test name
Test status
Simulation time 2418828214 ps
CPU time 5.06 seconds
Started Dec 24 02:09:22 PM PST 23
Finished Dec 24 02:09:38 PM PST 23
Peak memory 238528 kb
Host smart-de3f00df-eed4-49ba-a51a-746a79aff86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262308972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.4262308972
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.2981801092
Short name T40
Test name
Test status
Simulation time 1893442259 ps
CPU time 4.1 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 238440 kb
Host smart-ccc633b7-b14e-4790-9541-12322d45eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981801092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.2981801092
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.1114057962
Short name T740
Test name
Test status
Simulation time 46312049 ps
CPU time 1.57 seconds
Started Dec 24 02:07:18 PM PST 23
Finished Dec 24 02:07:31 PM PST 23
Peak memory 238252 kb
Host smart-637416f2-9d63-455d-8e1a-d4fc8433ee84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114057962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1114057962
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.3087788114
Short name T911
Test name
Test status
Simulation time 480398988 ps
CPU time 3.35 seconds
Started Dec 24 02:07:07 PM PST 23
Finished Dec 24 02:07:20 PM PST 23
Peak memory 238444 kb
Host smart-5ae852a0-0ad6-4179-859e-b855332a52fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087788114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.3087788114
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.1455598469
Short name T723
Test name
Test status
Simulation time 2781712964 ps
CPU time 10.59 seconds
Started Dec 24 02:07:10 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 238708 kb
Host smart-ecbc5389-fc7f-422e-b584-1687862e2244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455598469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1455598469
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.3280628927
Short name T475
Test name
Test status
Simulation time 2756172349 ps
CPU time 15.45 seconds
Started Dec 24 02:07:16 PM PST 23
Finished Dec 24 02:07:44 PM PST 23
Peak memory 238700 kb
Host smart-c8843ff9-b0c3-4171-a89e-47fcecfcebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280628927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.3280628927
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.2607926120
Short name T555
Test name
Test status
Simulation time 2323839037 ps
CPU time 5.97 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 238524 kb
Host smart-3602ff39-93e6-48a5-bec1-8081ac563e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607926120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2607926120
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.3082187659
Short name T123
Test name
Test status
Simulation time 1615669717 ps
CPU time 14.21 seconds
Started Dec 24 02:07:05 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 243708 kb
Host smart-ace54305-70ce-406d-81d6-17c3e962344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082187659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.3082187659
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.2184583876
Short name T410
Test name
Test status
Simulation time 1900382338 ps
CPU time 4.21 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:27 PM PST 23
Peak memory 238604 kb
Host smart-fbee0c45-4b31-43fa-828b-e15a04a5c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184583876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2184583876
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.2511176152
Short name T817
Test name
Test status
Simulation time 177197893 ps
CPU time 2.51 seconds
Started Dec 24 02:07:05 PM PST 23
Finished Dec 24 02:07:17 PM PST 23
Peak memory 232276 kb
Host smart-244b5d91-94da-47e9-97a8-e756031000ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511176152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2511176152
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.3188984502
Short name T844
Test name
Test status
Simulation time 440238892 ps
CPU time 12.67 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:39 PM PST 23
Peak memory 238448 kb
Host smart-fd70d877-a6b7-4037-bda4-c8e55878b95e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188984502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3188984502
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.997222038
Short name T859
Test name
Test status
Simulation time 370794410 ps
CPU time 4.27 seconds
Started Dec 24 02:07:04 PM PST 23
Finished Dec 24 02:07:18 PM PST 23
Peak memory 242856 kb
Host smart-d7f5a543-8c84-4cff-81a5-405fb6044b55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997222038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.997222038
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.2833204883
Short name T658
Test name
Test status
Simulation time 297079616 ps
CPU time 6.07 seconds
Started Dec 24 02:07:05 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 243188 kb
Host smart-78f66b17-0079-4ef7-a1ac-9c5a2a245ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833204883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.2833204883
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.2164736870
Short name T945
Test name
Test status
Simulation time 26765410858 ps
CPU time 67.62 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 246832 kb
Host smart-d5fa22a4-38e7-48f3-a752-964cca858c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164736870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.2164736870
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2641954443
Short name T919
Test name
Test status
Simulation time 902502518186 ps
CPU time 8349.08 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 04:26:33 PM PST 23
Peak memory 1650020 kb
Host smart-38b16cc1-ab71-406f-9f8d-d0e53157bede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641954443 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.2641954443
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.1139090232
Short name T148
Test name
Test status
Simulation time 376230484 ps
CPU time 3.9 seconds
Started Dec 24 02:09:28 PM PST 23
Finished Dec 24 02:09:39 PM PST 23
Peak memory 241084 kb
Host smart-c2639f3d-47f8-45c8-9984-81f28a2573d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139090232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.1139090232
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.3124315438
Short name T1037
Test name
Test status
Simulation time 1701256100 ps
CPU time 6.68 seconds
Started Dec 24 02:09:28 PM PST 23
Finished Dec 24 02:09:42 PM PST 23
Peak memory 240452 kb
Host smart-d52aa42b-bea4-46a8-a59c-307ad765878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124315438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3124315438
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.2776582299
Short name T408
Test name
Test status
Simulation time 147971370 ps
CPU time 5.04 seconds
Started Dec 24 02:09:35 PM PST 23
Finished Dec 24 02:09:44 PM PST 23
Peak memory 241088 kb
Host smart-7e6e1154-adae-431f-b5ad-93fbb298fddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776582299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2776582299
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.435023778
Short name T591
Test name
Test status
Simulation time 325237517 ps
CPU time 4.46 seconds
Started Dec 24 02:09:24 PM PST 23
Finished Dec 24 02:09:38 PM PST 23
Peak memory 238508 kb
Host smart-2965f44c-c3b5-4a8b-8f25-b73bfb48e174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435023778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.435023778
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.1117907503
Short name T498
Test name
Test status
Simulation time 150363507 ps
CPU time 4.98 seconds
Started Dec 24 02:09:35 PM PST 23
Finished Dec 24 02:09:44 PM PST 23
Peak memory 240408 kb
Host smart-a7fd506a-aea4-46fe-9791-d953277453bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117907503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1117907503
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.2210920100
Short name T210
Test name
Test status
Simulation time 470463472 ps
CPU time 3.59 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:36 PM PST 23
Peak memory 246644 kb
Host smart-bb8bcdcf-22e1-472a-b813-c75b27943526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210920100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2210920100
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.2094481792
Short name T876
Test name
Test status
Simulation time 1568805395 ps
CPU time 6.08 seconds
Started Dec 24 02:09:26 PM PST 23
Finished Dec 24 02:09:40 PM PST 23
Peak memory 241108 kb
Host smart-739a7a4b-ed56-4c7d-8433-f14048ff84f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094481792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2094481792
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.2024365571
Short name T451
Test name
Test status
Simulation time 251734716 ps
CPU time 3.82 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 238448 kb
Host smart-bb968422-1dd3-4990-9eb3-128006c3c155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024365571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2024365571
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.4207594600
Short name T85
Test name
Test status
Simulation time 329411911 ps
CPU time 4.74 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 241064 kb
Host smart-3e09123e-5036-4631-975f-43f8e8c82862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207594600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.4207594600
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.340296179
Short name T699
Test name
Test status
Simulation time 796507757 ps
CPU time 2.12 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:25 PM PST 23
Peak memory 239412 kb
Host smart-431ce994-4242-41b2-ab23-b8c7f4715036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340296179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.340296179
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.3647386852
Short name T941
Test name
Test status
Simulation time 8731061836 ps
CPU time 19.17 seconds
Started Dec 24 02:07:16 PM PST 23
Finished Dec 24 02:07:47 PM PST 23
Peak memory 238780 kb
Host smart-e529e8a1-5ea8-408e-9a75-e9ba2636e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647386852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3647386852
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.3823784004
Short name T566
Test name
Test status
Simulation time 190730105 ps
CPU time 6.14 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:33 PM PST 23
Peak memory 242736 kb
Host smart-d7843f92-8d05-4c21-925c-8fce5ba2cf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823784004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3823784004
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.3012052658
Short name T1089
Test name
Test status
Simulation time 2573550655 ps
CPU time 14.93 seconds
Started Dec 24 02:07:10 PM PST 23
Finished Dec 24 02:07:35 PM PST 23
Peak memory 238564 kb
Host smart-8247a252-9a14-4878-92d3-fb47b376e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012052658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3012052658
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.1614508107
Short name T751
Test name
Test status
Simulation time 592277202 ps
CPU time 8.24 seconds
Started Dec 24 02:07:11 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 238616 kb
Host smart-d02e2fb8-89d5-4c03-9fc7-e3abed2f04f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614508107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1614508107
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.380591798
Short name T332
Test name
Test status
Simulation time 1214929319 ps
CPU time 21.15 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:47 PM PST 23
Peak memory 238504 kb
Host smart-438a40d4-e6c7-4095-be93-91bbd9e2da2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380591798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.380591798
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.1155921393
Short name T997
Test name
Test status
Simulation time 403786326 ps
CPU time 4.64 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:31 PM PST 23
Peak memory 238520 kb
Host smart-34d13b08-8083-4629-90f1-f5d41a38c058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155921393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.1155921393
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.2219627771
Short name T567
Test name
Test status
Simulation time 1516550026 ps
CPU time 12.53 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:35 PM PST 23
Peak memory 238448 kb
Host smart-b3ce609e-9453-4ed4-8284-08be8c0d6da4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219627771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.2219627771
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.661933842
Short name T763
Test name
Test status
Simulation time 1712094695 ps
CPU time 5.68 seconds
Started Dec 24 02:07:18 PM PST 23
Finished Dec 24 02:07:35 PM PST 23
Peak memory 238424 kb
Host smart-925113a2-fd85-43ec-83e3-bd54da4bb035
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661933842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.661933842
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1557371909
Short name T861
Test name
Test status
Simulation time 2102157120 ps
CPU time 4.16 seconds
Started Dec 24 02:07:07 PM PST 23
Finished Dec 24 02:07:21 PM PST 23
Peak memory 237716 kb
Host smart-942f8a4f-5c91-4176-94e9-ad93737f9d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557371909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1557371909
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.3792629356
Short name T970
Test name
Test status
Simulation time 2091393820 ps
CPU time 12.1 seconds
Started Dec 24 02:07:19 PM PST 23
Finished Dec 24 02:07:42 PM PST 23
Peak memory 237736 kb
Host smart-f032a38e-e441-4efd-8dd0-2b7de66ff5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792629356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.3792629356
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.4067406604
Short name T437
Test name
Test status
Simulation time 508560883 ps
CPU time 4.81 seconds
Started Dec 24 02:09:25 PM PST 23
Finished Dec 24 02:09:38 PM PST 23
Peak memory 240956 kb
Host smart-73202858-cf62-43c7-9a5c-ba57b0b15a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067406604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.4067406604
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.3522256454
Short name T896
Test name
Test status
Simulation time 233503890 ps
CPU time 3.43 seconds
Started Dec 24 02:09:25 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 240436 kb
Host smart-c1328993-9afb-457b-bd6f-b8764a85a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522256454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3522256454
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.1968166394
Short name T165
Test name
Test status
Simulation time 168035653 ps
CPU time 3.01 seconds
Started Dec 24 02:09:22 PM PST 23
Finished Dec 24 02:09:36 PM PST 23
Peak memory 238432 kb
Host smart-04f9584b-7005-417e-938c-e81617f300a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968166394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.1968166394
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.2587928901
Short name T1231
Test name
Test status
Simulation time 96093128 ps
CPU time 3.81 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 241320 kb
Host smart-d5628528-f013-4140-b928-6bbe17dc9e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587928901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.2587928901
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.1015537462
Short name T1276
Test name
Test status
Simulation time 112924960 ps
CPU time 3.68 seconds
Started Dec 24 02:09:24 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 241152 kb
Host smart-9caa44be-1290-44aa-83e4-6c9bd63cea85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015537462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1015537462
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.217639987
Short name T998
Test name
Test status
Simulation time 304891333 ps
CPU time 4.69 seconds
Started Dec 24 02:09:28 PM PST 23
Finished Dec 24 02:09:40 PM PST 23
Peak memory 238416 kb
Host smart-77024444-3b4f-450b-a40a-35c297a18a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217639987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.217639987
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.2855238775
Short name T68
Test name
Test status
Simulation time 410837467 ps
CPU time 3.99 seconds
Started Dec 24 02:09:23 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 241232 kb
Host smart-19753029-a1f9-4638-86b6-11131196ebd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855238775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2855238775
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.1759359395
Short name T503
Test name
Test status
Simulation time 596377370 ps
CPU time 4.73 seconds
Started Dec 24 02:09:21 PM PST 23
Finished Dec 24 02:09:37 PM PST 23
Peak memory 241324 kb
Host smart-24f2ba5c-7b40-431e-a8cb-386b387377cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759359395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1759359395
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.359278108
Short name T1091
Test name
Test status
Simulation time 318493568 ps
CPU time 2.05 seconds
Started Dec 24 02:06:30 PM PST 23
Finished Dec 24 02:06:36 PM PST 23
Peak memory 239312 kb
Host smart-b2401900-9700-4502-b8bb-c72d0e35d2cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359278108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.359278108
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.3956215186
Short name T572
Test name
Test status
Simulation time 2157252898 ps
CPU time 15.11 seconds
Started Dec 24 02:06:13 PM PST 23
Finished Dec 24 02:06:34 PM PST 23
Peak memory 238788 kb
Host smart-c4d8959a-4947-412e-9add-63040f0f9638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956215186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3956215186
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1905538351
Short name T600
Test name
Test status
Simulation time 198551632 ps
CPU time 4.17 seconds
Started Dec 24 02:06:34 PM PST 23
Finished Dec 24 02:06:41 PM PST 23
Peak memory 238544 kb
Host smart-e8da648a-c0de-4984-a347-df1bc571abe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905538351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1905538351
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.248857819
Short name T605
Test name
Test status
Simulation time 383740890 ps
CPU time 5.09 seconds
Started Dec 24 02:06:15 PM PST 23
Finished Dec 24 02:06:27 PM PST 23
Peak memory 238348 kb
Host smart-3b13709d-1b2c-42f9-858b-abe0a84d773f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248857819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.248857819
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.3035939539
Short name T340
Test name
Test status
Simulation time 1933433343 ps
CPU time 14.85 seconds
Started Dec 24 02:06:21 PM PST 23
Finished Dec 24 02:06:41 PM PST 23
Peak memory 243784 kb
Host smart-1452ec9b-1ab3-45e4-8b58-445cdc02f45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035939539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3035939539
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.2325954732
Short name T1260
Test name
Test status
Simulation time 200631993 ps
CPU time 3.38 seconds
Started Dec 24 02:06:19 PM PST 23
Finished Dec 24 02:06:29 PM PST 23
Peak memory 240628 kb
Host smart-47268cf7-63f5-4e63-bc42-8bd01e21e9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325954732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.2325954732
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.2858820140
Short name T1109
Test name
Test status
Simulation time 846196589 ps
CPU time 7.2 seconds
Started Dec 24 02:06:11 PM PST 23
Finished Dec 24 02:06:25 PM PST 23
Peak memory 238608 kb
Host smart-511dc300-0bf6-4cbe-b825-b7d469efd178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858820140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.2858820140
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.2572352639
Short name T778
Test name
Test status
Simulation time 818687803 ps
CPU time 18.07 seconds
Started Dec 24 02:06:25 PM PST 23
Finished Dec 24 02:06:45 PM PST 23
Peak memory 244228 kb
Host smart-50044660-7f4c-40ff-8916-1ad461c7dbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572352639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2572352639
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.4217570108
Short name T579
Test name
Test status
Simulation time 482938619 ps
CPU time 4.49 seconds
Started Dec 24 02:06:09 PM PST 23
Finished Dec 24 02:06:19 PM PST 23
Peak memory 246768 kb
Host smart-6d005b6e-58b4-4585-b118-aaefe92175aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217570108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.4217570108
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.2187778874
Short name T897
Test name
Test status
Simulation time 686277812 ps
CPU time 17.52 seconds
Started Dec 24 02:06:20 PM PST 23
Finished Dec 24 02:06:43 PM PST 23
Peak memory 238380 kb
Host smart-6e0d1e34-5dc2-48fe-b398-69900728e5f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187778874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2187778874
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3716652397
Short name T1253
Test name
Test status
Simulation time 250941770 ps
CPU time 7.07 seconds
Started Dec 24 02:06:34 PM PST 23
Finished Dec 24 02:06:44 PM PST 23
Peak memory 241740 kb
Host smart-84a99bea-12ea-47e1-a5c0-5fe5ca2d525e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716652397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3716652397
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.1939915363
Short name T209
Test name
Test status
Simulation time 18971805266 ps
CPU time 144.33 seconds
Started Dec 24 02:06:32 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 271280 kb
Host smart-b5a27c53-bee0-4915-9777-2799b3f90587
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939915363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1939915363
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.3831706715
Short name T1140
Test name
Test status
Simulation time 307112674 ps
CPU time 6.44 seconds
Started Dec 24 02:06:09 PM PST 23
Finished Dec 24 02:06:21 PM PST 23
Peak memory 242836 kb
Host smart-6552232f-975e-4ba3-a16c-d79b00dff482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831706715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.3831706715
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.800329823
Short name T964
Test name
Test status
Simulation time 4542316126 ps
CPU time 94.83 seconds
Started Dec 24 02:06:27 PM PST 23
Finished Dec 24 02:08:03 PM PST 23
Peak memory 246756 kb
Host smart-7d7de525-97b2-4457-94a5-e712e19355db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800329823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.800329823
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1731728642
Short name T1283
Test name
Test status
Simulation time 714801013868 ps
CPU time 4976.57 seconds
Started Dec 24 02:06:29 PM PST 23
Finished Dec 24 03:29:28 PM PST 23
Peak memory 360556 kb
Host smart-39644698-75b2-45d3-ad47-0a6a2cb8bd19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731728642 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.1731728642
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.855799064
Short name T150
Test name
Test status
Simulation time 114378691 ps
CPU time 2.29 seconds
Started Dec 24 02:07:11 PM PST 23
Finished Dec 24 02:07:24 PM PST 23
Peak memory 238844 kb
Host smart-c76390c2-dde8-4c1c-a172-58292c0ee1d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855799064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.855799064
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.3429971013
Short name T37
Test name
Test status
Simulation time 888903925 ps
CPU time 7.35 seconds
Started Dec 24 02:07:15 PM PST 23
Finished Dec 24 02:07:34 PM PST 23
Peak memory 240152 kb
Host smart-e5d6a000-8f40-4b65-bfc6-9eefd7af4f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429971013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3429971013
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.334639145
Short name T967
Test name
Test status
Simulation time 596512767 ps
CPU time 6.86 seconds
Started Dec 24 02:07:17 PM PST 23
Finished Dec 24 02:07:35 PM PST 23
Peak memory 242852 kb
Host smart-f7481edd-734e-4452-8e76-2c71e7c80809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334639145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.334639145
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.1697375866
Short name T645
Test name
Test status
Simulation time 10265214646 ps
CPU time 30.35 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:53 PM PST 23
Peak memory 238564 kb
Host smart-389e8fbb-04bb-48a2-8c0c-f64621edae71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697375866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.1697375866
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.1844356247
Short name T979
Test name
Test status
Simulation time 2021208510 ps
CPU time 6.23 seconds
Started Dec 24 02:07:15 PM PST 23
Finished Dec 24 02:07:34 PM PST 23
Peak memory 240764 kb
Host smart-4bbdcb1b-766f-4318-bbc9-2c2e156a7e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844356247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1844356247
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.1606661071
Short name T732
Test name
Test status
Simulation time 842563238 ps
CPU time 13.63 seconds
Started Dec 24 02:07:16 PM PST 23
Finished Dec 24 02:07:42 PM PST 23
Peak memory 246596 kb
Host smart-54db16d0-d991-4e68-9183-523166d26e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606661071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1606661071
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.1883018036
Short name T341
Test name
Test status
Simulation time 10720514415 ps
CPU time 29.75 seconds
Started Dec 24 02:07:19 PM PST 23
Finished Dec 24 02:08:00 PM PST 23
Peak memory 238652 kb
Host smart-87e3725b-485b-40cb-9389-9e7c10222be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883018036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.1883018036
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.4141088702
Short name T851
Test name
Test status
Simulation time 163946609 ps
CPU time 3.17 seconds
Started Dec 24 02:07:17 PM PST 23
Finished Dec 24 02:07:32 PM PST 23
Peak memory 242764 kb
Host smart-fc1f3966-55a6-4726-8b75-ab1827be7d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141088702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.4141088702
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.3093542876
Short name T1103
Test name
Test status
Simulation time 9934169300 ps
CPU time 23.43 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:48 PM PST 23
Peak memory 238660 kb
Host smart-e12b6a36-9aff-49b9-9a5e-a7c284385751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093542876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3093542876
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.3774626316
Short name T929
Test name
Test status
Simulation time 1413323898 ps
CPU time 3.91 seconds
Started Dec 24 02:07:19 PM PST 23
Finished Dec 24 02:07:34 PM PST 23
Peak memory 241000 kb
Host smart-e0959d5e-c920-4624-bfbe-e358f8fa24ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774626316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.3774626316
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.4177441814
Short name T1005
Test name
Test status
Simulation time 112051448 ps
CPU time 3.53 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 246536 kb
Host smart-c24df4fb-4b93-40a2-b776-1751c227dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177441814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.4177441814
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.1848924094
Short name T171
Test name
Test status
Simulation time 13231250018 ps
CPU time 123.88 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:09:30 PM PST 23
Peak memory 246524 kb
Host smart-9a7f6b80-6762-42b2-be34-d2274e99633a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848924094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.1848924094
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.1644410878
Short name T1209
Test name
Test status
Simulation time 12283888300 ps
CPU time 19.54 seconds
Started Dec 24 02:07:13 PM PST 23
Finished Dec 24 02:07:44 PM PST 23
Peak memory 244980 kb
Host smart-bc001181-66e7-468f-bd44-ec9476e23d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644410878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.1644410878
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.934399295
Short name T627
Test name
Test status
Simulation time 68004581 ps
CPU time 1.67 seconds
Started Dec 24 02:07:18 PM PST 23
Finished Dec 24 02:07:31 PM PST 23
Peak memory 238272 kb
Host smart-79daf6c1-3a64-488b-8aa4-354e943b1517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934399295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.934399295
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.1086602363
Short name T1132
Test name
Test status
Simulation time 823344089 ps
CPU time 9.18 seconds
Started Dec 24 02:07:30 PM PST 23
Finished Dec 24 02:07:46 PM PST 23
Peak memory 238412 kb
Host smart-f0445346-0a9b-484e-88d4-c0b4dddd050d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086602363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1086602363
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.4178955918
Short name T501
Test name
Test status
Simulation time 4022284812 ps
CPU time 6.39 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:33 PM PST 23
Peak memory 238632 kb
Host smart-d57fd569-fd0c-4dec-98b2-a4c536c2bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178955918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.4178955918
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.1833532147
Short name T538
Test name
Test status
Simulation time 382144692 ps
CPU time 3.41 seconds
Started Dec 24 02:07:10 PM PST 23
Finished Dec 24 02:07:23 PM PST 23
Peak memory 246648 kb
Host smart-2ff606e2-5ca9-4caa-9358-8ab5147cdc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833532147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.1833532147
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.4272713545
Short name T1069
Test name
Test status
Simulation time 2724749883 ps
CPU time 5.69 seconds
Started Dec 24 02:07:29 PM PST 23
Finished Dec 24 02:07:42 PM PST 23
Peak memory 246136 kb
Host smart-a7602af3-7f64-42c1-9989-6a72229ef5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272713545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.4272713545
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.1986727179
Short name T940
Test name
Test status
Simulation time 1586380930 ps
CPU time 15.76 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:42 PM PST 23
Peak memory 238548 kb
Host smart-9e1c2d16-4227-4e08-85be-bf9a1272d07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986727179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1986727179
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.1040408569
Short name T446
Test name
Test status
Simulation time 686952196 ps
CPU time 5.33 seconds
Started Dec 24 02:07:11 PM PST 23
Finished Dec 24 02:07:27 PM PST 23
Peak memory 242304 kb
Host smart-beefddee-42bb-40b2-8ab8-4cd1c75c1648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040408569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1040408569
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.3126987124
Short name T599
Test name
Test status
Simulation time 618364714 ps
CPU time 9.45 seconds
Started Dec 24 02:07:26 PM PST 23
Finished Dec 24 02:07:45 PM PST 23
Peak memory 242984 kb
Host smart-e7620aa9-fa75-45e5-8063-1dac653674bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126987124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.3126987124
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.2426706563
Short name T1051
Test name
Test status
Simulation time 370457226 ps
CPU time 6.09 seconds
Started Dec 24 02:07:25 PM PST 23
Finished Dec 24 02:07:41 PM PST 23
Peak memory 237264 kb
Host smart-e819a8f3-bef0-4b2e-bf2e-ad35916bffc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2426706563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2426706563
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.4183135649
Short name T881
Test name
Test status
Simulation time 161182854 ps
CPU time 4.07 seconds
Started Dec 24 02:07:10 PM PST 23
Finished Dec 24 02:07:24 PM PST 23
Peak memory 240548 kb
Host smart-626f735d-2aef-4bab-9c38-eb1408e4335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183135649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.4183135649
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.1437509679
Short name T1152
Test name
Test status
Simulation time 37855736183 ps
CPU time 88.37 seconds
Started Dec 24 02:07:15 PM PST 23
Finished Dec 24 02:08:56 PM PST 23
Peak memory 242348 kb
Host smart-42c74912-3a56-4b16-9753-019e42359377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437509679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.1437509679
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.1216063082
Short name T713
Test name
Test status
Simulation time 1330571231 ps
CPU time 10.29 seconds
Started Dec 24 02:07:24 PM PST 23
Finished Dec 24 02:07:45 PM PST 23
Peak memory 238576 kb
Host smart-dec65875-4694-4e59-bbc3-93b5164cb5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216063082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1216063082
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.1024426485
Short name T971
Test name
Test status
Simulation time 738708435 ps
CPU time 1.91 seconds
Started Dec 24 02:07:40 PM PST 23
Finished Dec 24 02:07:43 PM PST 23
Peak memory 239240 kb
Host smart-c7ed535c-03fb-4ccb-9e8b-fa5f229e720f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024426485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1024426485
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.1124431530
Short name T62
Test name
Test status
Simulation time 452317031 ps
CPU time 7.65 seconds
Started Dec 24 02:07:41 PM PST 23
Finished Dec 24 02:07:50 PM PST 23
Peak memory 244804 kb
Host smart-750d46ac-0e8e-49ec-aa6b-c80366940960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124431530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1124431530
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.1521440394
Short name T489
Test name
Test status
Simulation time 390529407 ps
CPU time 8.32 seconds
Started Dec 24 02:07:29 PM PST 23
Finished Dec 24 02:07:45 PM PST 23
Peak memory 244472 kb
Host smart-494709f6-7bfe-4989-94cb-90f138d267f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521440394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1521440394
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.1807618997
Short name T478
Test name
Test status
Simulation time 220694495 ps
CPU time 7.2 seconds
Started Dec 24 02:07:27 PM PST 23
Finished Dec 24 02:07:43 PM PST 23
Peak memory 238576 kb
Host smart-5e32dbd1-3103-41d7-811a-ec6896f15a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807618997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.1807618997
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.1535795828
Short name T132
Test name
Test status
Simulation time 236676907 ps
CPU time 3.61 seconds
Started Dec 24 02:07:29 PM PST 23
Finished Dec 24 02:07:40 PM PST 23
Peak memory 238476 kb
Host smart-6b2fc924-15da-4d89-aa2c-453c87f062b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535795828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1535795828
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.3911159423
Short name T528
Test name
Test status
Simulation time 168912296 ps
CPU time 3.51 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:48 PM PST 23
Peak memory 238544 kb
Host smart-3b30a003-09df-4254-a0c8-dca10de631f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911159423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3911159423
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.1759097339
Short name T689
Test name
Test status
Simulation time 138023778 ps
CPU time 3.2 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 02:07:30 PM PST 23
Peak memory 246544 kb
Host smart-6aa789e3-bc29-4cbc-a2fa-37f14ab1c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759097339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1759097339
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.399656
Short name T101
Test name
Test status
Simulation time 457915838 ps
CPU time 10.74 seconds
Started Dec 24 02:07:17 PM PST 23
Finished Dec 24 02:07:40 PM PST 23
Peak memory 242640 kb
Host smart-691dfc8a-817b-4cd5-b3ce-faa66c4adc33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.399656
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.3433447395
Short name T984
Test name
Test status
Simulation time 231901148 ps
CPU time 6.38 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:50 PM PST 23
Peak memory 238576 kb
Host smart-947504fb-bbe4-478d-b977-1f2722804054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3433447395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.3433447395
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.3078593211
Short name T1061
Test name
Test status
Simulation time 463117459 ps
CPU time 8.27 seconds
Started Dec 24 02:07:12 PM PST 23
Finished Dec 24 02:07:31 PM PST 23
Peak memory 238548 kb
Host smart-91cc769e-796e-46bc-864a-55087d103840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078593211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3078593211
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.1838703708
Short name T612
Test name
Test status
Simulation time 704396500 ps
CPU time 6.96 seconds
Started Dec 24 02:07:55 PM PST 23
Finished Dec 24 02:08:15 PM PST 23
Peak memory 242932 kb
Host smart-f20c98fb-9b1b-45a3-9965-b6e5bdc3cdad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838703708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.1838703708
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.1199948239
Short name T654
Test name
Test status
Simulation time 144744422894 ps
CPU time 1738.57 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:36:43 PM PST 23
Peak memory 259000 kb
Host smart-4889db76-a200-4459-a167-b42ae05e1fc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199948239 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.1199948239
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.1935197118
Short name T454
Test name
Test status
Simulation time 740467080 ps
CPU time 5.85 seconds
Started Dec 24 02:07:53 PM PST 23
Finished Dec 24 02:08:01 PM PST 23
Peak memory 238544 kb
Host smart-1c65e0ee-7d31-4c7b-980c-8aed06540fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935197118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1935197118
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.3562319451
Short name T792
Test name
Test status
Simulation time 592824962 ps
CPU time 2.07 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:25 PM PST 23
Peak memory 238332 kb
Host smart-638577a2-0229-4f17-8a4e-2ce064848cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562319451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3562319451
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.927293925
Short name T963
Test name
Test status
Simulation time 6628432084 ps
CPU time 14.71 seconds
Started Dec 24 02:07:57 PM PST 23
Finished Dec 24 02:08:24 PM PST 23
Peak memory 239052 kb
Host smart-a9ebd626-01e4-4c45-998c-2746c1b66677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927293925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.927293925
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.3066951143
Short name T877
Test name
Test status
Simulation time 217335671 ps
CPU time 9.24 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 246692 kb
Host smart-49edf618-8fb5-480f-b345-17f407f00032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066951143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3066951143
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.2570017732
Short name T653
Test name
Test status
Simulation time 586969756 ps
CPU time 10.53 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:08:21 PM PST 23
Peak memory 238524 kb
Host smart-f0baae21-2195-4bd5-b13d-8babadc32d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570017732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.2570017732
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.2594199820
Short name T795
Test name
Test status
Simulation time 259214432 ps
CPU time 4.87 seconds
Started Dec 24 02:08:09 PM PST 23
Finished Dec 24 02:08:25 PM PST 23
Peak memory 238396 kb
Host smart-4e5c23e2-b4c5-4aca-ae05-c2aa54c5ced9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594199820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2594199820
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.2911007541
Short name T288
Test name
Test status
Simulation time 1369747663 ps
CPU time 21.41 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 241912 kb
Host smart-cdab8806-835e-4802-aa32-8af5caf756d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911007541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2911007541
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.1133324301
Short name T742
Test name
Test status
Simulation time 519438148 ps
CPU time 5 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 238520 kb
Host smart-e14f6b79-604c-43f5-a020-433ee1fba409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133324301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.1133324301
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.357193843
Short name T1172
Test name
Test status
Simulation time 398456575 ps
CPU time 4.47 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 238528 kb
Host smart-c345317e-b14e-44e3-8754-2e4baed0f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357193843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.357193843
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1364293991
Short name T873
Test name
Test status
Simulation time 1167143459 ps
CPU time 11.1 seconds
Started Dec 24 02:07:40 PM PST 23
Finished Dec 24 02:07:52 PM PST 23
Peak memory 238420 kb
Host smart-6047f2ee-df66-4b70-b3ce-86d978c21149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364293991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1364293991
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.706698800
Short name T932
Test name
Test status
Simulation time 208446780 ps
CPU time 2.72 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:28 PM PST 23
Peak memory 237216 kb
Host smart-59e652c7-f682-41f3-8180-f3b7b2342b70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706698800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.706698800
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.3100333525
Short name T529
Test name
Test status
Simulation time 470523741 ps
CPU time 3.78 seconds
Started Dec 24 02:07:54 PM PST 23
Finished Dec 24 02:08:02 PM PST 23
Peak memory 238576 kb
Host smart-2abb97cf-7ef9-49c7-bd44-3b0c1c459f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100333525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.3100333525
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.3104820517
Short name T1265
Test name
Test status
Simulation time 3894811404 ps
CPU time 85.2 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:09:50 PM PST 23
Peak memory 240632 kb
Host smart-c96a3bfc-6300-4649-a61e-aec0bf05a376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104820517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.3104820517
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.2124777664
Short name T924
Test name
Test status
Simulation time 2504574833 ps
CPU time 5.92 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 241556 kb
Host smart-20103a2d-3e77-44f2-b191-2bed71968b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124777664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2124777664
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.1730248105
Short name T915
Test name
Test status
Simulation time 778460849 ps
CPU time 2.21 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:25 PM PST 23
Peak memory 238548 kb
Host smart-671c3dc4-a362-4136-ab7c-f63d9a8f2d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730248105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.1730248105
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3105833523
Short name T755
Test name
Test status
Simulation time 1487355495 ps
CPU time 5.99 seconds
Started Dec 24 02:08:46 PM PST 23
Finished Dec 24 02:09:06 PM PST 23
Peak memory 243456 kb
Host smart-35503a51-3a4f-4f41-8d7e-fb8e44045b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105833523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3105833523
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.2707197973
Short name T127
Test name
Test status
Simulation time 374199714 ps
CPU time 5.76 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:36 PM PST 23
Peak memory 238516 kb
Host smart-7569e713-def2-48d8-bfcb-de032c8d5707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707197973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2707197973
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.1146925238
Short name T898
Test name
Test status
Simulation time 265586562 ps
CPU time 6 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 245236 kb
Host smart-2af2f5f5-405b-4b8a-8bc0-4445a6d23974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146925238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1146925238
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.1868408058
Short name T428
Test name
Test status
Simulation time 2459187825 ps
CPU time 5.8 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 241584 kb
Host smart-84840b07-fe02-497d-9abf-5c1107f48180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868408058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1868408058
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.3450380052
Short name T706
Test name
Test status
Simulation time 573086561 ps
CPU time 7.19 seconds
Started Dec 24 02:07:38 PM PST 23
Finished Dec 24 02:07:46 PM PST 23
Peak memory 238568 kb
Host smart-4f31e25d-513c-481c-9d82-ac1419499520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450380052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3450380052
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.1447700611
Short name T99
Test name
Test status
Simulation time 928080351 ps
CPU time 14.74 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 244116 kb
Host smart-e5555ffe-c889-4f29-9a5c-1fb811a17ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447700611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1447700611
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.360205698
Short name T1058
Test name
Test status
Simulation time 298504295 ps
CPU time 5.33 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 238412 kb
Host smart-0fb41741-f339-4892-860d-7c61a6545bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360205698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.360205698
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.2608474609
Short name T585
Test name
Test status
Simulation time 6204277898 ps
CPU time 19.66 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:50 PM PST 23
Peak memory 244040 kb
Host smart-91ba2239-6477-4684-aa5b-4106699cdfc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608474609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2608474609
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.869452456
Short name T987
Test name
Test status
Simulation time 514192946 ps
CPU time 7.95 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:39 PM PST 23
Peak memory 238552 kb
Host smart-9e5d257c-711c-4f96-bb21-ad5172206eae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869452456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.869452456
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.598302897
Short name T1108
Test name
Test status
Simulation time 636527933 ps
CPU time 4.81 seconds
Started Dec 24 02:08:20 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 238524 kb
Host smart-892dd5ae-6a7b-450f-96a5-e86a38ad64cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598302897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.598302897
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.86278043
Short name T737
Test name
Test status
Simulation time 246897669 ps
CPU time 1.93 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:46 PM PST 23
Peak memory 228480 kb
Host smart-e66f0883-71a6-4ebf-ba60-2708868b7488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86278043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.86278043
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.3816881158
Short name T1121
Test name
Test status
Simulation time 620225328059 ps
CPU time 3596.38 seconds
Started Dec 24 02:07:14 PM PST 23
Finished Dec 24 03:07:23 PM PST 23
Peak memory 259132 kb
Host smart-75158df2-9e58-46f6-a575-d53bbb0b67a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816881158 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.3816881158
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.1107740674
Short name T476
Test name
Test status
Simulation time 8718542995 ps
CPU time 21.95 seconds
Started Dec 24 02:07:28 PM PST 23
Finished Dec 24 02:07:58 PM PST 23
Peak memory 246836 kb
Host smart-5dd88ee6-178a-4e81-9edc-75da8fac959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107740674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.1107740674
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.1600963600
Short name T539
Test name
Test status
Simulation time 64357047 ps
CPU time 1.7 seconds
Started Dec 24 02:07:53 PM PST 23
Finished Dec 24 02:07:57 PM PST 23
Peak memory 239400 kb
Host smart-fbf70b28-8268-4141-84fd-c421f78373b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600963600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.1600963600
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.4037326616
Short name T561
Test name
Test status
Simulation time 3834891270 ps
CPU time 6.93 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:08:18 PM PST 23
Peak memory 238712 kb
Host smart-ec2ddab2-b11f-4db5-8bfb-3d164b2da7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037326616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.4037326616
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.3432134078
Short name T827
Test name
Test status
Simulation time 1846233246 ps
CPU time 5.73 seconds
Started Dec 24 02:08:03 PM PST 23
Finished Dec 24 02:08:17 PM PST 23
Peak memory 242652 kb
Host smart-398a58c8-3339-4af2-b4a7-36f1cc3ade1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432134078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.3432134078
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.232490547
Short name T1000
Test name
Test status
Simulation time 702751352 ps
CPU time 5.2 seconds
Started Dec 24 02:07:59 PM PST 23
Finished Dec 24 02:08:15 PM PST 23
Peak memory 244180 kb
Host smart-de1a396c-a43c-4602-8c76-83e62cc09e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232490547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.232490547
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.2535609264
Short name T958
Test name
Test status
Simulation time 452447192 ps
CPU time 3.42 seconds
Started Dec 24 02:07:43 PM PST 23
Finished Dec 24 02:07:48 PM PST 23
Peak memory 240908 kb
Host smart-5a97a719-1943-423c-bd1b-c00f82eb88ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535609264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2535609264
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.1770735205
Short name T886
Test name
Test status
Simulation time 761267702 ps
CPU time 4.89 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 238620 kb
Host smart-f8cc34b9-ad9c-4f0c-9207-65ac2ea2334c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770735205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.1770735205
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.3559213686
Short name T759
Test name
Test status
Simulation time 6904693336 ps
CPU time 16.01 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:38 PM PST 23
Peak memory 238564 kb
Host smart-5342a9c5-d03a-476c-a867-5f535da87d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559213686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.3559213686
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.2802149725
Short name T835
Test name
Test status
Simulation time 311267574 ps
CPU time 7.37 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 243028 kb
Host smart-b00fdfef-6135-4d9d-ba9f-5920add893f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802149725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.2802149725
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.972331624
Short name T1142
Test name
Test status
Simulation time 1293633261 ps
CPU time 19.93 seconds
Started Dec 24 02:07:54 PM PST 23
Finished Dec 24 02:08:24 PM PST 23
Peak memory 238532 kb
Host smart-1718af7c-4b15-4ae7-9ba8-7b9e6b2d079c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972331624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.972331624
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.3369759869
Short name T41
Test name
Test status
Simulation time 760042918 ps
CPU time 8.27 seconds
Started Dec 24 02:08:10 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 238568 kb
Host smart-35a079d1-5658-427e-88f8-6152cbb0e8af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369759869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3369759869
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.3081620447
Short name T278
Test name
Test status
Simulation time 158138597 ps
CPU time 3.64 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:26 PM PST 23
Peak memory 240556 kb
Host smart-584c9a68-6b2f-4f61-bbf4-6a2679c70320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081620447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3081620447
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.264032021
Short name T1261
Test name
Test status
Simulation time 1424740687 ps
CPU time 32.39 seconds
Started Dec 24 02:07:41 PM PST 23
Finished Dec 24 02:08:15 PM PST 23
Peak memory 245668 kb
Host smart-bfcc470b-6edd-4d6c-a932-fdd99659a8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264032021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.
264032021
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.3219547217
Short name T922
Test name
Test status
Simulation time 137161673 ps
CPU time 3.75 seconds
Started Dec 24 02:07:44 PM PST 23
Finished Dec 24 02:07:50 PM PST 23
Peak memory 237652 kb
Host smart-b2ec89ed-1918-4f8e-8f2f-f28717427a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219547217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3219547217
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.2584883461
Short name T821
Test name
Test status
Simulation time 754312426 ps
CPU time 1.89 seconds
Started Dec 24 02:07:43 PM PST 23
Finished Dec 24 02:07:47 PM PST 23
Peak memory 238212 kb
Host smart-c2fe9313-ab4a-49f1-b130-b09a7ed742b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584883461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2584883461
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.3454962677
Short name T685
Test name
Test status
Simulation time 507802601 ps
CPU time 5.39 seconds
Started Dec 24 02:07:44 PM PST 23
Finished Dec 24 02:07:51 PM PST 23
Peak memory 243068 kb
Host smart-5898a64e-43bf-4011-88ca-44499429d16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454962677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3454962677
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.830975980
Short name T560
Test name
Test status
Simulation time 2785189750 ps
CPU time 20.49 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 244092 kb
Host smart-3c17ea65-0b57-4df8-8394-f87acd3cd116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830975980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.830975980
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.2236241084
Short name T772
Test name
Test status
Simulation time 321923101 ps
CPU time 4.05 seconds
Started Dec 24 02:08:09 PM PST 23
Finished Dec 24 02:08:26 PM PST 23
Peak memory 241264 kb
Host smart-4c79a9c3-9cf1-4ba4-b7b5-06e9a4bc3b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236241084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.2236241084
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.1222424163
Short name T583
Test name
Test status
Simulation time 164501151 ps
CPU time 3.87 seconds
Started Dec 24 02:08:09 PM PST 23
Finished Dec 24 02:08:25 PM PST 23
Peak memory 238580 kb
Host smart-1b319d35-35ba-4cec-976b-95b9eb02afa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222424163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1222424163
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1656084825
Short name T95
Test name
Test status
Simulation time 7387215661 ps
CPU time 20.85 seconds
Started Dec 24 02:07:43 PM PST 23
Finished Dec 24 02:08:05 PM PST 23
Peak memory 238660 kb
Host smart-e4cadb29-cbfb-4f73-8aca-71c946843c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656084825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1656084825
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.1725967979
Short name T899
Test name
Test status
Simulation time 127536411 ps
CPU time 3.33 seconds
Started Dec 24 02:07:54 PM PST 23
Finished Dec 24 02:08:07 PM PST 23
Peak memory 238412 kb
Host smart-1a3a8ee1-a60f-4f45-8203-b22364c2843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725967979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1725967979
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.2515342358
Short name T470
Test name
Test status
Simulation time 246277538 ps
CPU time 7.28 seconds
Started Dec 24 02:07:53 PM PST 23
Finished Dec 24 02:08:03 PM PST 23
Peak memory 238480 kb
Host smart-e04bb23a-ba9a-4f3e-96c3-fe96d0552dcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515342358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2515342358
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.2493890718
Short name T214
Test name
Test status
Simulation time 3635737261 ps
CPU time 8.61 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:53 PM PST 23
Peak memory 238656 kb
Host smart-eab59314-0bf9-4e4d-92da-0ba9d01b3db8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493890718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.2493890718
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3347238287
Short name T951
Test name
Test status
Simulation time 241837899 ps
CPU time 4.79 seconds
Started Dec 24 02:07:53 PM PST 23
Finished Dec 24 02:08:00 PM PST 23
Peak memory 238508 kb
Host smart-27084837-4791-4270-b8a3-ce026fbfa5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347238287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3347238287
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.203294005
Short name T495
Test name
Test status
Simulation time 21732406739 ps
CPU time 143.67 seconds
Started Dec 24 02:07:37 PM PST 23
Finished Dec 24 02:10:01 PM PST 23
Peak memory 242324 kb
Host smart-68978cda-6759-4373-a1ac-2a63cc1eb203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203294005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.
203294005
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.163793687
Short name T532
Test name
Test status
Simulation time 5599821187891 ps
CPU time 7753.73 seconds
Started Dec 24 02:08:09 PM PST 23
Finished Dec 24 04:17:35 PM PST 23
Peak memory 1390232 kb
Host smart-b0c864bb-15d9-40fa-b0eb-29995ad21bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163793687 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.163793687
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.2132353720
Short name T1138
Test name
Test status
Simulation time 2605955020 ps
CPU time 14.87 seconds
Started Dec 24 02:08:10 PM PST 23
Finished Dec 24 02:08:37 PM PST 23
Peak memory 245416 kb
Host smart-14a6b861-f16d-4dd2-9e48-aa5b85dc4e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132353720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2132353720
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.207943398
Short name T1186
Test name
Test status
Simulation time 788274469 ps
CPU time 2.24 seconds
Started Dec 24 02:07:58 PM PST 23
Finished Dec 24 02:08:12 PM PST 23
Peak memory 239224 kb
Host smart-25869a6d-009c-46e9-9285-48de8be1877f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207943398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.207943398
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.3482973637
Short name T223
Test name
Test status
Simulation time 185657618 ps
CPU time 3.03 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 02:08:27 PM PST 23
Peak memory 240868 kb
Host smart-76dbb592-a52a-4d46-a195-84098223de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482973637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3482973637
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.1689062400
Short name T1278
Test name
Test status
Simulation time 634114579 ps
CPU time 8.11 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 238432 kb
Host smart-f4b38543-756d-4b28-91b8-55894d153d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689062400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.1689062400
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.3856454950
Short name T836
Test name
Test status
Simulation time 115030781 ps
CPU time 3.16 seconds
Started Dec 24 02:07:51 PM PST 23
Finished Dec 24 02:07:58 PM PST 23
Peak memory 237548 kb
Host smart-b251fb91-45f1-4e65-a86f-d04f4c78ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856454950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.3856454950
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.845484508
Short name T788
Test name
Test status
Simulation time 2401996824 ps
CPU time 6.27 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:50 PM PST 23
Peak memory 238588 kb
Host smart-cdbc0d21-bf1a-4cf9-a13b-dafef3ef931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845484508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.845484508
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.1819965281
Short name T1030
Test name
Test status
Simulation time 1535071635 ps
CPU time 19.1 seconds
Started Dec 24 02:07:44 PM PST 23
Finished Dec 24 02:08:05 PM PST 23
Peak memory 238608 kb
Host smart-331ebb52-c6cc-4af9-a594-67324b5e188c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819965281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.1819965281
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.2156615012
Short name T957
Test name
Test status
Simulation time 1733669267 ps
CPU time 19.23 seconds
Started Dec 24 02:07:45 PM PST 23
Finished Dec 24 02:08:05 PM PST 23
Peak memory 238540 kb
Host smart-7cb56def-3eb0-4c64-82ab-9460afa728f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156615012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.2156615012
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.3258508198
Short name T1199
Test name
Test status
Simulation time 250138440 ps
CPU time 5.22 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:28 PM PST 23
Peak memory 238612 kb
Host smart-bf04775b-f342-492d-8470-0df7b2576f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258508198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.3258508198
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.3827605370
Short name T1208
Test name
Test status
Simulation time 373074057 ps
CPU time 8.7 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:53 PM PST 23
Peak memory 238388 kb
Host smart-8b2ab0a9-5427-4a9f-8895-49e421a2c204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827605370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.3827605370
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.2850495188
Short name T318
Test name
Test status
Simulation time 350871802 ps
CPU time 5.55 seconds
Started Dec 24 02:08:10 PM PST 23
Finished Dec 24 02:08:28 PM PST 23
Peak memory 238516 kb
Host smart-e62dbcf4-91d6-433c-a331-bb0e37913c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850495188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.2850495188
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.1798248340
Short name T417
Test name
Test status
Simulation time 265523991 ps
CPU time 5.2 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:28 PM PST 23
Peak memory 243088 kb
Host smart-5462152e-bbfb-4cb6-9a3c-4862aaa2a226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798248340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.1798248340
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.2823553423
Short name T804
Test name
Test status
Simulation time 16855791822 ps
CPU time 114.02 seconds
Started Dec 24 02:07:56 PM PST 23
Finished Dec 24 02:10:03 PM PST 23
Peak memory 246904 kb
Host smart-96b33041-452f-4732-ace6-8c4803ca861b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823553423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.2823553423
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.2356338164
Short name T194
Test name
Test status
Simulation time 431197030895 ps
CPU time 2672.2 seconds
Started Dec 24 02:07:40 PM PST 23
Finished Dec 24 02:52:14 PM PST 23
Peak memory 255204 kb
Host smart-5975cbe2-247e-4296-b28e-29c12c5aaed1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356338164 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.2356338164
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3723207400
Short name T1100
Test name
Test status
Simulation time 1015923314 ps
CPU time 6.23 seconds
Started Dec 24 02:07:58 PM PST 23
Finished Dec 24 02:08:16 PM PST 23
Peak memory 237688 kb
Host smart-1d0eb0f9-c175-46c3-ba51-4ecc61c9fd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723207400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3723207400
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.3030883883
Short name T831
Test name
Test status
Simulation time 147462603 ps
CPU time 1.64 seconds
Started Dec 24 02:08:01 PM PST 23
Finished Dec 24 02:08:12 PM PST 23
Peak memory 238488 kb
Host smart-e21ce5bb-9afd-47d9-9085-216848138f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030883883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3030883883
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.1394208173
Short name T609
Test name
Test status
Simulation time 301489567 ps
CPU time 5.5 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:49 PM PST 23
Peak memory 238456 kb
Host smart-32acba73-7937-4e95-9b40-4694b66c5a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394208173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.1394208173
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.912067675
Short name T1156
Test name
Test status
Simulation time 1127602394 ps
CPU time 8.27 seconds
Started Dec 24 02:07:59 PM PST 23
Finished Dec 24 02:08:18 PM PST 23
Peak memory 238504 kb
Host smart-d41e352a-2042-4d1c-b3d8-bf83bc775113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912067675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.912067675
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.2915051793
Short name T905
Test name
Test status
Simulation time 339700032 ps
CPU time 3.64 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:27 PM PST 23
Peak memory 240476 kb
Host smart-f5673769-c569-4649-b514-c3f393ef0463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915051793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.2915051793
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.3986021976
Short name T286
Test name
Test status
Simulation time 2589950655 ps
CPU time 18.35 seconds
Started Dec 24 02:07:40 PM PST 23
Finished Dec 24 02:07:59 PM PST 23
Peak memory 238784 kb
Host smart-c27d2b4b-2e02-4bb9-a6ee-44875b80d222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986021976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3986021976
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.1067366136
Short name T35
Test name
Test status
Simulation time 727305429 ps
CPU time 5.25 seconds
Started Dec 24 02:08:02 PM PST 23
Finished Dec 24 02:08:16 PM PST 23
Peak memory 246616 kb
Host smart-10f2aadf-66d6-4292-93aa-4aaebd05399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067366136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1067366136
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.3399126052
Short name T448
Test name
Test status
Simulation time 2024394980 ps
CPU time 5.55 seconds
Started Dec 24 02:07:54 PM PST 23
Finished Dec 24 02:08:11 PM PST 23
Peak memory 242764 kb
Host smart-8fcadd85-0e76-41c5-a751-ef45afca7fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399126052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3399126052
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.3814602665
Short name T442
Test name
Test status
Simulation time 910539070 ps
CPU time 18.48 seconds
Started Dec 24 02:08:09 PM PST 23
Finished Dec 24 02:08:40 PM PST 23
Peak memory 243064 kb
Host smart-5d048a64-d3d0-44f6-96a2-bca389cd73ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814602665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3814602665
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3583181681
Short name T322
Test name
Test status
Simulation time 124416052 ps
CPU time 3.99 seconds
Started Dec 24 02:07:55 PM PST 23
Finished Dec 24 02:08:10 PM PST 23
Peak memory 238492 kb
Host smart-d6af0007-41b3-4f2d-acf6-e31b295e2eea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583181681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3583181681
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1934160875
Short name T962
Test name
Test status
Simulation time 497492857 ps
CPU time 6.23 seconds
Started Dec 24 02:07:56 PM PST 23
Finished Dec 24 02:08:15 PM PST 23
Peak memory 238364 kb
Host smart-6116687f-98ed-490f-a8e7-9257823be900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934160875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1934160875
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.1882995567
Short name T733
Test name
Test status
Simulation time 1748576354536 ps
CPU time 10728.1 seconds
Started Dec 24 02:07:43 PM PST 23
Finished Dec 24 05:06:34 PM PST 23
Peak memory 1730564 kb
Host smart-62a68f85-8a6f-4c91-a6bb-b06b82f54671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882995567 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.1882995567
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3991018004
Short name T1112
Test name
Test status
Simulation time 11054435681 ps
CPU time 20.95 seconds
Started Dec 24 02:07:55 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 245896 kb
Host smart-b4e942d7-9fe2-4eba-8afa-813117adae2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991018004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3991018004
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.635963075
Short name T937
Test name
Test status
Simulation time 103450015 ps
CPU time 1.67 seconds
Started Dec 24 02:07:43 PM PST 23
Finished Dec 24 02:07:47 PM PST 23
Peak memory 239324 kb
Host smart-799a4886-817c-49a2-bfbf-7a1a1e59921b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635963075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.635963075
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.197661001
Short name T760
Test name
Test status
Simulation time 178339160 ps
CPU time 3.64 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 241744 kb
Host smart-34249771-a2a7-4a57-8084-0d3cb5f29104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197661001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.197661001
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3212979947
Short name T1198
Test name
Test status
Simulation time 2166102878 ps
CPU time 7.26 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:51 PM PST 23
Peak memory 243548 kb
Host smart-105fc4cf-2d64-4069-ab0c-cd91820d2f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212979947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3212979947
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.383068312
Short name T807
Test name
Test status
Simulation time 6917427866 ps
CPU time 8.67 seconds
Started Dec 24 02:07:46 PM PST 23
Finished Dec 24 02:07:56 PM PST 23
Peak memory 245192 kb
Host smart-9ab587f7-dbdb-4f28-b8b3-7a9b20cbf4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383068312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.383068312
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.2917528294
Short name T486
Test name
Test status
Simulation time 302497782 ps
CPU time 3.6 seconds
Started Dec 24 02:08:08 PM PST 23
Finished Dec 24 02:08:24 PM PST 23
Peak memory 240972 kb
Host smart-5fefa36a-2d94-4956-8d4b-b10db717ed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917528294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2917528294
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.2583542741
Short name T981
Test name
Test status
Simulation time 11543766140 ps
CPU time 27.83 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 238768 kb
Host smart-88de39d3-b102-4f95-8b27-0225e2d83a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583542741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2583542741
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.778128300
Short name T1244
Test name
Test status
Simulation time 3900407821 ps
CPU time 9.7 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:32 PM PST 23
Peak memory 238572 kb
Host smart-95084780-820e-42d6-a4fa-94d11f57e109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778128300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.778128300
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3613273885
Short name T1169
Test name
Test status
Simulation time 360693001 ps
CPU time 4.3 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:27 PM PST 23
Peak memory 238680 kb
Host smart-d0af052c-b66e-4a5d-921a-69d0c23af3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613273885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3613273885
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.73332478
Short name T1217
Test name
Test status
Simulation time 734363381 ps
CPU time 17.83 seconds
Started Dec 24 02:07:54 PM PST 23
Finished Dec 24 02:08:22 PM PST 23
Peak memory 238496 kb
Host smart-45209099-05dd-400d-98fc-b7c1cbf65ace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73332478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.73332478
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.4115820564
Short name T1015
Test name
Test status
Simulation time 3305947950 ps
CPU time 7.88 seconds
Started Dec 24 02:08:10 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 238616 kb
Host smart-b4452557-80cc-48aa-9820-6954adf1e669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115820564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.4115820564
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.2840170052
Short name T978
Test name
Test status
Simulation time 555066499 ps
CPU time 6.78 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 238352 kb
Host smart-03b4caa6-fce8-45e9-9e82-b1fb905c375a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840170052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2840170052
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.709068857
Short name T14
Test name
Test status
Simulation time 16746114456 ps
CPU time 393.09 seconds
Started Dec 24 02:07:54 PM PST 23
Finished Dec 24 02:14:37 PM PST 23
Peak memory 301900 kb
Host smart-7143dd62-f776-4c28-88b9-ba1cc94b09d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709068857 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.709068857
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.159579084
Short name T825
Test name
Test status
Simulation time 424516550 ps
CPU time 7.23 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:32 PM PST 23
Peak memory 243624 kb
Host smart-c71e4ff6-d7f2-48f2-83ff-9acdd517422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159579084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.159579084
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.1379514013
Short name T857
Test name
Test status
Simulation time 156591051 ps
CPU time 1.76 seconds
Started Dec 24 02:06:25 PM PST 23
Finished Dec 24 02:06:29 PM PST 23
Peak memory 238340 kb
Host smart-8b0750ee-525f-41d8-a0f6-5fd515a2841d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379514013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.1379514013
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.1778429925
Short name T799
Test name
Test status
Simulation time 4791774860 ps
CPU time 27.47 seconds
Started Dec 24 02:06:30 PM PST 23
Finished Dec 24 02:07:01 PM PST 23
Peak memory 240228 kb
Host smart-b5c8d33b-c8eb-4f84-8069-bcdf6a908779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778429925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1778429925
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.4246300091
Short name T738
Test name
Test status
Simulation time 628741259 ps
CPU time 11.11 seconds
Started Dec 24 02:06:25 PM PST 23
Finished Dec 24 02:06:38 PM PST 23
Peak memory 246664 kb
Host smart-53bf1f3e-6061-451f-b069-ed18852ab887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246300091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.4246300091
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.1266499410
Short name T683
Test name
Test status
Simulation time 5454371188 ps
CPU time 15.88 seconds
Started Dec 24 02:06:34 PM PST 23
Finished Dec 24 02:06:52 PM PST 23
Peak memory 238632 kb
Host smart-3179146d-0041-4692-a68c-e9780e9b8997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266499410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.1266499410
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.2775503347
Short name T1113
Test name
Test status
Simulation time 786987637 ps
CPU time 9.25 seconds
Started Dec 24 02:06:29 PM PST 23
Finished Dec 24 02:06:39 PM PST 23
Peak memory 246592 kb
Host smart-8999e1ac-414b-4721-a463-ead079bf82b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775503347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2775503347
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.1374957643
Short name T884
Test name
Test status
Simulation time 560818006 ps
CPU time 5.07 seconds
Started Dec 24 02:06:27 PM PST 23
Finished Dec 24 02:06:33 PM PST 23
Peak memory 238468 kb
Host smart-3d259c54-bc16-46dd-aecc-53d1470cee7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374957643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1374957643
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.1522302661
Short name T774
Test name
Test status
Simulation time 1472809225 ps
CPU time 20.95 seconds
Started Dec 24 02:06:34 PM PST 23
Finished Dec 24 02:06:57 PM PST 23
Peak memory 246692 kb
Host smart-2918458f-e93e-4821-938d-cc1309297b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522302661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1522302661
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.4005533221
Short name T834
Test name
Test status
Simulation time 427536615 ps
CPU time 5.31 seconds
Started Dec 24 02:06:25 PM PST 23
Finished Dec 24 02:06:32 PM PST 23
Peak memory 243464 kb
Host smart-b4499047-51cb-49d9-b725-6934983105ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005533221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.4005533221
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.579907619
Short name T1071
Test name
Test status
Simulation time 2742172239 ps
CPU time 6.13 seconds
Started Dec 24 02:06:30 PM PST 23
Finished Dec 24 02:06:39 PM PST 23
Peak memory 243708 kb
Host smart-14d258c7-d067-42d1-ba29-8227f1945e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579907619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.579907619
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2287177505
Short name T1259
Test name
Test status
Simulation time 9257428105 ps
CPU time 17.58 seconds
Started Dec 24 02:06:30 PM PST 23
Finished Dec 24 02:06:51 PM PST 23
Peak memory 238608 kb
Host smart-ae9efa2d-0dc6-4b9f-86f1-f78b59ca1375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287177505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2287177505
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.3075457817
Short name T618
Test name
Test status
Simulation time 117124985 ps
CPU time 3.25 seconds
Started Dec 24 02:06:32 PM PST 23
Finished Dec 24 02:06:38 PM PST 23
Peak memory 246728 kb
Host smart-ca798169-4231-4263-8f41-694cabb4a1f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075457817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3075457817
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.1793796208
Short name T26
Test name
Test status
Simulation time 9344143511 ps
CPU time 157.25 seconds
Started Dec 24 02:06:34 PM PST 23
Finished Dec 24 02:09:14 PM PST 23
Peak memory 268572 kb
Host smart-2d3306d8-6ab9-46f1-8bc4-d03a40a14bd7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793796208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1793796208
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.1048341971
Short name T412
Test name
Test status
Simulation time 137350105 ps
CPU time 3.85 seconds
Started Dec 24 02:06:25 PM PST 23
Finished Dec 24 02:06:31 PM PST 23
Peak memory 243660 kb
Host smart-7be291ed-1663-4938-8a1c-6e877031d4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048341971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1048341971
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.2103245242
Short name T199
Test name
Test status
Simulation time 6000285123 ps
CPU time 79.95 seconds
Started Dec 24 02:06:25 PM PST 23
Finished Dec 24 02:07:47 PM PST 23
Peak memory 240556 kb
Host smart-8891bec8-6978-405e-8da6-182d8f383675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103245242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
2103245242
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1701790591
Short name T20
Test name
Test status
Simulation time 350141551109 ps
CPU time 2241.5 seconds
Started Dec 24 02:06:29 PM PST 23
Finished Dec 24 02:43:52 PM PST 23
Peak memory 251776 kb
Host smart-f9abf5ab-40a9-4776-9b49-cfb5f50025d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701790591 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1701790591
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.1705310644
Short name T431
Test name
Test status
Simulation time 3467717463 ps
CPU time 10.6 seconds
Started Dec 24 02:06:25 PM PST 23
Finished Dec 24 02:06:37 PM PST 23
Peak memory 238608 kb
Host smart-45de9adf-889f-4ca7-b91c-c95347478e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705310644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.1705310644
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.2565245376
Short name T1290
Test name
Test status
Simulation time 84281301 ps
CPU time 1.47 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:24 PM PST 23
Peak memory 239292 kb
Host smart-da63e5a1-237c-4105-8132-c2bfcc83ff05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565245376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2565245376
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.1202735599
Short name T757
Test name
Test status
Simulation time 472271955 ps
CPU time 6.47 seconds
Started Dec 24 02:07:41 PM PST 23
Finished Dec 24 02:07:48 PM PST 23
Peak memory 243904 kb
Host smart-a6bc6701-6c3e-4126-9bc3-4ce4f1dfa8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202735599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.1202735599
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.1415882681
Short name T954
Test name
Test status
Simulation time 1034546830 ps
CPU time 23.32 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:08:07 PM PST 23
Peak memory 246648 kb
Host smart-018519c8-2085-44c1-9279-1b2dc900cb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415882681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1415882681
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.1178875413
Short name T126
Test name
Test status
Simulation time 627177250 ps
CPU time 4.55 seconds
Started Dec 24 02:07:44 PM PST 23
Finished Dec 24 02:07:50 PM PST 23
Peak memory 245344 kb
Host smart-73bf5519-835a-4cd6-a0d3-7c231f84c8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178875413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.1178875413
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.949606113
Short name T923
Test name
Test status
Simulation time 206829301 ps
CPU time 4.22 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:49 PM PST 23
Peak memory 238524 kb
Host smart-20bf753d-ea70-46db-b193-ffef9f77ac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949606113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.949606113
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.1175885137
Short name T348
Test name
Test status
Simulation time 146652783 ps
CPU time 3.73 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:07:48 PM PST 23
Peak memory 238448 kb
Host smart-a7c86884-32e8-4fe8-9f3d-e4651a5ab4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175885137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1175885137
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.944503543
Short name T716
Test name
Test status
Simulation time 8884634169 ps
CPU time 19.07 seconds
Started Dec 24 02:07:42 PM PST 23
Finished Dec 24 02:08:03 PM PST 23
Peak memory 244148 kb
Host smart-bd9b0391-406d-499c-a622-c90c0428916b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944503543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.944503543
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.3054940352
Short name T959
Test name
Test status
Simulation time 130675517 ps
CPU time 4.11 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:08:15 PM PST 23
Peak memory 238520 kb
Host smart-8d1ae1a0-b518-4e80-8736-571500ee8559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054940352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3054940352
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.2860759876
Short name T482
Test name
Test status
Simulation time 4511520337 ps
CPU time 11.62 seconds
Started Dec 24 02:07:53 PM PST 23
Finished Dec 24 02:08:07 PM PST 23
Peak memory 238660 kb
Host smart-ced430d1-2ed2-44c9-85ac-0ceafdefa0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860759876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2860759876
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.1895102047
Short name T339
Test name
Test status
Simulation time 13271648141 ps
CPU time 83.59 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:09:34 PM PST 23
Peak memory 240888 kb
Host smart-9059bde9-16ad-489a-96f5-949e7c14984a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895102047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.1895102047
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3197235384
Short name T782
Test name
Test status
Simulation time 1265138152140 ps
CPU time 8339.24 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 04:27:23 PM PST 23
Peak memory 1720892 kb
Host smart-df52180e-8951-462c-822b-7ab83354fd6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197235384 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3197235384
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.221833291
Short name T955
Test name
Test status
Simulation time 649061612 ps
CPU time 14.27 seconds
Started Dec 24 02:07:58 PM PST 23
Finished Dec 24 02:08:24 PM PST 23
Peak memory 244136 kb
Host smart-0443e385-8930-414e-b4f4-ad2a0fb22604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221833291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.221833291
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.3149545578
Short name T904
Test name
Test status
Simulation time 91837614 ps
CPU time 1.65 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:25 PM PST 23
Peak memory 238480 kb
Host smart-63142a7a-d3a2-4944-a6d9-636c8d5024f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149545578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3149545578
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.1128155001
Short name T1038
Test name
Test status
Simulation time 581312511 ps
CPU time 11.35 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 02:08:38 PM PST 23
Peak memory 245096 kb
Host smart-4ca965db-3dc3-4e96-ba0c-0e472a07d11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128155001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1128155001
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.3750398899
Short name T988
Test name
Test status
Simulation time 494178132 ps
CPU time 5.4 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:32 PM PST 23
Peak memory 238384 kb
Host smart-60270b2c-274d-48a0-ab30-6a0312761226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750398899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.3750398899
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.4248051519
Short name T4
Test name
Test status
Simulation time 3384622677 ps
CPU time 9.52 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:08:20 PM PST 23
Peak memory 238696 kb
Host smart-faaf0405-fca6-4386-9f9f-5c5c6ff9abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248051519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.4248051519
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.1139857718
Short name T140
Test name
Test status
Simulation time 154703750 ps
CPU time 3.75 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:28 PM PST 23
Peak memory 238440 kb
Host smart-b0fcd6e8-4984-4323-8f9b-17cb3623e587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139857718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.1139857718
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.556167817
Short name T1159
Test name
Test status
Simulation time 308449440 ps
CPU time 3.27 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:08:14 PM PST 23
Peak memory 238584 kb
Host smart-e808971c-3717-4119-94f5-52c08fe701f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556167817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.556167817
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.3943199069
Short name T786
Test name
Test status
Simulation time 776075643 ps
CPU time 9.49 seconds
Started Dec 24 02:07:57 PM PST 23
Finished Dec 24 02:08:19 PM PST 23
Peak memory 244292 kb
Host smart-02691ea3-fd0d-44da-a91b-7a17ae6f0de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943199069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.3943199069
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.3467325127
Short name T479
Test name
Test status
Simulation time 1143984158 ps
CPU time 7.16 seconds
Started Dec 24 02:08:25 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 238452 kb
Host smart-044b780c-4358-4538-8fbf-48157b9ce239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467325127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.3467325127
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.2909326788
Short name T92
Test name
Test status
Simulation time 574503255 ps
CPU time 9.13 seconds
Started Dec 24 02:08:02 PM PST 23
Finished Dec 24 02:08:20 PM PST 23
Peak memory 238508 kb
Host smart-817db74b-69d7-41f0-aea0-08ab86b4ccf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2909326788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2909326788
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.2274253888
Short name T665
Test name
Test status
Simulation time 975088085 ps
CPU time 7.73 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:08:18 PM PST 23
Peak memory 238420 kb
Host smart-6881fae0-dc17-4998-921c-3d7ec4e7e6ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274253888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.2274253888
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.1274847831
Short name T411
Test name
Test status
Simulation time 4032647250 ps
CPU time 10.48 seconds
Started Dec 24 02:07:59 PM PST 23
Finished Dec 24 02:08:21 PM PST 23
Peak memory 238268 kb
Host smart-d2ba0282-3903-48bb-9aed-3556bb745916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274847831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.1274847831
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.1987338321
Short name T282
Test name
Test status
Simulation time 42130142009 ps
CPU time 166.7 seconds
Started Dec 24 02:07:57 PM PST 23
Finished Dec 24 02:10:56 PM PST 23
Peak memory 242496 kb
Host smart-53b2ec70-01ba-4659-8229-7aa1756b7b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987338321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.1987338321
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.2756593470
Short name T652
Test name
Test status
Simulation time 3164262527 ps
CPU time 10.08 seconds
Started Dec 24 02:08:09 PM PST 23
Finished Dec 24 02:08:32 PM PST 23
Peak memory 238572 kb
Host smart-0df38f9c-6686-4a53-bdbf-294615e8288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756593470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.2756593470
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.535821027
Short name T1031
Test name
Test status
Simulation time 169874161 ps
CPU time 1.66 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:40 PM PST 23
Peak memory 238216 kb
Host smart-b7fc232c-a7a4-46bc-85ba-f94ddf1d2e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535821027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.535821027
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.394975973
Short name T849
Test name
Test status
Simulation time 1493020065 ps
CPU time 4.23 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 238456 kb
Host smart-ec53fccd-8e4d-4e6a-8700-f9f49aecb943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394975973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.394975973
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.1502554437
Short name T523
Test name
Test status
Simulation time 323050156 ps
CPU time 8.78 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:32 PM PST 23
Peak memory 238292 kb
Host smart-31bba696-0308-4f61-94aa-a9b2e3420de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502554437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1502554437
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3068531291
Short name T1083
Test name
Test status
Simulation time 3743446837 ps
CPU time 21.01 seconds
Started Dec 24 02:07:58 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 246816 kb
Host smart-78ea5e81-c05d-41ea-bef3-63c734cb0b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068531291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3068531291
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.629523239
Short name T136
Test name
Test status
Simulation time 172573655 ps
CPU time 4.03 seconds
Started Dec 24 02:07:58 PM PST 23
Finished Dec 24 02:08:13 PM PST 23
Peak memory 240644 kb
Host smart-4be434c6-1578-4fd6-9c37-b2f05bf400c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629523239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.629523239
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.624606962
Short name T1078
Test name
Test status
Simulation time 2916042366 ps
CPU time 14.66 seconds
Started Dec 24 02:08:01 PM PST 23
Finished Dec 24 02:08:26 PM PST 23
Peak memory 238712 kb
Host smart-276b84c6-3454-4689-9e76-42b4b68b9b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624606962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.624606962
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.239532230
Short name T803
Test name
Test status
Simulation time 5214574088 ps
CPU time 12.43 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:36 PM PST 23
Peak memory 238664 kb
Host smart-7004bf8f-e1be-44da-a0cf-62b15cfa5b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239532230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.239532230
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1353577451
Short name T839
Test name
Test status
Simulation time 1578211907 ps
CPU time 3.52 seconds
Started Dec 24 02:07:59 PM PST 23
Finished Dec 24 02:08:14 PM PST 23
Peak memory 238376 kb
Host smart-fa26f94a-0d81-4295-92d6-2230cb53c065
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353577451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1353577451
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3184990740
Short name T947
Test name
Test status
Simulation time 150041624 ps
CPU time 3.85 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:27 PM PST 23
Peak memory 238512 kb
Host smart-2ed66279-8278-493c-a8cf-ca613108d206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184990740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3184990740
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.2471399693
Short name T582
Test name
Test status
Simulation time 3313691958 ps
CPU time 7.6 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:08:18 PM PST 23
Peak memory 244680 kb
Host smart-ed82201e-587b-4634-abe8-5546a355a5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471399693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2471399693
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.275012269
Short name T809
Test name
Test status
Simulation time 47996394618 ps
CPU time 110.79 seconds
Started Dec 24 02:08:10 PM PST 23
Finished Dec 24 02:10:13 PM PST 23
Peak memory 242252 kb
Host smart-375c1217-ba5d-4059-8dd8-c54de123cc62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275012269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.
275012269
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.58165408
Short name T337
Test name
Test status
Simulation time 247079368028 ps
CPU time 4482.43 seconds
Started Dec 24 02:08:10 PM PST 23
Finished Dec 24 03:23:05 PM PST 23
Peak memory 279460 kb
Host smart-8cc82960-3fb5-468d-b920-0837e0db9b63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58165408 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.58165408
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.3973433002
Short name T1248
Test name
Test status
Simulation time 1247692130 ps
CPU time 19.05 seconds
Started Dec 24 02:08:00 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 238364 kb
Host smart-8f7d3252-de00-4578-b1a6-3c56eba6834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973433002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3973433002
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.3608649419
Short name T570
Test name
Test status
Simulation time 99218239 ps
CPU time 1.64 seconds
Started Dec 24 02:08:40 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 238128 kb
Host smart-bc731e78-435a-4274-b047-ceb24404ab4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608649419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3608649419
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.1839470955
Short name T1284
Test name
Test status
Simulation time 379184907 ps
CPU time 6.22 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 238436 kb
Host smart-dd198b44-c838-4961-b4db-2981465e9c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839470955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1839470955
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.3828400903
Short name T974
Test name
Test status
Simulation time 7200778946 ps
CPU time 23.32 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:54 PM PST 23
Peak memory 241304 kb
Host smart-f1ac8db0-ec85-45b1-9159-4b709a1b5349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828400903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3828400903
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.1009142055
Short name T868
Test name
Test status
Simulation time 1263563030 ps
CPU time 11.66 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:36 PM PST 23
Peak memory 244076 kb
Host smart-0b9138f1-88f5-42e8-bee2-a9fdeba702c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009142055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.1009142055
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.3675860651
Short name T900
Test name
Test status
Simulation time 207759943 ps
CPU time 4.72 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:35 PM PST 23
Peak memory 241424 kb
Host smart-275b17d2-d245-4af7-826a-4473e10c60bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675860651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3675860651
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.339910200
Short name T628
Test name
Test status
Simulation time 531650103 ps
CPU time 11.3 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 243744 kb
Host smart-11e87b97-e87a-4328-86cf-91eee41fef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339910200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.339910200
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.1212048004
Short name T966
Test name
Test status
Simulation time 104517564 ps
CPU time 3.45 seconds
Started Dec 24 02:08:18 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 241300 kb
Host smart-66c6ef1a-a20b-4a82-824d-92d837982246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212048004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1212048004
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.2615917486
Short name T670
Test name
Test status
Simulation time 649738392 ps
CPU time 15.89 seconds
Started Dec 24 02:08:18 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 242080 kb
Host smart-b27ff1b5-5aed-4cb0-a0c9-eb208f63069d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615917486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2615917486
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.1192681596
Short name T314
Test name
Test status
Simulation time 660902950 ps
CPU time 4.79 seconds
Started Dec 24 02:08:17 PM PST 23
Finished Dec 24 02:08:32 PM PST 23
Peak memory 238548 kb
Host smart-4a0e0424-1600-45f7-8f3c-7a5b62adcc6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192681596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1192681596
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.456370817
Short name T1175
Test name
Test status
Simulation time 1527748149 ps
CPU time 7.09 seconds
Started Dec 24 02:07:59 PM PST 23
Finished Dec 24 02:08:17 PM PST 23
Peak memory 244032 kb
Host smart-fa560dd2-827f-4fa1-86a8-94de23a90005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456370817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.456370817
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.2092740499
Short name T418
Test name
Test status
Simulation time 849046786 ps
CPU time 5.64 seconds
Started Dec 24 02:08:34 PM PST 23
Finished Dec 24 02:08:54 PM PST 23
Peak memory 242628 kb
Host smart-428de7d0-720f-4e65-8492-36fbd15b6e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092740499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2092740499
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.1999282136
Short name T1170
Test name
Test status
Simulation time 45751660 ps
CPU time 1.54 seconds
Started Dec 24 02:08:35 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 238488 kb
Host smart-0b2c0d26-637d-44cd-a5d2-23b4fbca6b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999282136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1999282136
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.1567092463
Short name T98
Test name
Test status
Simulation time 1077210598 ps
CPU time 6.91 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:50 PM PST 23
Peak memory 238528 kb
Host smart-694df7e9-9544-402a-a96a-bebd9425aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567092463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1567092463
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.2418384190
Short name T1224
Test name
Test status
Simulation time 259090007 ps
CPU time 4.52 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 238396 kb
Host smart-e7a3e60e-1c1e-4715-9fb3-9a4a85173469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418384190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2418384190
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.2460186398
Short name T1034
Test name
Test status
Simulation time 941487750 ps
CPU time 11.73 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:54 PM PST 23
Peak memory 238560 kb
Host smart-48518cd2-bad8-40ca-ba01-d6d647790773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460186398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2460186398
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.47954999
Short name T1149
Test name
Test status
Simulation time 201956255 ps
CPU time 4.47 seconds
Started Dec 24 02:08:34 PM PST 23
Finished Dec 24 02:08:53 PM PST 23
Peak memory 241204 kb
Host smart-753e2764-60c7-4a9a-9cb4-5e0c46a1e66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47954999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.47954999
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.1102786683
Short name T125
Test name
Test status
Simulation time 830312775 ps
CPU time 16.81 seconds
Started Dec 24 02:08:45 PM PST 23
Finished Dec 24 02:09:16 PM PST 23
Peak memory 238452 kb
Host smart-85467f54-5070-47d0-b3e4-54ae67ee117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102786683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.1102786683
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.355799055
Short name T426
Test name
Test status
Simulation time 311729348 ps
CPU time 4.79 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 238512 kb
Host smart-14964de8-ff34-4fbc-8663-7b2829383913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355799055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.355799055
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3217075821
Short name T324
Test name
Test status
Simulation time 248686551 ps
CPU time 2.7 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 240196 kb
Host smart-499ca2b7-e3c4-410f-ba86-a135ddd58157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217075821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3217075821
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.2632101718
Short name T1177
Test name
Test status
Simulation time 8681084982 ps
CPU time 18.69 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 238540 kb
Host smart-ac8d216a-91ba-4552-8bfd-af9f19aee81f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632101718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2632101718
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.1996558721
Short name T982
Test name
Test status
Simulation time 487988819 ps
CPU time 6.91 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 246724 kb
Host smart-f4151d86-5d9a-41b2-a696-23380d97dc42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996558721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1996558721
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.2871868185
Short name T823
Test name
Test status
Simulation time 1339106159 ps
CPU time 8.19 seconds
Started Dec 24 02:08:40 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 243504 kb
Host smart-befc53e5-d158-458c-9d49-8de711ef8684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871868185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.2871868185
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2111459215
Short name T1291
Test name
Test status
Simulation time 2220780046818 ps
CPU time 5804.9 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 03:45:33 PM PST 23
Peak memory 1060376 kb
Host smart-cae9febd-ff75-4d7e-b243-fbceca5a8aa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111459215 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.2111459215
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.298988779
Short name T1228
Test name
Test status
Simulation time 1835810516 ps
CPU time 15.71 seconds
Started Dec 24 02:08:40 PM PST 23
Finished Dec 24 02:09:11 PM PST 23
Peak memory 237636 kb
Host smart-9bb059ad-cc59-4c45-b1b4-e6c3d52aa455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298988779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.298988779
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.4112941495
Short name T1106
Test name
Test status
Simulation time 141416431 ps
CPU time 2.01 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:25 PM PST 23
Peak memory 239164 kb
Host smart-94bf2b68-fee2-44f5-8280-bd16904d2dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112941495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.4112941495
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.3179278262
Short name T549
Test name
Test status
Simulation time 1438022920 ps
CPU time 7.66 seconds
Started Dec 24 02:08:38 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 238544 kb
Host smart-d1bcb3d6-c978-4867-99eb-5457795babcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179278262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.3179278262
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.1757539569
Short name T617
Test name
Test status
Simulation time 196081519 ps
CPU time 8.11 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 243460 kb
Host smart-37180845-e57c-4d6a-899c-03500370f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757539569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.1757539569
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.1387159287
Short name T104
Test name
Test status
Simulation time 554781923 ps
CPU time 10.97 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:09:07 PM PST 23
Peak memory 238472 kb
Host smart-75bc01f8-bbbd-4c1f-be2c-7e78589b027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387159287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1387159287
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1739832052
Short name T460
Test name
Test status
Simulation time 140723269 ps
CPU time 3.55 seconds
Started Dec 24 02:08:42 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 238340 kb
Host smart-3aaf8328-892d-4c17-9904-4512997ff101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739832052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1739832052
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.1616421100
Short name T445
Test name
Test status
Simulation time 352750845 ps
CPU time 7.2 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 238620 kb
Host smart-d627ee50-d322-483a-8433-99a5aea9fe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616421100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1616421100
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.3743972019
Short name T828
Test name
Test status
Simulation time 1783290958 ps
CPU time 10.48 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:08 PM PST 23
Peak memory 244412 kb
Host smart-d1acc1be-f65c-49b5-a097-f9aa832ffc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743972019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3743972019
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.3458736581
Short name T430
Test name
Test status
Simulation time 713265254 ps
CPU time 8.66 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 246436 kb
Host smart-40d6c4ae-a753-44f1-8d59-b2167915ecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458736581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3458736581
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.1391645087
Short name T912
Test name
Test status
Simulation time 1453411118 ps
CPU time 14.38 seconds
Started Dec 24 02:08:34 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 238404 kb
Host smart-8c68d8a5-e69c-4701-ad25-491d60f0f4be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391645087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1391645087
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.1092976100
Short name T106
Test name
Test status
Simulation time 3815195436 ps
CPU time 11.65 seconds
Started Dec 24 02:08:35 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 238680 kb
Host smart-9a180263-a29a-4427-b57b-6a687b66fa82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1092976100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1092976100
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.1038900536
Short name T535
Test name
Test status
Simulation time 204376369 ps
CPU time 5.81 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 246676 kb
Host smart-e8b12f53-6eda-4c87-b788-af51d0732936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038900536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.1038900536
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.2309637622
Short name T197
Test name
Test status
Simulation time 11788350046 ps
CPU time 118.78 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:10:29 PM PST 23
Peak memory 242236 kb
Host smart-48811e19-08dd-49c9-b150-4a07cd3a3919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309637622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.2309637622
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.2113801089
Short name T216
Test name
Test status
Simulation time 172907906675 ps
CPU time 2884.42 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:56:43 PM PST 23
Peak memory 312624 kb
Host smart-b060897f-ff54-41d8-a6f8-d5dfa187d41a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113801089 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.2113801089
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.2122271506
Short name T1155
Test name
Test status
Simulation time 1230402061 ps
CPU time 7.45 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 245168 kb
Host smart-9415bfaa-1b07-47eb-97a2-339d3d050e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122271506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.2122271506
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.1087652660
Short name T651
Test name
Test status
Simulation time 102595179 ps
CPU time 1.72 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 238544 kb
Host smart-f3bc473f-78e9-4258-8eb6-08aa3ac37bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087652660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1087652660
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.2729710634
Short name T33
Test name
Test status
Simulation time 967949167 ps
CPU time 14.86 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:08:49 PM PST 23
Peak memory 238536 kb
Host smart-dbc90d50-5d89-4b4e-9720-b2f47564944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729710634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2729710634
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.3882023994
Short name T636
Test name
Test status
Simulation time 1040454357 ps
CPU time 12.68 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:38 PM PST 23
Peak memory 239256 kb
Host smart-2f0445af-748d-403c-89f6-6ca8c5cf03d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882023994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3882023994
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.258546577
Short name T806
Test name
Test status
Simulation time 1381564019 ps
CPU time 16.32 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:08:39 PM PST 23
Peak memory 243956 kb
Host smart-cde245d0-8aa9-4eec-8f69-53881a1891e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258546577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.258546577
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2351845039
Short name T29
Test name
Test status
Simulation time 532735511 ps
CPU time 4.68 seconds
Started Dec 24 02:08:20 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 238480 kb
Host smart-0f2bcd02-78d4-4bd0-a87d-6d818559b3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351845039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2351845039
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3105855247
Short name T119
Test name
Test status
Simulation time 1672755272 ps
CPU time 18.32 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 238712 kb
Host smart-e6a1d7a8-dad0-4760-be09-aaa39587ce51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105855247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3105855247
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.4121752228
Short name T349
Test name
Test status
Simulation time 3110336765 ps
CPU time 19.27 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 238732 kb
Host smart-a9cd0756-4b95-4d63-a2b8-f5cde1a198ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121752228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.4121752228
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.1801253729
Short name T1003
Test name
Test status
Simulation time 563426701 ps
CPU time 6.74 seconds
Started Dec 24 02:08:18 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 237580 kb
Host smart-f5b831a6-5e0b-4930-8fad-8c08b6c390ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801253729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1801253729
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.1907856438
Short name T943
Test name
Test status
Simulation time 365809881 ps
CPU time 5.82 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:33 PM PST 23
Peak memory 243496 kb
Host smart-2d2ec93b-8f50-4d1d-85a1-171bc019fc4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907856438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1907856438
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.1915084136
Short name T902
Test name
Test status
Simulation time 216706007 ps
CPU time 8.59 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 02:08:33 PM PST 23
Peak memory 238444 kb
Host smart-7da4dc19-3b01-465a-b30c-5ec0c98b753f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915084136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1915084136
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.2864048532
Short name T910
Test name
Test status
Simulation time 510419593 ps
CPU time 3.37 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 238460 kb
Host smart-03792edc-468d-45dc-a1b2-43509297ef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864048532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.2864048532
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.1895373471
Short name T277
Test name
Test status
Simulation time 3795589807 ps
CPU time 16.94 seconds
Started Dec 24 02:08:19 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 238532 kb
Host smart-8d79de83-a33e-4884-8f89-99991eee0f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895373471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.1895373471
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.628887394
Short name T305
Test name
Test status
Simulation time 884130940427 ps
CPU time 6912 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 04:03:36 PM PST 23
Peak memory 1026052 kb
Host smart-72b92e7b-2b51-40fe-aa16-4257f7ac53fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628887394 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.628887394
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.544404516
Short name T414
Test name
Test status
Simulation time 840437753 ps
CPU time 4.83 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:08:38 PM PST 23
Peak memory 242640 kb
Host smart-73c5d7db-837d-47a5-ad59-7ea1a0d56eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544404516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.544404516
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.2366226124
Short name T893
Test name
Test status
Simulation time 118589943 ps
CPU time 2.14 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 237888 kb
Host smart-b060ed50-b5d1-4ac3-a9a2-54edbb95b4f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366226124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2366226124
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.3715909682
Short name T289
Test name
Test status
Simulation time 1827321111 ps
CPU time 16.16 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 02:08:41 PM PST 23
Peak memory 238708 kb
Host smart-8eda54d4-df2d-4c4e-a4a1-beb71a116784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715909682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3715909682
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.2794388281
Short name T304
Test name
Test status
Simulation time 2499484591 ps
CPU time 7.61 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 238632 kb
Host smart-5f2b9939-a20c-474b-903e-e21495972600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794388281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.2794388281
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.2797468351
Short name T1111
Test name
Test status
Simulation time 1293699264 ps
CPU time 8.35 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 238636 kb
Host smart-81531791-c940-4f1c-920b-d5b492c17f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797468351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.2797468351
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.3395488695
Short name T509
Test name
Test status
Simulation time 2170125480 ps
CPU time 6.94 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:49 PM PST 23
Peak memory 238512 kb
Host smart-fad149d6-9305-4dc3-b114-49006aad7051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395488695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.3395488695
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.1901885964
Short name T1088
Test name
Test status
Simulation time 1412056114 ps
CPU time 4.26 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 238448 kb
Host smart-de2c0e1b-f465-4882-974f-da22c42f9181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901885964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.1901885964
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.2252815890
Short name T1201
Test name
Test status
Simulation time 896084214 ps
CPU time 15.99 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:56 PM PST 23
Peak memory 244564 kb
Host smart-5e678147-d271-4ce0-a44d-3c05872a2b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252815890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2252815890
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.425478115
Short name T1185
Test name
Test status
Simulation time 1489828167 ps
CPU time 4.56 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 242300 kb
Host smart-0c82499d-c4c2-4791-b2c3-6465bd06c919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425478115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.425478115
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.1556403428
Short name T679
Test name
Test status
Simulation time 1789719450 ps
CPU time 14 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 238596 kb
Host smart-6b401c09-6828-44cb-a163-fc4df90bc721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556403428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1556403428
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.816188049
Short name T1143
Test name
Test status
Simulation time 260908553 ps
CPU time 3.71 seconds
Started Dec 24 02:08:19 PM PST 23
Finished Dec 24 02:08:32 PM PST 23
Peak memory 243820 kb
Host smart-f4763514-0139-4379-9600-c61c409456c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=816188049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.816188049
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3945049979
Short name T695
Test name
Test status
Simulation time 506626259 ps
CPU time 7.22 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 245124 kb
Host smart-59f50a64-2170-48b7-8840-12240c830d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945049979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3945049979
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.1480483800
Short name T619
Test name
Test status
Simulation time 4242519722 ps
CPU time 28.06 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 239888 kb
Host smart-d761c54e-319f-46c9-a095-81388616cea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480483800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.1480483800
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.2013057914
Short name T1068
Test name
Test status
Simulation time 164038400559 ps
CPU time 1694.79 seconds
Started Dec 24 02:08:38 PM PST 23
Finished Dec 24 02:37:09 PM PST 23
Peak memory 328812 kb
Host smart-7743f0f3-1880-407a-ade8-50bdfe325830
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013057914 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.2013057914
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.860094792
Short name T816
Test name
Test status
Simulation time 1574686935 ps
CPU time 10.08 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 238416 kb
Host smart-38025742-81a1-4b06-b25e-3fa72b577e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860094792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.860094792
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.1778816501
Short name T1214
Test name
Test status
Simulation time 52838346 ps
CPU time 1.62 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 238584 kb
Host smart-4acbfab6-169a-41ec-b184-f840f8dc1f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778816501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1778816501
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.4249610741
Short name T1242
Test name
Test status
Simulation time 1354511583 ps
CPU time 8.27 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 238468 kb
Host smart-2950a590-2a42-4013-81a4-e32bec64e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249610741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.4249610741
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.3630620908
Short name T992
Test name
Test status
Simulation time 1407326800 ps
CPU time 4.43 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 241772 kb
Host smart-0615f6b4-ec2b-4395-8542-6f7ce5615fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630620908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3630620908
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.4154519838
Short name T826
Test name
Test status
Simulation time 942794904 ps
CPU time 13.26 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:09:05 PM PST 23
Peak memory 243376 kb
Host smart-75e9d2b6-9c5c-4c71-bc4d-95c0da68a75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154519838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.4154519838
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.1123325556
Short name T1238
Test name
Test status
Simulation time 166193146 ps
CPU time 4.4 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:35 PM PST 23
Peak memory 241060 kb
Host smart-6b0de882-600a-42a3-86b1-09f4a3875f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123325556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1123325556
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.178999800
Short name T1007
Test name
Test status
Simulation time 152784787 ps
CPU time 2.5 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:08:54 PM PST 23
Peak memory 238492 kb
Host smart-bbfc719b-b1d3-4875-8389-e8d499f60d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178999800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.178999800
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.4241140530
Short name T629
Test name
Test status
Simulation time 1409599013 ps
CPU time 15.87 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:09:10 PM PST 23
Peak memory 244092 kb
Host smart-617904ad-4ba3-495e-ad77-0d27c4f7a306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241140530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.4241140530
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.3199617641
Short name T298
Test name
Test status
Simulation time 422921326 ps
CPU time 4.42 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 241132 kb
Host smart-a60145bf-c164-4a4e-bce2-7903cec4c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199617641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.3199617641
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.4002696412
Short name T516
Test name
Test status
Simulation time 408522247 ps
CPU time 12.75 seconds
Started Dec 24 02:08:45 PM PST 23
Finished Dec 24 02:09:12 PM PST 23
Peak memory 243116 kb
Host smart-90a6dc8a-e004-4df5-8e77-cd576f563026
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002696412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.4002696412
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.3509816943
Short name T714
Test name
Test status
Simulation time 263245933 ps
CPU time 7.5 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 245492 kb
Host smart-f7449f8a-4063-4dc3-84f6-9ba3e8a1b81b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509816943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.3509816943
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.306705648
Short name T1114
Test name
Test status
Simulation time 2295913691 ps
CPU time 4.64 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 241316 kb
Host smart-9ef4083a-2693-40ae-a8fb-83283c422763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306705648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.306705648
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.2184626286
Short name T192
Test name
Test status
Simulation time 1959975771 ps
CPU time 49.74 seconds
Started Dec 24 02:08:36 PM PST 23
Finished Dec 24 02:09:41 PM PST 23
Peak memory 245920 kb
Host smart-d4f465dd-24f3-4498-b2d9-1ed43bcf8c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184626286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.2184626286
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.826108593
Short name T1249
Test name
Test status
Simulation time 519393889789 ps
CPU time 3420.97 seconds
Started Dec 24 02:07:59 PM PST 23
Finished Dec 24 03:05:12 PM PST 23
Peak memory 271576 kb
Host smart-a5a93aa8-9974-430f-a0c0-3191561ea879
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826108593 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.826108593
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1405011386
Short name T1218
Test name
Test status
Simulation time 505321520 ps
CPU time 7.09 seconds
Started Dec 24 02:08:40 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 238488 kb
Host smart-f381c2cc-aaae-41ca-8495-77f97da2ab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405011386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1405011386
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.5974481
Short name T1026
Test name
Test status
Simulation time 68234020 ps
CPU time 1.88 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:08:54 PM PST 23
Peak memory 238624 kb
Host smart-bbbe8a87-a115-49d9-bf83-c9c00c7e77bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5974481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.5974481
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.1440950345
Short name T563
Test name
Test status
Simulation time 3825399928 ps
CPU time 14.47 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:09:09 PM PST 23
Peak memory 238992 kb
Host smart-406aef80-7cf1-4d89-a093-707ee37e42b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440950345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1440950345
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.912548352
Short name T300
Test name
Test status
Simulation time 509170456 ps
CPU time 6.9 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:55 PM PST 23
Peak memory 238328 kb
Host smart-cc9ffcbe-c49a-4c3a-b90d-7b75bb743445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912548352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.912548352
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.3718051196
Short name T580
Test name
Test status
Simulation time 280415918 ps
CPU time 3.32 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 241424 kb
Host smart-45c25bdf-bfc7-4bec-a9ae-dc7a1e925b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718051196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3718051196
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.3904897191
Short name T427
Test name
Test status
Simulation time 258019705 ps
CPU time 4.09 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 240408 kb
Host smart-6dace10d-b3fd-402b-95bd-be70e5cac00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904897191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3904897191
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.1291713078
Short name T281
Test name
Test status
Simulation time 413639582 ps
CPU time 9.28 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:56 PM PST 23
Peak memory 238632 kb
Host smart-e0beaf85-5b01-4d4f-8b71-007f7e59eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291713078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1291713078
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.3574199865
Short name T973
Test name
Test status
Simulation time 218380963 ps
CPU time 4.57 seconds
Started Dec 24 02:08:42 PM PST 23
Finished Dec 24 02:09:02 PM PST 23
Peak memory 238552 kb
Host smart-65b7ff20-60be-442d-bcc4-63b416241be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574199865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.3574199865
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.304924482
Short name T154
Test name
Test status
Simulation time 3019785712 ps
CPU time 5.94 seconds
Started Dec 24 02:08:40 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 243456 kb
Host smart-b038dd62-8192-4658-97a6-4be89d0d689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304924482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.304924482
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.2235595671
Short name T198
Test name
Test status
Simulation time 774445766 ps
CPU time 22.06 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:09:08 PM PST 23
Peak memory 238484 kb
Host smart-ff8063e9-2bc5-47f6-8eb0-9086214f7456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235595671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2235595671
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.32945956
Short name T1229
Test name
Test status
Simulation time 196882277 ps
CPU time 2.68 seconds
Started Dec 24 02:08:38 PM PST 23
Finished Dec 24 02:08:56 PM PST 23
Peak memory 240760 kb
Host smart-d4ed6ef1-2b62-4475-a5b8-a6d29bffdf65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32945956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.32945956
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.1498771336
Short name T1146
Test name
Test status
Simulation time 289042468 ps
CPU time 4.63 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 242128 kb
Host smart-cde84ec8-c264-471f-8364-8397cb691ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498771336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.1498771336
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.3054402944
Short name T513
Test name
Test status
Simulation time 23574401020 ps
CPU time 114.14 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:10:50 PM PST 23
Peak memory 246868 kb
Host smart-478cb912-badd-469d-8048-d0b64b6fda75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054402944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.3054402944
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.1754503804
Short name T97
Test name
Test status
Simulation time 438060612 ps
CPU time 10.52 seconds
Started Dec 24 02:08:44 PM PST 23
Finished Dec 24 02:09:08 PM PST 23
Peak memory 238584 kb
Host smart-15ef6d2f-7c25-4179-8a43-8e4adcc1d07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754503804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1754503804
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.2709567314
Short name T747
Test name
Test status
Simulation time 92167577 ps
CPU time 1.75 seconds
Started Dec 24 02:06:39 PM PST 23
Finished Dec 24 02:06:42 PM PST 23
Peak memory 238520 kb
Host smart-696376b3-672d-440d-bbee-69f99fac1d2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709567314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2709567314
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.770380217
Short name T487
Test name
Test status
Simulation time 2446684024 ps
CPU time 19.25 seconds
Started Dec 24 02:06:23 PM PST 23
Finished Dec 24 02:06:45 PM PST 23
Peak memory 243876 kb
Host smart-e1269b28-b10a-4038-b078-9671f168b7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770380217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.770380217
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.2165160458
Short name T770
Test name
Test status
Simulation time 1412377572 ps
CPU time 13.77 seconds
Started Dec 24 02:06:31 PM PST 23
Finished Dec 24 02:06:48 PM PST 23
Peak memory 246564 kb
Host smart-60e76cb9-e2e1-44f7-8d35-eb2d14888ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165160458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2165160458
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.1748822726
Short name T1098
Test name
Test status
Simulation time 223730482 ps
CPU time 6.32 seconds
Started Dec 24 02:06:30 PM PST 23
Finished Dec 24 02:06:40 PM PST 23
Peak memory 238504 kb
Host smart-11c2aaf7-4f62-41d3-88ac-8faa7f4053a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748822726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1748822726
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.2593389461
Short name T338
Test name
Test status
Simulation time 862849506 ps
CPU time 20.03 seconds
Started Dec 24 02:06:29 PM PST 23
Finished Dec 24 02:06:50 PM PST 23
Peak memory 238544 kb
Host smart-0e94631b-e208-44ba-bb2b-11bf5dcaae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593389461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2593389461
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.2381541158
Short name T84
Test name
Test status
Simulation time 2237646778 ps
CPU time 4.56 seconds
Started Dec 24 02:06:30 PM PST 23
Finished Dec 24 02:06:38 PM PST 23
Peak memory 241352 kb
Host smart-30bf320d-e078-4de8-9cbc-7ef287131f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381541158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.2381541158
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.3182856029
Short name T287
Test name
Test status
Simulation time 983028633 ps
CPU time 9.49 seconds
Started Dec 24 02:06:25 PM PST 23
Finished Dec 24 02:06:36 PM PST 23
Peak memory 238564 kb
Host smart-4a0ccfa5-f5d9-4253-bbd2-532e910c3aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182856029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3182856029
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.3529901945
Short name T158
Test name
Test status
Simulation time 10368536033 ps
CPU time 19.87 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 246740 kb
Host smart-e52d4c03-f564-4fef-84bd-959e7cf2f526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529901945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3529901945
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.315881040
Short name T1075
Test name
Test status
Simulation time 140557465 ps
CPU time 3.15 seconds
Started Dec 24 02:06:34 PM PST 23
Finished Dec 24 02:06:40 PM PST 23
Peak memory 241348 kb
Host smart-b97c1780-4f33-4fde-97d4-0ce54aed1170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315881040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.315881040
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.1050729709
Short name T611
Test name
Test status
Simulation time 1063974522 ps
CPU time 9.24 seconds
Started Dec 24 02:06:31 PM PST 23
Finished Dec 24 02:06:44 PM PST 23
Peak memory 238476 kb
Host smart-599c222d-eecc-4995-9f90-fcd9a079d4ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1050729709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1050729709
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.681288574
Short name T1219
Test name
Test status
Simulation time 164619193 ps
CPU time 5.2 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:10 PM PST 23
Peak memory 237592 kb
Host smart-61b464fe-a783-453b-9c86-5f16bb2dbc36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=681288574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.681288574
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.2671570
Short name T1122
Test name
Test status
Simulation time 262847295 ps
CPU time 4.05 seconds
Started Dec 24 02:06:28 PM PST 23
Finished Dec 24 02:06:33 PM PST 23
Peak memory 240304 kb
Host smart-75bd56d2-ecdb-496b-8a55-b2d957fbf06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.2671570
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.2119718979
Short name T1042
Test name
Test status
Simulation time 22901401153 ps
CPU time 144.5 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:09:22 PM PST 23
Peak memory 246960 kb
Host smart-4265fcc6-41d5-40f1-affa-fdefcda99d8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119718979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
2119718979
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.46017548
Short name T335
Test name
Test status
Simulation time 441357134740 ps
CPU time 3388.51 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 03:03:31 PM PST 23
Peak memory 318988 kb
Host smart-767647dc-e971-4fa9-b4aa-f0f3ae89e534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46017548 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.46017548
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.1208276699
Short name T1011
Test name
Test status
Simulation time 12012443278 ps
CPU time 31.05 seconds
Started Dec 24 02:06:41 PM PST 23
Finished Dec 24 02:07:12 PM PST 23
Peak memory 238720 kb
Host smart-b43d9290-2864-4fc8-994d-701c1a87ed60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208276699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1208276699
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.2067210611
Short name T142
Test name
Test status
Simulation time 520922363 ps
CPU time 4.23 seconds
Started Dec 24 02:08:56 PM PST 23
Finished Dec 24 02:09:11 PM PST 23
Peak memory 238528 kb
Host smart-4a8cc61d-d496-4773-b735-83cbba603b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067210611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.2067210611
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.3179473167
Short name T480
Test name
Test status
Simulation time 335471663 ps
CPU time 6.94 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 238372 kb
Host smart-bba27395-389f-4f61-830c-8abc6f1dfe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179473167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.3179473167
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.553501050
Short name T122
Test name
Test status
Simulation time 116105736911 ps
CPU time 1359.23 seconds
Started Dec 24 02:08:35 PM PST 23
Finished Dec 24 02:31:30 PM PST 23
Peak memory 278388 kb
Host smart-5618c67f-fca9-4b09-9810-d4cd39f2c5b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553501050 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.553501050
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.3555919536
Short name T1150
Test name
Test status
Simulation time 102594241 ps
CPU time 3.97 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:51 PM PST 23
Peak memory 238436 kb
Host smart-7623fabf-b5a0-4df0-8441-7e3b94232de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555919536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.3555919536
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.549059370
Short name T1216
Test name
Test status
Simulation time 242764695 ps
CPU time 8.12 seconds
Started Dec 24 02:08:53 PM PST 23
Finished Dec 24 02:09:13 PM PST 23
Peak memory 238520 kb
Host smart-3e674792-e057-4c0f-8e78-19b3b36510c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549059370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.549059370
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.681994461
Short name T892
Test name
Test status
Simulation time 331094409409 ps
CPU time 4441.8 seconds
Started Dec 24 02:08:36 PM PST 23
Finished Dec 24 03:22:54 PM PST 23
Peak memory 263080 kb
Host smart-8c7ac450-96c8-4ce7-b0e2-094f8518f8f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681994461 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.681994461
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.2405412768
Short name T71
Test name
Test status
Simulation time 160447857 ps
CPU time 3.94 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 238312 kb
Host smart-638e1dc4-84d8-44a6-8b6c-2130b882c860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405412768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2405412768
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.627535660
Short name T2
Test name
Test status
Simulation time 2769704949 ps
CPU time 3.99 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 242120 kb
Host smart-e1ec9752-0000-48ea-9854-e00c7ca9ed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627535660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.627535660
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.2095374878
Short name T1056
Test name
Test status
Simulation time 718129467115 ps
CPU time 3787.09 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 03:11:53 PM PST 23
Peak memory 464428 kb
Host smart-04f5ce84-0705-40f3-8a79-f0de77a952e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095374878 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.2095374878
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.2082587120
Short name T961
Test name
Test status
Simulation time 2787321538 ps
CPU time 6.23 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 238556 kb
Host smart-6820889e-70ac-45a7-81d9-f9e9cad3cb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082587120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.2082587120
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.3855595044
Short name T724
Test name
Test status
Simulation time 150774783 ps
CPU time 3.78 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 241196 kb
Host smart-1350d0b5-28ee-4dbd-98d2-288eb15fba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855595044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3855595044
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.223840027
Short name T693
Test name
Test status
Simulation time 162369605530 ps
CPU time 1750.79 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:37:36 PM PST 23
Peak memory 247016 kb
Host smart-42421aa5-66c3-41e7-9005-499278e87af0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223840027 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.223840027
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.1536901149
Short name T147
Test name
Test status
Simulation time 196893360 ps
CPU time 3.04 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:28 PM PST 23
Peak memory 238476 kb
Host smart-5e15af7b-3908-4226-8061-556f4a863d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536901149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1536901149
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.731249885
Short name T694
Test name
Test status
Simulation time 284506904 ps
CPU time 5.03 seconds
Started Dec 24 02:08:20 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 242612 kb
Host smart-47cfa7d2-9eb1-4126-94c6-aa9438dfbe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731249885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.731249885
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.1435191931
Short name T882
Test name
Test status
Simulation time 4794780815599 ps
CPU time 4156.11 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 03:17:42 PM PST 23
Peak memory 296184 kb
Host smart-9ba2f9a0-a01c-4dc9-9ad0-ad8864d218d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435191931 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.1435191931
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.2557566536
Short name T965
Test name
Test status
Simulation time 383889864 ps
CPU time 4.78 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 238392 kb
Host smart-f8540c24-1271-4017-936e-832a6979ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557566536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2557566536
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.2460719922
Short name T639
Test name
Test status
Simulation time 1253612625 ps
CPU time 8.74 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 238372 kb
Host smart-9b891bd5-7f90-44bf-beaf-d756c9feb989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460719922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2460719922
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.4156970755
Short name T23
Test name
Test status
Simulation time 124398856575 ps
CPU time 1710.69 seconds
Started Dec 24 02:08:20 PM PST 23
Finished Dec 24 02:37:00 PM PST 23
Peak memory 257104 kb
Host smart-ee3c1fa5-dce2-4927-aec4-796e856352ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156970755 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.4156970755
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.3817854875
Short name T1221
Test name
Test status
Simulation time 172816679 ps
CPU time 4.49 seconds
Started Dec 24 02:08:25 PM PST 23
Finished Dec 24 02:08:40 PM PST 23
Peak memory 240952 kb
Host smart-8872f47b-1cc4-4296-80ae-c0b83b07a263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817854875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.3817854875
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.2066928405
Short name T1062
Test name
Test status
Simulation time 163685203 ps
CPU time 4.93 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 238484 kb
Host smart-e8908d69-9ad6-4564-8452-5b839da74a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066928405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2066928405
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.3518274057
Short name T1107
Test name
Test status
Simulation time 577136096715 ps
CPU time 4331.23 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 03:20:38 PM PST 23
Peak memory 287792 kb
Host smart-ca7a76de-92b8-4cd4-a5a6-ddc4a2daf8a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518274057 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.3518274057
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.2860080352
Short name T746
Test name
Test status
Simulation time 1786514651 ps
CPU time 6.4 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 242440 kb
Host smart-ad359881-d1ac-4caf-b4cf-81e302ee948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860080352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2860080352
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.424228639
Short name T625
Test name
Test status
Simulation time 144887484339 ps
CPU time 2061.06 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:43:00 PM PST 23
Peak memory 255988 kb
Host smart-e76b46c2-bb66-4bb1-86aa-53ccc4edc90f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424228639 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.424228639
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.3138436710
Short name T1080
Test name
Test status
Simulation time 483414836 ps
CPU time 3.68 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:27 PM PST 23
Peak memory 238528 kb
Host smart-d7065399-5ba4-4d95-a500-1aa2e3b0adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138436710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3138436710
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.2251275291
Short name T558
Test name
Test status
Simulation time 1555409752 ps
CPU time 2.75 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 241100 kb
Host smart-bc22b73d-1e06-45a4-9613-5a7adb0c4407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251275291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2251275291
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2316632631
Short name T18
Test name
Test status
Simulation time 891449257461 ps
CPU time 5979.53 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 03:48:05 PM PST 23
Peak memory 367268 kb
Host smart-3327fe12-a6bc-4e2c-8df9-c2f20e22ec14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316632631 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.2316632631
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.900477623
Short name T159
Test name
Test status
Simulation time 178616587 ps
CPU time 2.76 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:41 PM PST 23
Peak memory 240544 kb
Host smart-69d19fd4-2ccd-4826-bb12-35fcc600280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900477623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.900477623
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.231312497
Short name T172
Test name
Test status
Simulation time 372196873 ps
CPU time 4.83 seconds
Started Dec 24 02:08:19 PM PST 23
Finished Dec 24 02:08:33 PM PST 23
Peak memory 238316 kb
Host smart-91b288a6-2d6f-4adc-b07c-9cd9eabd7388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231312497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.231312497
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.1705829637
Short name T264
Test name
Test status
Simulation time 170303359962 ps
CPU time 1973.65 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:41:21 PM PST 23
Peak memory 287028 kb
Host smart-19514549-ccee-4982-a5c1-c693c2651fd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705829637 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.1705829637
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.2709792791
Short name T885
Test name
Test status
Simulation time 67963695 ps
CPU time 1.65 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:06:51 PM PST 23
Peak memory 238256 kb
Host smart-e99afb61-85a5-4940-b524-ea361373fe49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709792791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2709792791
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.3980872076
Short name T734
Test name
Test status
Simulation time 3451859041 ps
CPU time 28.88 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:07:15 PM PST 23
Peak memory 243996 kb
Host smart-17a4666a-56c1-41de-a659-9b35b0d6e252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980872076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3980872076
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.481458009
Short name T1164
Test name
Test status
Simulation time 1181290249 ps
CPU time 4.92 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:06:50 PM PST 23
Peak memory 243236 kb
Host smart-aa090c92-4fbd-4e42-95e2-3ef9ee5b4e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481458009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.481458009
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.1521412119
Short name T494
Test name
Test status
Simulation time 150231694 ps
CPU time 4.76 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 02:06:56 PM PST 23
Peak memory 242684 kb
Host smart-6bc379cf-855f-43dc-91d8-c09cc4ffc152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521412119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1521412119
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.3139734591
Short name T1044
Test name
Test status
Simulation time 639786437 ps
CPU time 18.71 seconds
Started Dec 24 02:06:42 PM PST 23
Finished Dec 24 02:07:01 PM PST 23
Peak memory 238572 kb
Host smart-a6c07b57-89d9-496f-ba40-6c916a82f6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139734591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3139734591
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.1336211856
Short name T10
Test name
Test status
Simulation time 210394267 ps
CPU time 4.24 seconds
Started Dec 24 02:06:53 PM PST 23
Finished Dec 24 02:07:01 PM PST 23
Peak memory 246560 kb
Host smart-4e2e1674-a725-40f4-9764-4cd734365412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336211856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1336211856
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.3990625027
Short name T118
Test name
Test status
Simulation time 4513850856 ps
CPU time 28.98 seconds
Started Dec 24 02:06:47 PM PST 23
Finished Dec 24 02:07:22 PM PST 23
Peak memory 238724 kb
Host smart-a3b2ab50-38e4-4b72-8011-0370481049bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990625027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3990625027
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.2302973519
Short name T330
Test name
Test status
Simulation time 673987705 ps
CPU time 5.65 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:05 PM PST 23
Peak memory 243660 kb
Host smart-4ce5476c-05b5-4eb8-8bd9-cb2c007e6931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302973519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2302973519
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.2516016994
Short name T429
Test name
Test status
Simulation time 258419082 ps
CPU time 3.88 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:06:52 PM PST 23
Peak memory 246620 kb
Host smart-2a38650a-ce5c-4cda-82ec-16e7f53c1e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516016994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.2516016994
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.4149212082
Short name T1243
Test name
Test status
Simulation time 676651833 ps
CPU time 7.53 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:06:57 PM PST 23
Peak memory 238504 kb
Host smart-be280a8f-2f6d-4224-a201-876832431e4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149212082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.4149212082
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.1282225989
Short name T993
Test name
Test status
Simulation time 273759603 ps
CPU time 4.1 seconds
Started Dec 24 02:07:01 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 238568 kb
Host smart-2b84b03c-4a58-4a9f-ac2c-1fdb34cc9ee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1282225989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1282225989
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.463986372
Short name T1021
Test name
Test status
Simulation time 4663584861 ps
CPU time 8.03 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:12 PM PST 23
Peak memory 238604 kb
Host smart-e540f918-47f7-4f5f-bca2-a6f956587861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463986372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.463986372
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.1629095793
Short name T1272
Test name
Test status
Simulation time 35355136750 ps
CPU time 65.99 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:07:56 PM PST 23
Peak memory 244400 kb
Host smart-6f6ad895-3af5-492e-8ce8-228bd14d8532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629095793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
1629095793
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.427558084
Short name T607
Test name
Test status
Simulation time 1971278690032 ps
CPU time 2270.59 seconds
Started Dec 24 02:06:53 PM PST 23
Finished Dec 24 02:44:48 PM PST 23
Peak memory 904656 kb
Host smart-729a06be-e779-43de-93bf-afdabdfac586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427558084 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.427558084
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.635123016
Short name T702
Test name
Test status
Simulation time 1454493107 ps
CPU time 18.36 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 244580 kb
Host smart-2d37db8f-a0b2-49b5-b417-b9033c71fecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635123016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.635123016
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.3933663790
Short name T419
Test name
Test status
Simulation time 86013227 ps
CPU time 3.09 seconds
Started Dec 24 02:08:25 PM PST 23
Finished Dec 24 02:08:39 PM PST 23
Peak memory 240524 kb
Host smart-3f2aae09-b714-4800-9cab-5b3acd5aa4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933663790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3933663790
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.3066663635
Short name T462
Test name
Test status
Simulation time 2706798463 ps
CPU time 6.05 seconds
Started Dec 24 02:08:25 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 243600 kb
Host smart-d0d8f479-e64d-42a4-a2ca-7732eae3c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066663635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.3066663635
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.2344174015
Short name T791
Test name
Test status
Simulation time 322740440017 ps
CPU time 4803.04 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 03:28:30 PM PST 23
Peak memory 361644 kb
Host smart-1420f596-a70a-4632-a99c-8109af1d419e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344174015 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.2344174015
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.2852846612
Short name T764
Test name
Test status
Simulation time 138379724 ps
CPU time 3.97 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 238468 kb
Host smart-44a6315e-39d2-4b6e-b0bf-546801299cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852846612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2852846612
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.3605825752
Short name T521
Test name
Test status
Simulation time 130166487 ps
CPU time 3.61 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 241876 kb
Host smart-7cc0617e-7016-49aa-bef3-31153c49f9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605825752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3605825752
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3582490911
Short name T1294
Test name
Test status
Simulation time 3636993865904 ps
CPU time 6375.48 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 03:54:42 PM PST 23
Peak memory 1148584 kb
Host smart-80c8e470-083f-4ffe-aba8-078d614f6f4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582490911 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.3582490911
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.3720782404
Short name T1236
Test name
Test status
Simulation time 194687929 ps
CPU time 4.17 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 240476 kb
Host smart-054ecebb-49b4-46d7-8327-40873d033a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720782404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.3720782404
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.3454496890
Short name T432
Test name
Test status
Simulation time 1022574644 ps
CPU time 3.37 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:41 PM PST 23
Peak memory 241044 kb
Host smart-7c552785-1ef9-4bab-ad5f-1c3e131c7e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454496890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3454496890
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2874414271
Short name T256
Test name
Test status
Simulation time 836526307881 ps
CPU time 2492.53 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:50:13 PM PST 23
Peak memory 344316 kb
Host smart-35e398d1-4355-49d1-b5cc-a1a21f6e12f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874414271 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.2874414271
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.1804942286
Short name T684
Test name
Test status
Simulation time 434257864 ps
CPU time 3.61 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 240572 kb
Host smart-b1337351-4dd4-47b6-8254-7b62326bd2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804942286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1804942286
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.2318270786
Short name T447
Test name
Test status
Simulation time 241728313 ps
CPU time 5.55 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 238452 kb
Host smart-0c140355-0643-4c5c-91b2-0fdf5052a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318270786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.2318270786
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.79544496
Short name T930
Test name
Test status
Simulation time 994757079521 ps
CPU time 6269.64 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 03:53:18 PM PST 23
Peak memory 873684 kb
Host smart-d83c771d-f550-4f6e-966d-5f5a55b27de1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79544496 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.79544496
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.1486569130
Short name T1018
Test name
Test status
Simulation time 575049474 ps
CPU time 3.92 seconds
Started Dec 24 02:08:18 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 238360 kb
Host smart-2b219365-2d57-4251-a044-099fbd9f4b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486569130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1486569130
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1209048078
Short name T1024
Test name
Test status
Simulation time 353934148 ps
CPU time 3.96 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:42 PM PST 23
Peak memory 246588 kb
Host smart-b9359447-e72b-4ec4-8ce4-c6baf26accf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209048078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1209048078
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.1600515330
Short name T274
Test name
Test status
Simulation time 179316417334 ps
CPU time 2507.37 seconds
Started Dec 24 02:08:18 PM PST 23
Finished Dec 24 02:50:15 PM PST 23
Peak memory 309064 kb
Host smart-ca848535-2754-4f8d-a5af-c2fd05d4b6e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600515330 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.1600515330
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.138519961
Short name T1222
Test name
Test status
Simulation time 498198961 ps
CPU time 4.68 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:53 PM PST 23
Peak memory 240540 kb
Host smart-398a6daa-a694-44de-88fa-0be4c7388e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138519961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.138519961
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.1363670853
Short name T603
Test name
Test status
Simulation time 1302992764 ps
CPU time 3.43 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:50 PM PST 23
Peak memory 246656 kb
Host smart-4bdc8a79-d28a-48bb-a181-fe7eb687c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363670853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.1363670853
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.3065887714
Short name T195
Test name
Test status
Simulation time 398083138076 ps
CPU time 5933.29 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 03:47:18 PM PST 23
Peak memory 294460 kb
Host smart-c9156a26-a540-434f-8430-265ba73f76ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065887714 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.3065887714
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.2118994206
Short name T160
Test name
Test status
Simulation time 142332394 ps
CPU time 3.9 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 241416 kb
Host smart-7f855446-71ca-4ea3-bce0-22e05628a60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118994206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.2118994206
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.1662887666
Short name T863
Test name
Test status
Simulation time 163646055 ps
CPU time 3.35 seconds
Started Dec 24 02:08:42 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 238448 kb
Host smart-ea7e8394-9bc2-44c0-ad94-6a55180e8f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662887666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.1662887666
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1928325047
Short name T1180
Test name
Test status
Simulation time 114431991178 ps
CPU time 1844.21 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:39:28 PM PST 23
Peak memory 271552 kb
Host smart-cf39ceb1-5e29-4e70-aa91-0ffec9d4c216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928325047 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.1928325047
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.995640525
Short name T854
Test name
Test status
Simulation time 775265766 ps
CPU time 5.35 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 238616 kb
Host smart-a911108e-52d0-4c79-bdf8-626e2b2db1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995640525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.995640525
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.143286577
Short name T425
Test name
Test status
Simulation time 188665714 ps
CPU time 3.66 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 238412 kb
Host smart-371c3632-7c30-45c9-9da4-b2df9de408e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143286577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.143286577
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.1497698257
Short name T273
Test name
Test status
Simulation time 320026996647 ps
CPU time 3649.66 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 03:09:36 PM PST 23
Peak memory 836844 kb
Host smart-ddc4c5ec-636c-432b-ade1-bb5f39c377a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497698257 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.1497698257
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.3260178312
Short name T1079
Test name
Test status
Simulation time 183290824 ps
CPU time 4.63 seconds
Started Dec 24 02:08:36 PM PST 23
Finished Dec 24 02:08:56 PM PST 23
Peak memory 240904 kb
Host smart-40c77871-4216-4105-821f-dbc76f893ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260178312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3260178312
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.1154891702
Short name T443
Test name
Test status
Simulation time 1387907466 ps
CPU time 11.56 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:58 PM PST 23
Peak memory 238508 kb
Host smart-86d42461-b37d-448a-a516-7380d3332d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154891702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1154891702
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.3647717040
Short name T1027
Test name
Test status
Simulation time 681004139300 ps
CPU time 4543.43 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 03:24:38 PM PST 23
Peak memory 315720 kb
Host smart-9c4d6509-a6b7-472d-ae9a-12fd1f49bf8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647717040 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.3647717040
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.958605976
Short name T1009
Test name
Test status
Simulation time 2635028721 ps
CPU time 8.27 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:56 PM PST 23
Peak memory 238588 kb
Host smart-fc43ebfe-74c8-4763-b387-0d5403dbf351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958605976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.958605976
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.2196263756
Short name T533
Test name
Test status
Simulation time 203056438 ps
CPU time 2.65 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 238444 kb
Host smart-b87e1c04-2ac8-4963-8507-985154a58625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196263756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2196263756
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.1308155166
Short name T1182
Test name
Test status
Simulation time 115517598 ps
CPU time 1.8 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:06:59 PM PST 23
Peak memory 238572 kb
Host smart-6e8daec7-d146-4b05-8ce8-c58bf06dff78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308155166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1308155166
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.3716399198
Short name T744
Test name
Test status
Simulation time 1460015074 ps
CPU time 9.89 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:09 PM PST 23
Peak memory 238652 kb
Host smart-4f004d1f-89b8-4cd1-8d79-6a3124e25998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716399198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3716399198
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.2053859461
Short name T810
Test name
Test status
Simulation time 1122407116 ps
CPU time 9.1 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:10 PM PST 23
Peak memory 246760 kb
Host smart-88f2885c-2b82-4a0e-ba74-8ea968dcc1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053859461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2053859461
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.1945975519
Short name T1064
Test name
Test status
Simulation time 8655497014 ps
CPU time 19.03 seconds
Started Dec 24 02:06:42 PM PST 23
Finished Dec 24 02:07:02 PM PST 23
Peak memory 242628 kb
Host smart-e0aa0811-f643-45ee-922b-0ffeb462e102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945975519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.1945975519
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.1113036843
Short name T852
Test name
Test status
Simulation time 3922923222 ps
CPU time 22.46 seconds
Started Dec 24 02:06:53 PM PST 23
Finished Dec 24 02:07:19 PM PST 23
Peak memory 244456 kb
Host smart-ef3ee527-3bce-49e1-9f9b-29b7aa5c76e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113036843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1113036843
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.573377552
Short name T1183
Test name
Test status
Simulation time 638990486 ps
CPU time 3.85 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:06:54 PM PST 23
Peak memory 238520 kb
Host smart-5d6950ef-e011-4a5a-839f-2a2c8f8a0015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573377552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.573377552
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.2505008587
Short name T1097
Test name
Test status
Simulation time 2443088134 ps
CPU time 18.24 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:07:04 PM PST 23
Peak memory 238760 kb
Host smart-be79d657-bdec-4fb4-bed9-a39b659ea6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505008587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2505008587
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.2332618920
Short name T1271
Test name
Test status
Simulation time 7643664028 ps
CPU time 13.55 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:15 PM PST 23
Peak memory 245632 kb
Host smart-3785d24c-6218-4b87-a657-b62f535d4193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332618920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2332618920
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.4215805030
Short name T275
Test name
Test status
Simulation time 172292920 ps
CPU time 4.74 seconds
Started Dec 24 02:06:53 PM PST 23
Finished Dec 24 02:07:01 PM PST 23
Peak memory 242204 kb
Host smart-82377542-6631-43b9-b221-58870b477189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215805030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.4215805030
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.2128017668
Short name T157
Test name
Test status
Simulation time 3732562827 ps
CPU time 6.85 seconds
Started Dec 24 02:06:49 PM PST 23
Finished Dec 24 02:07:02 PM PST 23
Peak memory 238564 kb
Host smart-e87963e5-3ff1-45c2-8907-10d873aded0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128017668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2128017668
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.1833898002
Short name T569
Test name
Test status
Simulation time 831916103 ps
CPU time 6.01 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 243512 kb
Host smart-272b039e-8082-45b4-ade8-f8d8860ff604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833898002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.1833898002
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.679538323
Short name T635
Test name
Test status
Simulation time 330485765 ps
CPU time 6.01 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:06:52 PM PST 23
Peak memory 238544 kb
Host smart-282d0a0f-b520-4d80-84dd-837f7b282e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679538323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.679538323
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.4260061038
Short name T1275
Test name
Test status
Simulation time 2647554029 ps
CPU time 19.57 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:19 PM PST 23
Peak memory 245660 kb
Host smart-d8d994f4-73c6-4889-bd9e-deeae5eaac76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260061038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
4260061038
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.2517383521
Short name T1207
Test name
Test status
Simulation time 765894636577 ps
CPU time 7629.31 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 04:14:02 PM PST 23
Peak memory 955640 kb
Host smart-8a337107-2b72-4c26-a2a2-734b4f4f3bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517383521 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.2517383521
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.1913268688
Short name T1178
Test name
Test status
Simulation time 1447478374 ps
CPU time 10.08 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:11 PM PST 23
Peak memory 243336 kb
Host smart-d224e538-78e5-4bdd-ad1f-e9effafe25b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913268688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.1913268688
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.2273428374
Short name T664
Test name
Test status
Simulation time 2620447101 ps
CPU time 6.16 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 238696 kb
Host smart-bae5d965-8f57-4d52-bea9-f0c2ca54d098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273428374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.2273428374
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.588615163
Short name T86
Test name
Test status
Simulation time 185332988 ps
CPU time 4.56 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 242444 kb
Host smart-c4d65a54-67c5-4091-b371-8954ea41bd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588615163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.588615163
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.382976351
Short name T663
Test name
Test status
Simulation time 302261042037 ps
CPU time 2738.32 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:54:26 PM PST 23
Peak memory 609488 kb
Host smart-732f6e2c-75f5-4c51-925d-87c1d0332a13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382976351 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.382976351
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.401588369
Short name T1254
Test name
Test status
Simulation time 114521521 ps
CPU time 3.49 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 02:08:50 PM PST 23
Peak memory 240556 kb
Host smart-2eb17b63-2706-4b03-bd4c-20055346019c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401588369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.401588369
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.3817367512
Short name T524
Test name
Test status
Simulation time 2915613164 ps
CPU time 5.41 seconds
Started Dec 24 02:08:32 PM PST 23
Finished Dec 24 02:08:52 PM PST 23
Peak memory 243324 kb
Host smart-c7eb688e-131e-4b7e-83ef-4d3058a1bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817367512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.3817367512
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.3409395898
Short name T527
Test name
Test status
Simulation time 4217030078394 ps
CPU time 5786.76 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 03:45:23 PM PST 23
Peak memory 288352 kb
Host smart-3e18bb6b-a0ea-413c-8ab5-76e265938bf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409395898 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.3409395898
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.2949707704
Short name T674
Test name
Test status
Simulation time 1089604900 ps
CPU time 3.27 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 02:08:50 PM PST 23
Peak memory 238412 kb
Host smart-49aba4ee-f7a7-430b-9c89-c2cadb6a1fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949707704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.2949707704
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.801714949
Short name T1128
Test name
Test status
Simulation time 518712011266 ps
CPU time 3412.67 seconds
Started Dec 24 02:08:47 PM PST 23
Finished Dec 24 03:05:53 PM PST 23
Peak memory 371884 kb
Host smart-2080e295-773a-4bad-8a34-6999bd993cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801714949 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.801714949
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.1266936432
Short name T1247
Test name
Test status
Simulation time 2642688927 ps
CPU time 7.35 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:05 PM PST 23
Peak memory 238648 kb
Host smart-09bef24e-1561-4445-acad-64c42ba5ff73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266936432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1266936432
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.2553459377
Short name T819
Test name
Test status
Simulation time 246782858 ps
CPU time 4.52 seconds
Started Dec 24 02:08:41 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 246680 kb
Host smart-779d7508-b661-460b-9531-f3cf59d923a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553459377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2553459377
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.4245149115
Short name T729
Test name
Test status
Simulation time 1470108363 ps
CPU time 4.94 seconds
Started Dec 24 02:08:42 PM PST 23
Finished Dec 24 02:09:01 PM PST 23
Peak memory 246692 kb
Host smart-110268f4-496a-4ef7-b6a4-842b076a6812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245149115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.4245149115
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.3921826004
Short name T1215
Test name
Test status
Simulation time 2580853242 ps
CPU time 7.14 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 02:09:00 PM PST 23
Peak memory 238392 kb
Host smart-4005c6c2-1247-412a-8035-2b043e7b66e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921826004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3921826004
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.2981710735
Short name T777
Test name
Test status
Simulation time 2124188535721 ps
CPU time 5507.68 seconds
Started Dec 24 02:08:57 PM PST 23
Finished Dec 24 03:40:55 PM PST 23
Peak memory 722292 kb
Host smart-65141684-2801-4dff-8a4e-d5d93d565d51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981710735 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.2981710735
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3299945898
Short name T49
Test name
Test status
Simulation time 127536723 ps
CPU time 3.19 seconds
Started Dec 24 02:08:56 PM PST 23
Finished Dec 24 02:09:10 PM PST 23
Peak memory 238508 kb
Host smart-7df40a6e-6b27-47e7-9d93-c65b8c1802c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299945898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3299945898
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.342823181
Short name T590
Test name
Test status
Simulation time 190738889 ps
CPU time 4.11 seconds
Started Dec 24 02:08:48 PM PST 23
Finished Dec 24 02:09:04 PM PST 23
Peak memory 238456 kb
Host smart-628060d9-4730-4f54-9983-5941848729c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342823181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.342823181
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.2658634846
Short name T1130
Test name
Test status
Simulation time 3422504551734 ps
CPU time 8287.71 seconds
Started Dec 24 02:08:37 PM PST 23
Finished Dec 24 04:27:01 PM PST 23
Peak memory 277320 kb
Host smart-e5b79414-6589-4972-a4d7-3cf04772cae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658634846 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.2658634846
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.2250680646
Short name T721
Test name
Test status
Simulation time 326661324 ps
CPU time 2.9 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 240816 kb
Host smart-4279bb10-2108-4162-b25c-f1bfab188cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250680646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2250680646
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.1251671479
Short name T655
Test name
Test status
Simulation time 470255840 ps
CPU time 3.31 seconds
Started Dec 24 02:08:39 PM PST 23
Finished Dec 24 02:08:57 PM PST 23
Peak memory 242340 kb
Host smart-605f77fa-ee70-4152-b1c3-c97b1ca7d611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251671479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1251671479
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2971357077
Short name T1057
Test name
Test status
Simulation time 4027912715220 ps
CPU time 5456.49 seconds
Started Dec 24 02:08:49 PM PST 23
Finished Dec 24 03:39:59 PM PST 23
Peak memory 275704 kb
Host smart-ee670de9-e337-45a4-b18e-39833ab99080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971357077 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.2971357077
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.3939081555
Short name T1223
Test name
Test status
Simulation time 737620336 ps
CPU time 5.59 seconds
Started Dec 24 02:08:38 PM PST 23
Finished Dec 24 02:08:59 PM PST 23
Peak memory 238528 kb
Host smart-0e76f74b-2adf-4526-a904-ea81215fa6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939081555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3939081555
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.3652616985
Short name T894
Test name
Test status
Simulation time 147320209 ps
CPU time 3.59 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:28 PM PST 23
Peak memory 242024 kb
Host smart-54a9497b-298b-4ba1-a4f0-ebd61b153ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652616985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3652616985
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.3253843959
Short name T1119
Test name
Test status
Simulation time 1130900329759 ps
CPU time 6376.17 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 03:54:55 PM PST 23
Peak memory 931496 kb
Host smart-c97133b4-73bd-42c9-89c9-787aa1a5e02d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253843959 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.3253843959
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.503734700
Short name T60
Test name
Test status
Simulation time 661178758 ps
CPU time 4.35 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 240500 kb
Host smart-d80b39f7-d419-40f7-b91f-76ca543e8cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503734700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.503734700
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.2768596757
Short name T484
Test name
Test status
Simulation time 1301838048 ps
CPU time 2.35 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:08:28 PM PST 23
Peak memory 241064 kb
Host smart-75c9945a-a079-423f-a55d-2c3bf162841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768596757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.2768596757
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.445242298
Short name T1191
Test name
Test status
Simulation time 332585397 ps
CPU time 4.47 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 238468 kb
Host smart-c26cab9b-e000-4bfb-ba86-08998eebc19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445242298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.445242298
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.2576288944
Short name T467
Test name
Test status
Simulation time 743833319 ps
CPU time 8.45 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:35 PM PST 23
Peak memory 238424 kb
Host smart-494c8dd5-8077-4fab-badd-e3af291819a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576288944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.2576288944
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.3422899781
Short name T743
Test name
Test status
Simulation time 88388174842 ps
CPU time 1000.41 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 02:25:05 PM PST 23
Peak memory 272880 kb
Host smart-aab1c85c-1812-40f5-9af2-e303dd4f837a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422899781 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.3422899781
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.1715250747
Short name T456
Test name
Test status
Simulation time 56943349 ps
CPU time 1.69 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:06:45 PM PST 23
Peak memory 238220 kb
Host smart-aee5de33-6c2c-497c-9eda-a3ad06b31f7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715250747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1715250747
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.1760453373
Short name T1073
Test name
Test status
Simulation time 611823890 ps
CPU time 13.98 seconds
Started Dec 24 02:06:38 PM PST 23
Finished Dec 24 02:06:52 PM PST 23
Peak memory 238556 kb
Host smart-5f437569-5a13-4f2d-88a6-c3a07c272379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760453373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1760453373
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.2941197191
Short name T949
Test name
Test status
Simulation time 438885103 ps
CPU time 9.88 seconds
Started Dec 24 02:06:57 PM PST 23
Finished Dec 24 02:07:12 PM PST 23
Peak memory 238384 kb
Host smart-06120c9a-b9e7-4603-b673-e928c441bcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941197191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2941197191
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.1503554337
Short name T1166
Test name
Test status
Simulation time 403904677 ps
CPU time 7.93 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:06:56 PM PST 23
Peak memory 245808 kb
Host smart-e741b053-f305-4db4-baed-226df00ecc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503554337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1503554337
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.1271278051
Short name T107
Test name
Test status
Simulation time 181298047 ps
CPU time 3.89 seconds
Started Dec 24 02:06:44 PM PST 23
Finished Dec 24 02:06:50 PM PST 23
Peak memory 238528 kb
Host smart-a83c138e-5c49-4bd4-95b6-344c344b021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271278051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1271278051
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.2123933252
Short name T845
Test name
Test status
Simulation time 147526277 ps
CPU time 5.11 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:06 PM PST 23
Peak memory 238592 kb
Host smart-600b954b-98a2-4d8b-8b04-69fbd3321f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123933252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2123933252
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.999377537
Short name T1077
Test name
Test status
Simulation time 1318312832 ps
CPU time 5.16 seconds
Started Dec 24 02:06:42 PM PST 23
Finished Dec 24 02:06:48 PM PST 23
Peak memory 238432 kb
Host smart-b54c7e96-df52-4992-a28e-8214708793c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999377537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.999377537
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3748055836
Short name T719
Test name
Test status
Simulation time 535222760 ps
CPU time 12.51 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:07:03 PM PST 23
Peak memory 238504 kb
Host smart-6bec4c3f-d100-4a4a-bc9b-d93965b3f021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748055836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3748055836
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.529984908
Short name T1267
Test name
Test status
Simulation time 202090108 ps
CPU time 6.35 seconds
Started Dec 24 02:06:47 PM PST 23
Finished Dec 24 02:07:00 PM PST 23
Peak memory 238604 kb
Host smart-5f238127-8c17-4876-a1af-5588ff14c478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529984908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.529984908
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.1853212131
Short name T540
Test name
Test status
Simulation time 703251224 ps
CPU time 8.02 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:14 PM PST 23
Peak memory 244320 kb
Host smart-e83effc0-a871-41ec-9c6f-7bd9a4799555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853212131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1853212131
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.3463367330
Short name T206
Test name
Test status
Simulation time 234264712560 ps
CPU time 2735.76 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:52:21 PM PST 23
Peak memory 261876 kb
Host smart-a3289cbf-eee8-4f07-945b-37c7e86adedf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463367330 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.3463367330
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.445953648
Short name T802
Test name
Test status
Simulation time 1213197162 ps
CPU time 18.87 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 237700 kb
Host smart-60e9604a-2834-468c-a1fc-266d1af30f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445953648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.445953648
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.3876516188
Short name T588
Test name
Test status
Simulation time 1812054067 ps
CPU time 5.98 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 02:08:32 PM PST 23
Peak memory 240664 kb
Host smart-5104254a-bcc8-41b2-899e-4cf6f8b0369c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876516188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3876516188
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.4127936083
Short name T1202
Test name
Test status
Simulation time 266113914 ps
CPU time 3.48 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 241392 kb
Host smart-655c70a6-d53e-4db0-9a49-e46e081af198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127936083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.4127936083
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1808142164
Short name T986
Test name
Test status
Simulation time 490107359394 ps
CPU time 5366.84 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 03:38:06 PM PST 23
Peak memory 889844 kb
Host smart-abfba6e0-69ac-4468-b7bb-4197d9aa1f36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808142164 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.1808142164
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.885281985
Short name T508
Test name
Test status
Simulation time 119364965 ps
CPU time 3.44 seconds
Started Dec 24 02:08:25 PM PST 23
Finished Dec 24 02:08:40 PM PST 23
Peak memory 238344 kb
Host smart-2cbf9280-40ac-42f9-b397-80d0d10b52cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885281985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.885281985
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.3866549135
Short name T152
Test name
Test status
Simulation time 501554547 ps
CPU time 5.79 seconds
Started Dec 24 02:08:18 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 242856 kb
Host smart-5178d64e-36a4-4cde-bc96-d7ace5a62eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866549135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3866549135
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1254185489
Short name T1048
Test name
Test status
Simulation time 244499703698 ps
CPU time 1896.54 seconds
Started Dec 24 02:08:18 PM PST 23
Finished Dec 24 02:40:05 PM PST 23
Peak memory 257936 kb
Host smart-84b32b56-96c9-4383-b228-2e1a1f2921a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254185489 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1254185489
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.1929736072
Short name T985
Test name
Test status
Simulation time 2043748540 ps
CPU time 5.36 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 241164 kb
Host smart-230414ed-7e9e-49bd-a222-1ffae042f609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929736072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1929736072
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.675583204
Short name T550
Test name
Test status
Simulation time 133269861 ps
CPU time 5.23 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 238400 kb
Host smart-ee2dcd90-3d4c-4aec-9818-31b324b91f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675583204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.675583204
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.738634444
Short name T787
Test name
Test status
Simulation time 106149851 ps
CPU time 3.36 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:41 PM PST 23
Peak memory 238416 kb
Host smart-594c9df9-3f6d-453f-b1fb-0efb889ec598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738634444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.738634444
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.67317389
Short name T1127
Test name
Test status
Simulation time 188496093 ps
CPU time 4.16 seconds
Started Dec 24 02:08:20 PM PST 23
Finished Dec 24 02:08:33 PM PST 23
Peak memory 238340 kb
Host smart-844c36f7-d577-4c70-bd7b-f3c7aa20c509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67317389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.67317389
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.1919772386
Short name T1268
Test name
Test status
Simulation time 5093001590398 ps
CPU time 4576.01 seconds
Started Dec 24 02:08:33 PM PST 23
Finished Dec 24 03:25:04 PM PST 23
Peak memory 291028 kb
Host smart-c0fb34f7-dc4e-47b7-8c60-2ffd68e6c1dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919772386 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.1919772386
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.2300386726
Short name T1280
Test name
Test status
Simulation time 535133362 ps
CPU time 3.85 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:46 PM PST 23
Peak memory 240960 kb
Host smart-3e225b0d-9ef1-4ada-b168-0568f59e979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300386726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2300386726
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.2545591918
Short name T200
Test name
Test status
Simulation time 265141186 ps
CPU time 2.56 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 238284 kb
Host smart-f30e76bc-d006-4426-8f7b-c83ac378bd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545591918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2545591918
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1479974790
Short name T812
Test name
Test status
Simulation time 673685263293 ps
CPU time 2514.35 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:50:37 PM PST 23
Peak memory 388144 kb
Host smart-5a2b7020-2385-4583-b887-a76f0dfb210f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479974790 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.1479974790
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.3587357447
Short name T82
Test name
Test status
Simulation time 344517571 ps
CPU time 4.95 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 238388 kb
Host smart-d528623f-f8cd-4fc3-ad4a-a13ef56f7307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587357447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.3587357447
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.3566197738
Short name T586
Test name
Test status
Simulation time 829229810 ps
CPU time 5.9 seconds
Started Dec 24 02:08:43 PM PST 23
Finished Dec 24 02:09:03 PM PST 23
Peak memory 238436 kb
Host smart-aef2f681-1cad-44a4-81eb-1f12b3abe2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566197738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3566197738
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.1709305881
Short name T1032
Test name
Test status
Simulation time 392053045368 ps
CPU time 2870.07 seconds
Started Dec 24 02:08:14 PM PST 23
Finished Dec 24 02:56:16 PM PST 23
Peak memory 331548 kb
Host smart-579e3f1b-c349-434c-af4d-053697ec74b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709305881 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.1709305881
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.4232342741
Short name T1036
Test name
Test status
Simulation time 556013684 ps
CPU time 3.85 seconds
Started Dec 24 02:08:20 PM PST 23
Finished Dec 24 02:08:33 PM PST 23
Peak memory 241120 kb
Host smart-086400bc-5322-405b-b5d7-04fed6ca16d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232342741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.4232342741
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.2964950928
Short name T1052
Test name
Test status
Simulation time 314916041 ps
CPU time 3.62 seconds
Started Dec 24 02:08:24 PM PST 23
Finished Dec 24 02:08:39 PM PST 23
Peak memory 238396 kb
Host smart-bf7bc8f2-f88a-4c3e-a4b9-b16516deb6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964950928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2964950928
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.2056010475
Short name T1092
Test name
Test status
Simulation time 18270683116 ps
CPU time 240.91 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:12:39 PM PST 23
Peak memory 255200 kb
Host smart-74c37d1d-18c7-491a-bd85-105683c015c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056010475 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.2056010475
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.4290966640
Short name T805
Test name
Test status
Simulation time 160060158 ps
CPU time 3.89 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:08:38 PM PST 23
Peak memory 238468 kb
Host smart-c8d5be33-eb7e-452f-8362-b62ffaae0e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290966640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.4290966640
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.3331527484
Short name T837
Test name
Test status
Simulation time 458147159 ps
CPU time 6.62 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:48 PM PST 23
Peak memory 238448 kb
Host smart-55ffa263-ff8a-4638-bdd0-9647c017d848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331527484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3331527484
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.2577757002
Short name T1220
Test name
Test status
Simulation time 44829030277 ps
CPU time 465.76 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:16:24 PM PST 23
Peak memory 246876 kb
Host smart-b8a396e0-e59e-45c0-9241-8ba1b2027ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577757002 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.2577757002
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.3125409732
Short name T1043
Test name
Test status
Simulation time 742670781 ps
CPU time 6.47 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:33 PM PST 23
Peak memory 238472 kb
Host smart-2717194b-be44-4b71-965d-0b061b6ca32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125409732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.3125409732
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.2907079615
Short name T710
Test name
Test status
Simulation time 128556486301 ps
CPU time 1755.36 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:37:50 PM PST 23
Peak memory 625204 kb
Host smart-78527e6e-43de-4011-9c30-8e0cefed77a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907079615 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.2907079615
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.1855641933
Short name T145
Test name
Test status
Simulation time 128498003 ps
CPU time 4.21 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 02:08:29 PM PST 23
Peak memory 238504 kb
Host smart-7f756e6c-2930-45ff-9787-8d2c5b3021f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855641933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1855641933
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1866499350
Short name T326
Test name
Test status
Simulation time 102103368 ps
CPU time 3.82 seconds
Started Dec 24 02:08:30 PM PST 23
Finished Dec 24 02:08:47 PM PST 23
Peak memory 238504 kb
Host smart-87c863e4-5757-4967-9149-92de23220284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866499350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1866499350
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.282352877
Short name T1016
Test name
Test status
Simulation time 125484079712 ps
CPU time 1659.75 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 02:36:03 PM PST 23
Peak memory 280104 kb
Host smart-a2599bed-ed52-4f14-93c5-3c9484ac622f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282352877 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.282352877
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.1571560814
Short name T1176
Test name
Test status
Simulation time 88697522 ps
CPU time 1.64 seconds
Started Dec 24 02:06:42 PM PST 23
Finished Dec 24 02:06:45 PM PST 23
Peak memory 238252 kb
Host smart-5dee31fb-78f2-40b3-a47d-5c64366c28f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571560814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.1571560814
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.1615580435
Short name T1120
Test name
Test status
Simulation time 4400390439 ps
CPU time 10.58 seconds
Started Dec 24 02:06:47 PM PST 23
Finished Dec 24 02:07:04 PM PST 23
Peak memory 238740 kb
Host smart-2c190a4c-3b94-48c6-a460-e6a68f0e899e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615580435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1615580435
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.1226677253
Short name T797
Test name
Test status
Simulation time 509979080 ps
CPU time 2.78 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:06:53 PM PST 23
Peak memory 238436 kb
Host smart-9b80510a-df0c-4d93-b18b-4bf9e0363341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226677253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1226677253
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.2885122444
Short name T691
Test name
Test status
Simulation time 289212546 ps
CPU time 5.89 seconds
Started Dec 24 02:06:45 PM PST 23
Finished Dec 24 02:06:57 PM PST 23
Peak memory 243012 kb
Host smart-bc579d9a-a5e5-4c03-b83d-036ebcd1a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885122444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2885122444
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.2464921417
Short name T173
Test name
Test status
Simulation time 268409102 ps
CPU time 3.72 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:07 PM PST 23
Peak memory 238556 kb
Host smart-83460026-51d5-4dfc-a267-b397f46bc88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464921417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2464921417
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.1589458256
Short name T944
Test name
Test status
Simulation time 114086555 ps
CPU time 3.11 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:07:01 PM PST 23
Peak memory 246608 kb
Host smart-c4cf42dd-47cb-426f-9233-f2e6df371b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589458256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1589458256
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.589842616
Short name T279
Test name
Test status
Simulation time 3522025946 ps
CPU time 24.85 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:29 PM PST 23
Peak memory 238752 kb
Host smart-81b4cb55-b559-4c57-a9bc-0359881f9c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589842616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.589842616
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.2227399575
Short name T217
Test name
Test status
Simulation time 3522068579 ps
CPU time 9.33 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:13 PM PST 23
Peak memory 246516 kb
Host smart-87845540-a3ae-4d6a-ab04-ccb84175b4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227399575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2227399575
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.2617476697
Short name T436
Test name
Test status
Simulation time 107296375 ps
CPU time 2.92 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:02 PM PST 23
Peak memory 238384 kb
Host smart-75687ded-e8a6-4337-87a4-c6e11de7767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617476697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2617476697
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.2043643174
Short name T1274
Test name
Test status
Simulation time 4124748779 ps
CPU time 11.21 seconds
Started Dec 24 02:06:58 PM PST 23
Finished Dec 24 02:07:15 PM PST 23
Peak memory 244340 kb
Host smart-6ec525c5-4c4b-47d0-8b69-fd0caa541b3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043643174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.2043643174
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.4179396016
Short name T319
Test name
Test status
Simulation time 410168855 ps
CPU time 9.44 seconds
Started Dec 24 02:06:55 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 237360 kb
Host smart-bd43efd9-178c-4815-9a13-bcb44e6b3c2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179396016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.4179396016
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.3436179182
Short name T1144
Test name
Test status
Simulation time 232118564 ps
CPU time 3.93 seconds
Started Dec 24 02:06:56 PM PST 23
Finished Dec 24 02:07:03 PM PST 23
Peak memory 238488 kb
Host smart-5b9a9373-d8b2-4fd5-9f19-8edb676dd71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436179182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3436179182
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.438796434
Short name T584
Test name
Test status
Simulation time 42504410644 ps
CPU time 102.15 seconds
Started Dec 24 02:06:43 PM PST 23
Finished Dec 24 02:08:26 PM PST 23
Peak memory 240776 kb
Host smart-9e04e1e6-c354-48ad-8176-461be24bb325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438796434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.438796434
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.694831197
Short name T850
Test name
Test status
Simulation time 281697776105 ps
CPU time 5851.17 seconds
Started Dec 24 02:06:46 PM PST 23
Finished Dec 24 03:44:27 PM PST 23
Peak memory 761392 kb
Host smart-7ac617dc-b3ba-414f-800a-a7cf46688f67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694831197 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.694831197
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.711987168
Short name T1129
Test name
Test status
Simulation time 317600693 ps
CPU time 7.06 seconds
Started Dec 24 02:06:54 PM PST 23
Finished Dec 24 02:07:05 PM PST 23
Peak memory 238520 kb
Host smart-d2c1bf32-5d45-41c9-9aa7-970976412893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711987168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.711987168
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.2763103936
Short name T687
Test name
Test status
Simulation time 128384803 ps
CPU time 3.44 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:41 PM PST 23
Peak memory 241280 kb
Host smart-08a7a99e-fca5-4f07-ab76-bc89221463cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763103936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2763103936
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.1218268203
Short name T604
Test name
Test status
Simulation time 1874115044 ps
CPU time 5.67 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 242088 kb
Host smart-44d24a1f-6d2a-4186-a58e-4e6b85228b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218268203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.1218268203
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2118463661
Short name T1289
Test name
Test status
Simulation time 121033017829 ps
CPU time 2311.79 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:47:11 PM PST 23
Peak memory 282968 kb
Host smart-72bb869b-dee8-4e9b-a8ce-4fe18657c6ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118463661 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.2118463661
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.2242378836
Short name T1006
Test name
Test status
Simulation time 107954328 ps
CPU time 3.68 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 238352 kb
Host smart-5f92ed25-c745-4252-ae35-5e15c98b697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242378836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2242378836
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.1737875314
Short name T1054
Test name
Test status
Simulation time 611875172 ps
CPU time 6.51 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:33 PM PST 23
Peak memory 246768 kb
Host smart-6ffd5e1d-9b07-427b-b0c8-4e20a598d553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737875314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1737875314
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.4098391888
Short name T13
Test name
Test status
Simulation time 262055391500 ps
CPU time 3865.85 seconds
Started Dec 24 02:08:25 PM PST 23
Finished Dec 24 03:13:03 PM PST 23
Peak memory 822604 kb
Host smart-0cd9bfee-727a-4558-82b4-013e52efed66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098391888 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.4098391888
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.3501802410
Short name T610
Test name
Test status
Simulation time 285576534 ps
CPU time 3.58 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 237692 kb
Host smart-8c89e41d-036e-4ec2-81b3-6db52bf69df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501802410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3501802410
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.1339878774
Short name T726
Test name
Test status
Simulation time 92759636 ps
CPU time 2.41 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:33 PM PST 23
Peak memory 238256 kb
Host smart-991ab240-d852-423a-9fbd-14d541e232bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339878774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.1339878774
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1928462404
Short name T1076
Test name
Test status
Simulation time 497916894980 ps
CPU time 3227.43 seconds
Started Dec 24 02:08:31 PM PST 23
Finished Dec 24 03:02:33 PM PST 23
Peak memory 338356 kb
Host smart-12f20fe5-4037-4f84-80de-918ea20b132e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928462404 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.1928462404
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.784840132
Short name T139
Test name
Test status
Simulation time 327202377 ps
CPU time 3.39 seconds
Started Dec 24 02:08:15 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 238392 kb
Host smart-0c79788c-0742-4a57-a9d0-e867dcb30fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784840132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.784840132
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.402415389
Short name T504
Test name
Test status
Simulation time 2798505509 ps
CPU time 5.76 seconds
Started Dec 24 02:08:26 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 242860 kb
Host smart-d2408998-89d9-4de6-868f-873b8f9069de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402415389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.402415389
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1853745040
Short name T775
Test name
Test status
Simulation time 512718718298 ps
CPU time 6661.01 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 03:59:26 PM PST 23
Peak memory 288920 kb
Host smart-64cd1a7c-8b58-4391-8901-ee5e977c6d6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853745040 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1853745040
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.453079780
Short name T1095
Test name
Test status
Simulation time 412260235 ps
CPU time 3.38 seconds
Started Dec 24 02:08:23 PM PST 23
Finished Dec 24 02:08:38 PM PST 23
Peak memory 246608 kb
Host smart-61c8c173-445d-45a1-9447-e8c722e4c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453079780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.453079780
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.217548120
Short name T422
Test name
Test status
Simulation time 531808309 ps
CPU time 6.24 seconds
Started Dec 24 02:08:17 PM PST 23
Finished Dec 24 02:08:33 PM PST 23
Peak memory 242944 kb
Host smart-401f7995-aaf6-4ad7-ab9f-bb84edaae40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217548120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.217548120
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2314785463
Short name T336
Test name
Test status
Simulation time 772590197127 ps
CPU time 6630.34 seconds
Started Dec 24 02:08:13 PM PST 23
Finished Dec 24 03:58:55 PM PST 23
Peak memory 882084 kb
Host smart-e7e0b2a0-f7e4-46b9-8326-ddf4e0add850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314785463 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2314785463
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.2040479875
Short name T56
Test name
Test status
Simulation time 130814402 ps
CPU time 4.47 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 238408 kb
Host smart-cac42dc9-f0e3-4e40-b177-0b1ad14f0403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040479875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.2040479875
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.3519286628
Short name T534
Test name
Test status
Simulation time 221541723 ps
CPU time 3.23 seconds
Started Dec 24 02:08:28 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 242436 kb
Host smart-3b5d2deb-4c78-4e55-84f3-b6fb67fdd943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519286628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.3519286628
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.3339965469
Short name T334
Test name
Test status
Simulation time 584063163147 ps
CPU time 4027.67 seconds
Started Dec 24 02:08:11 PM PST 23
Finished Dec 24 03:15:30 PM PST 23
Peak memory 725296 kb
Host smart-5c19f58e-e138-4c04-a2c3-48201ac3266b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339965469 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.3339965469
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.3006543955
Short name T1251
Test name
Test status
Simulation time 609591296 ps
CPU time 3.71 seconds
Started Dec 24 02:08:22 PM PST 23
Finished Dec 24 02:08:37 PM PST 23
Peak memory 238420 kb
Host smart-11f5024c-b511-4d58-b2bc-f71aa41753cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006543955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.3006543955
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.604296654
Short name T520
Test name
Test status
Simulation time 1662083709 ps
CPU time 4.56 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 238444 kb
Host smart-7b7b009d-d6be-4558-aaec-77578afb24ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604296654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.604296654
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.400711292
Short name T215
Test name
Test status
Simulation time 1994752953666 ps
CPU time 5291.74 seconds
Started Dec 24 02:08:24 PM PST 23
Finished Dec 24 03:36:47 PM PST 23
Peak memory 1004924 kb
Host smart-ffe49f6e-d449-4932-a054-3c96cac8b1eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400711292 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.400711292
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2799935411
Short name T650
Test name
Test status
Simulation time 189557800 ps
CPU time 4.02 seconds
Started Dec 24 02:08:17 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 238532 kb
Host smart-fbcd40b6-020b-4599-a437-63668ce08b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799935411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2799935411
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.2346842558
Short name T1137
Test name
Test status
Simulation time 2088000561 ps
CPU time 6.25 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 02:08:44 PM PST 23
Peak memory 238400 kb
Host smart-00c04a1d-a93b-49bc-bf72-83909c6391fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346842558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2346842558
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3418225073
Short name T1063
Test name
Test status
Simulation time 1914319633517 ps
CPU time 8989.9 seconds
Started Dec 24 02:08:27 PM PST 23
Finished Dec 24 04:38:29 PM PST 23
Peak memory 1419728 kb
Host smart-5c314f1d-f203-42f7-832f-c8d3955ef29d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418225073 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.3418225073
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.2438339149
Short name T648
Test name
Test status
Simulation time 403190787 ps
CPU time 3.55 seconds
Started Dec 24 02:08:16 PM PST 23
Finished Dec 24 02:08:30 PM PST 23
Peak memory 246712 kb
Host smart-8c6cbebf-8c79-4def-a0e8-a27a45aeb8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438339149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.2438339149
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.4108127505
Short name T492
Test name
Test status
Simulation time 3842121651 ps
CPU time 8.61 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:50 PM PST 23
Peak memory 243712 kb
Host smart-c32059aa-34f5-440a-91c9-d54b61a20706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108127505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.4108127505
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1372198599
Short name T841
Test name
Test status
Simulation time 987876860847 ps
CPU time 4505.43 seconds
Started Dec 24 02:08:12 PM PST 23
Finished Dec 24 03:23:30 PM PST 23
Peak memory 351472 kb
Host smart-8ee3ba3a-9cb1-4ffb-895a-bb8ee23dd304
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372198599 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.1372198599
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.3212548891
Short name T497
Test name
Test status
Simulation time 2047511913 ps
CPU time 5.97 seconds
Started Dec 24 02:08:21 PM PST 23
Finished Dec 24 02:08:36 PM PST 23
Peak memory 241308 kb
Host smart-709e2bf1-4860-44e1-a1e5-0d16ddbac5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212548891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3212548891
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.355251171
Short name T156
Test name
Test status
Simulation time 2309090145 ps
CPU time 4.23 seconds
Started Dec 24 02:08:29 PM PST 23
Finished Dec 24 02:08:45 PM PST 23
Peak memory 238552 kb
Host smart-7c211700-efa0-47bb-81e0-cd8d7f4136fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355251171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.355251171
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest
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