Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	51	7	44	86.27

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	7	44	86.27	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	52924	1			T10	149		T95	93		T11	109
access_err	78530	1			T2	218		T3	99		T4	143
write_blank_err	494	1			T9	1		T88	8		T90	3
ecc_uncorr_err	77671	1			T9	434		T109	47		T88	1309
ecc_corr_err	1436	1			T10	47		T88	2		T68	48
no_err	380273	1			T2	496		T3	219		T4	302

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	42640	1			T2	96		T3	58		T4	58
secret2	70154	1			T2	50		T3	42		T4	48
secret1	86840	1			T2	62		T3	60		T4	42
secret0	121539	1			T2	74		T3	36		T4	32
hw_cfg	69237	1			T2	110		T3	16		T4	43
owner_sw_cfg	58913	1			T2	122		T3	32		T4	48
creator_sw_cfg	59136	1			T2	122		T3	40		T4	102
vendor_test	82869	1			T2	78		T3	34		T4	72

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	7	44	86.27	7
Automatically Generated Cross Bins	51	7	44	86.27	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	3066	1			T95	93		T31	120		T308	5
fsm_err	secret2	6811	1			T165	490		T156	167		T309	25
fsm_err	secret1	6164	1			T115	311		T112	128		T259	299
fsm_err	secret0	4847	1			T11	109		T112	276		T310	312
fsm_err	hw_cfg	6751	1			T311	472		T32	265		T312	38
fsm_err	owner_sw_cfg	2460	1			T121	110		T313	214		T314	352
fsm_err	creator_sw_cfg	2933	1			T315	309		T316	69		T32	195
fsm_err	vendor_test	19892	1			T10	149		T158	8		T159	486
access_err	lc_or_oob	18249	1			T2	48		T3	29		T4	29
access_err	secret2	12664	1			T2	19		T3	18		T4	17
access_err	secret1	7200	1			T3	21		T4	19		T6	46
access_err	secret0	5520	1			T2	12		T3	11		T4	4
access_err	hw_cfg	3257	1			T2	19		T3	6		T4	9
access_err	owner_sw_cfg	11816	1			T2	54		T3	3		T4	16
access_err	creator_sw_cfg	12246	1			T2	47		T3	8		T4	35
access_err	vendor_test	7578	1			T2	19		T3	3		T4	14
write_blank_err	secret2	23	1			T90	1		T82	2		T317	1
write_blank_err	secret1	47	1			T9	1		T88	1		T114	1
write_blank_err	secret0	89	1			T88	3		T90	1		T113	1
write_blank_err	hw_cfg	24	1			T82	2		T259	1		T143	1
write_blank_err	owner_sw_cfg	112	1			T88	2		T90	1		T114	3
write_blank_err	creator_sw_cfg	164	1			T88	1		T82	10		T259	1
write_blank_err	vendor_test	35	1			T88	1		T114	2		T82	4
ecc_uncorr_err	secret2	8263	1			T90	545		T82	503		T317	138
ecc_uncorr_err	secret1	18045	1			T9	434		T110	121		T114	406
ecc_uncorr_err	secret0	39018	1			T88	1309		T110	174		T90	320
ecc_uncorr_err	hw_cfg	8456	1			T110	121		T82	552		T259	568
ecc_uncorr_err	owner_sw_cfg	1875	1			T83	3		T305	4		T121	53
ecc_uncorr_err	creator_sw_cfg	2014	1			T109	47		T110	126		T111	34
ecc_corr_err	secret2	127	1			T10	26		T68	7		T83	1
ecc_corr_err	secret1	163	1			T10	4		T88	1		T68	2
ecc_corr_err	secret0	193	1			T10	5		T34	1		T305	1
ecc_corr_err	hw_cfg	311	1			T10	6		T68	17		T82	3
ecc_corr_err	owner_sw_cfg	202	1			T10	1		T68	4		T110	1
ecc_corr_err	creator_sw_cfg	177	1			T10	1		T68	16		T110	5
ecc_corr_err	vendor_test	263	1			T10	4		T88	1		T68	2
no_err	lc_or_oob	21325	1			T2	48		T3	29		T4	29
no_err	secret2	42266	1			T2	31		T3	24		T4	31
no_err	secret1	55221	1			T2	62		T3	39		T4	23
no_err	secret0	71872	1			T2	62		T3	25		T4	28
no_err	hw_cfg	50438	1			T2	91		T3	10		T4	34
no_err	owner_sw_cfg	42448	1			T2	68		T3	29		T4	32
no_err	creator_sw_cfg	41602	1			T2	75		T3	32		T4	67
no_err	vendor_test	55101	1			T2	59		T3	31		T4	58

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded