Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.37 92.57 90.98 92.29 92.68 93.28 96.53 95.27


Total tests in report: 1332
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
42.88 42.88 67.48 67.48 55.62 55.62 49.12 49.12 0.00 0.00 63.32 63.32 44.80 44.80 19.83 19.83 /workspace/coverage/default/14.otp_ctrl_check_fail.979876084
76.15 33.27 89.21 21.73 78.69 23.07 62.36 13.24 92.68 92.68 85.19 21.87 89.89 45.10 35.02 15.19 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2162462567
80.01 3.86 89.53 0.32 80.43 1.74 76.91 14.55 92.68 0.00 86.47 1.28 90.27 0.38 43.80 8.78 /workspace/coverage/default/20.otp_ctrl_stress_all.3871572250
82.98 2.97 89.53 0.00 80.43 0.00 76.91 0.00 92.68 0.00 86.47 0.00 90.57 0.30 64.30 20.51 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2521592993
84.78 1.80 89.53 0.00 80.65 0.22 83.07 6.16 92.68 0.00 86.52 0.05 90.65 0.08 70.38 6.08 /workspace/coverage/default/46.otp_ctrl_stress_all.1952568569
86.25 1.47 89.91 0.38 83.71 3.07 83.22 0.15 92.68 0.00 86.95 0.43 91.33 0.68 75.95 5.57 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1525186968
87.48 1.23 90.46 0.55 86.07 2.36 83.92 0.70 92.68 0.00 88.88 1.93 91.86 0.53 78.48 2.53 /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.3729228180
88.39 0.91 90.52 0.06 86.62 0.54 88.05 4.12 92.68 0.00 89.14 0.27 92.08 0.23 79.66 1.18 /workspace/coverage/default/9.otp_ctrl_stress_all.4246816384
89.13 0.73 90.67 0.15 87.21 0.60 88.44 0.39 92.68 0.00 90.53 1.39 94.34 2.26 80.00 0.34 /workspace/coverage/default/3.otp_ctrl_sec_cm.1351262966
89.64 0.52 90.71 0.04 87.73 0.52 88.46 0.01 92.68 0.00 90.75 0.21 94.49 0.15 82.70 2.70 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.3435493946
90.04 0.40 90.78 0.08 87.95 0.22 88.56 0.10 92.68 0.00 90.91 0.16 94.87 0.38 84.56 1.86 /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.854209710
90.37 0.33 91.01 0.23 88.44 0.49 89.18 0.62 92.68 0.00 91.12 0.21 94.87 0.00 85.32 0.76 /workspace/coverage/default/24.otp_ctrl_test_access.1091106550
90.59 0.22 91.01 0.00 88.46 0.03 89.18 0.00 92.68 0.00 91.12 0.00 95.10 0.23 86.58 1.27 /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.219526885
90.77 0.18 91.01 0.00 88.49 0.03 89.20 0.02 92.68 0.00 91.12 0.00 95.40 0.30 87.51 0.93 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2232268611
90.95 0.17 91.18 0.17 88.65 0.16 89.28 0.08 92.68 0.00 91.44 0.32 95.63 0.23 87.76 0.25 /workspace/coverage/default/284.otp_ctrl_init_fail.2392525208
91.12 0.17 91.18 0.00 88.65 0.00 89.89 0.61 92.68 0.00 91.44 0.00 95.63 0.00 88.35 0.59 /workspace/coverage/default/30.otp_ctrl_stress_all.4066253462
91.27 0.15 91.31 0.13 89.01 0.35 89.90 0.01 92.68 0.00 91.60 0.16 95.70 0.08 88.69 0.34 /workspace/coverage/default/25.otp_ctrl_check_fail.53898703
91.42 0.15 91.31 0.00 89.01 0.00 90.42 0.52 92.68 0.00 91.60 0.00 95.70 0.00 89.20 0.51 /workspace/coverage/default/38.otp_ctrl_regwen.3028403929
91.55 0.13 91.41 0.09 89.22 0.22 90.72 0.31 92.68 0.00 91.82 0.21 95.70 0.00 89.28 0.08 /workspace/coverage/default/23.otp_ctrl_init_fail.190793334
91.67 0.12 91.52 0.11 89.28 0.05 90.72 0.00 92.68 0.00 91.93 0.11 95.85 0.15 89.70 0.42 /workspace/coverage/default/33.otp_ctrl_macro_errs.1038527538
91.79 0.12 91.52 0.00 89.28 0.00 90.72 0.00 92.68 0.00 91.93 0.00 96.00 0.15 90.38 0.68 /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.31937492
91.89 0.10 91.52 0.00 89.28 0.00 90.85 0.12 92.68 0.00 91.93 0.00 96.00 0.00 90.97 0.59 /workspace/coverage/default/11.otp_ctrl_stress_all.294415427
91.97 0.08 91.52 0.00 89.47 0.19 90.94 0.10 92.68 0.00 91.93 0.00 96.30 0.30 90.97 0.00 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.474808252
92.05 0.08 91.52 0.00 89.47 0.00 91.18 0.23 92.68 0.00 91.93 0.00 96.30 0.00 91.31 0.34 /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3147321863
92.13 0.07 91.52 0.00 89.47 0.00 91.18 0.00 92.68 0.00 91.93 0.00 96.30 0.00 91.81 0.51 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1677920921
92.20 0.07 91.63 0.11 89.55 0.08 91.18 0.01 92.68 0.00 92.14 0.21 96.30 0.00 91.90 0.08 /workspace/coverage/default/272.otp_ctrl_init_fail.3128757958
92.27 0.07 91.97 0.34 89.55 0.00 91.18 0.00 92.68 0.00 92.14 0.00 96.46 0.15 91.90 0.00 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3660506544
92.33 0.07 92.03 0.06 89.63 0.08 91.32 0.13 92.68 0.00 92.25 0.11 96.46 0.00 91.98 0.08 /workspace/coverage/default/87.otp_ctrl_init_fail.2082775665
92.40 0.06 92.07 0.04 89.69 0.05 91.32 0.00 92.68 0.00 92.35 0.11 96.46 0.00 92.24 0.25 /workspace/coverage/default/26.otp_ctrl_check_fail.3416278958
92.46 0.06 92.07 0.00 89.77 0.08 91.32 0.00 92.68 0.00 92.35 0.00 96.46 0.00 92.57 0.34 /workspace/coverage/default/35.otp_ctrl_stress_all.542985488
92.51 0.06 92.07 0.00 89.77 0.00 91.37 0.06 92.68 0.00 92.35 0.00 96.46 0.00 92.91 0.34 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2545946102
92.57 0.06 92.07 0.00 89.82 0.05 91.37 0.00 92.68 0.00 92.35 0.00 96.46 0.00 93.25 0.34 /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2714684421
92.62 0.05 92.14 0.08 89.88 0.05 91.37 0.00 92.68 0.00 92.46 0.11 96.46 0.00 93.33 0.08 /workspace/coverage/default/28.otp_ctrl_check_fail.2226940628
92.66 0.05 92.20 0.06 89.93 0.05 91.39 0.02 92.68 0.00 92.57 0.11 96.46 0.00 93.42 0.08 /workspace/coverage/default/286.otp_ctrl_init_fail.4030865
92.70 0.04 92.26 0.06 89.96 0.03 91.46 0.07 92.68 0.00 92.62 0.05 96.46 0.00 93.50 0.08 /workspace/coverage/default/111.otp_ctrl_init_fail.284137704
92.74 0.04 92.26 0.00 90.23 0.27 91.47 0.01 92.68 0.00 92.62 0.00 96.46 0.00 93.50 0.00 /workspace/coverage/default/11.otp_ctrl_alert_test.2586369985
92.78 0.04 92.26 0.00 90.23 0.00 91.49 0.02 92.68 0.00 92.62 0.00 96.46 0.00 93.76 0.25 /workspace/coverage/default/33.otp_ctrl_stress_all.3348030948
92.82 0.04 92.31 0.06 90.26 0.03 91.52 0.03 92.68 0.00 92.67 0.05 96.46 0.00 93.84 0.08 /workspace/coverage/default/12.otp_ctrl_init_fail.1310071652
92.86 0.04 92.37 0.06 90.28 0.03 91.55 0.02 92.68 0.00 92.73 0.05 96.46 0.00 93.92 0.08 /workspace/coverage/default/262.otp_ctrl_init_fail.782352961
92.89 0.03 92.43 0.06 90.31 0.03 91.56 0.01 92.68 0.00 92.78 0.05 96.46 0.00 94.01 0.08 /workspace/coverage/default/241.otp_ctrl_init_fail.3523016110
92.92 0.03 92.49 0.06 90.36 0.05 91.60 0.04 92.68 0.00 92.83 0.05 96.46 0.00 94.01 0.00 /workspace/coverage/default/42.otp_ctrl_check_fail.3457210508
92.95 0.03 92.52 0.04 90.39 0.03 91.69 0.08 92.68 0.00 92.89 0.05 96.46 0.00 94.01 0.00 /workspace/coverage/default/17.otp_ctrl_init_fail.953773366
92.97 0.03 92.64 0.11 90.42 0.03 91.69 0.00 92.68 0.00 92.94 0.05 96.46 0.00 94.01 0.00 /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.646163714
93.00 0.03 92.64 0.00 90.53 0.11 91.69 0.00 92.68 0.00 92.94 0.00 96.46 0.00 94.09 0.08 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2397897420
93.03 0.03 92.66 0.02 90.55 0.03 91.69 0.00 92.68 0.00 92.99 0.05 96.46 0.00 94.18 0.08 /workspace/coverage/default/41.otp_ctrl_check_fail.2546228409
93.05 0.03 92.66 0.00 90.55 0.00 91.69 0.01 92.68 0.00 92.99 0.00 96.46 0.00 94.35 0.17 /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2646663892
93.08 0.02 92.66 0.00 90.55 0.00 91.69 0.00 92.68 0.00 92.99 0.00 96.46 0.00 94.51 0.17 /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.28674245
93.10 0.02 92.66 0.00 90.55 0.00 91.69 0.00 92.68 0.00 92.99 0.00 96.46 0.00 94.68 0.17 /workspace/coverage/default/2.otp_ctrl_stress_all.4267435947
93.13 0.02 92.71 0.06 90.61 0.05 91.69 0.00 92.68 0.00 93.05 0.05 96.46 0.00 94.68 0.00 /workspace/coverage/default/29.otp_ctrl_check_fail.3171148684
93.15 0.02 92.71 0.00 90.61 0.00 91.83 0.14 92.68 0.00 93.05 0.00 96.46 0.00 94.68 0.00 /workspace/coverage/default/22.otp_ctrl_init_fail.3764170223
93.16 0.02 92.75 0.04 90.64 0.03 91.85 0.01 92.68 0.00 93.10 0.05 96.46 0.00 94.68 0.00 /workspace/coverage/default/81.otp_ctrl_init_fail.3971636663
93.18 0.02 92.75 0.00 90.64 0.00 91.97 0.13 92.68 0.00 93.10 0.00 96.46 0.00 94.68 0.00 /workspace/coverage/default/260.otp_ctrl_init_fail.3297250265
93.20 0.02 92.79 0.04 90.66 0.03 91.98 0.01 92.68 0.00 93.16 0.05 96.46 0.00 94.68 0.00 /workspace/coverage/default/110.otp_ctrl_init_fail.2890380346
93.22 0.02 92.83 0.04 90.69 0.03 91.99 0.01 92.68 0.00 93.21 0.05 96.46 0.00 94.68 0.00 /workspace/coverage/default/135.otp_ctrl_init_fail.1405889355
93.24 0.02 92.84 0.02 90.72 0.03 91.99 0.00 92.68 0.00 93.21 0.00 96.53 0.08 94.68 0.00 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3073081187
93.25 0.02 92.84 0.00 90.74 0.03 91.99 0.00 92.68 0.00 93.21 0.00 96.53 0.00 94.77 0.08 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.478038881
93.27 0.01 92.86 0.02 90.74 0.00 91.99 0.00 92.68 0.00 93.21 0.00 96.53 0.00 94.85 0.08 /workspace/coverage/default/1.otp_ctrl_stress_all.3745778717
93.28 0.01 92.86 0.00 90.74 0.00 92.00 0.01 92.68 0.00 93.21 0.00 96.53 0.00 94.94 0.08 /workspace/coverage/default/25.otp_ctrl_regwen.2529865698
93.29 0.01 92.86 0.00 90.74 0.00 92.08 0.08 92.68 0.00 93.21 0.00 96.53 0.00 94.94 0.00 /workspace/coverage/default/157.otp_ctrl_init_fail.34146480
93.30 0.01 92.86 0.00 90.74 0.00 92.08 0.00 92.68 0.00 93.21 0.00 96.53 0.00 95.02 0.08 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.773143465
93.32 0.01 92.86 0.00 90.74 0.00 92.08 0.00 92.68 0.00 93.21 0.00 96.53 0.00 95.11 0.08 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.103077307
93.33 0.01 92.86 0.00 90.74 0.00 92.08 0.00 92.68 0.00 93.21 0.00 96.53 0.00 95.19 0.08 /workspace/coverage/default/10.otp_ctrl_regwen.3766492686
93.34 0.01 92.86 0.00 90.74 0.00 92.08 0.00 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.08 /workspace/coverage/default/29.otp_ctrl_regwen.2878994613
93.35 0.01 92.86 0.00 90.77 0.03 92.13 0.05 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/36.otp_ctrl_stress_all.3608718883
93.36 0.01 92.86 0.00 90.83 0.05 92.13 0.00 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/19.otp_ctrl_stress_all.3481157095
93.36 0.01 92.90 0.04 90.83 0.00 92.13 0.00 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/11.otp_ctrl_test_access.1939259090
93.37 0.01 92.90 0.00 90.83 0.00 92.16 0.03 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/32.otp_ctrl_init_fail.2870902427
93.37 0.01 92.90 0.00 90.83 0.00 92.19 0.03 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1277359303
93.38 0.01 92.90 0.00 90.85 0.03 92.19 0.00 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/13.otp_ctrl_stress_all.491171901
93.38 0.01 92.90 0.00 90.85 0.00 92.21 0.02 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/249.otp_ctrl_init_fail.1204294057
93.38 0.01 92.90 0.00 90.85 0.00 92.22 0.01 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/119.otp_ctrl_init_fail.1742863461
93.38 0.01 92.90 0.00 90.85 0.00 92.24 0.01 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/212.otp_ctrl_init_fail.3383824775
93.39 0.01 92.90 0.00 90.85 0.00 92.25 0.01 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/271.otp_ctrl_init_fail.346563844
93.39 0.01 92.90 0.00 90.85 0.00 92.27 0.01 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/291.otp_ctrl_init_fail.4118024157
93.39 0.01 92.90 0.00 90.85 0.00 92.28 0.01 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/60.otp_ctrl_init_fail.880280661
93.39 0.01 92.90 0.00 90.85 0.00 92.29 0.01 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/278.otp_ctrl_init_fail.4013649478
93.39 0.01 92.90 0.00 90.85 0.00 92.29 0.01 92.68 0.00 93.21 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/35.otp_ctrl_regwen.2713597677

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1027643454
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1033701552
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3249270972
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2528692152
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3952959615
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3268023396
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1926649748
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2017316224
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1081768476
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3288593799
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2224748131
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1418189830
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.77965515
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1462615304
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1514991567
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.618961386
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2054225106
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3600581775
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3007056655
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.561856480
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3109508954
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4193474414
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3097360290
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2261506553
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3702594295
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3460954917
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3682891038
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3555315302
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.587367414
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3934557628
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2781871006
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2351600442
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1864171453
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.113296884
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3538236895
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1516127642
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.722342378
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.4284613098
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2200720271
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1736310515
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.266024329
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.749620802
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1178486696
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3263309260
/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.593722057
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.844298074
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3517259587
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1029289513
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.41856426
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1867821358
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2907021830
/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.898215690
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.889131465
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1275951186
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2565729182
/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1774659135
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3756571243
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2310156116
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1746346899
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2120192351
/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2558967816
/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2700677765
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.810640259
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3608304553
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.468419019
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3545126561
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/workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2968271939
/workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.2698294103
/workspace/coverage/default/96.otp_ctrl_init_fail.2293933231
/workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.2971956551
/workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.1983199544
/workspace/coverage/default/97.otp_ctrl_init_fail.131999698
/workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.874272888
/workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1660204604
/workspace/coverage/default/98.otp_ctrl_init_fail.471869715
/workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.1164519935
/workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1484836429
/workspace/coverage/default/99.otp_ctrl_init_fail.3020549942
/workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.2458120437
/workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3622891653



Total test records in report: 1332
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T15 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2162462567 Dec 27 01:25:52 PM PST 23 Dec 27 01:26:16 PM PST 23 9346260010 ps
T101 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1253720853 Dec 27 01:26:59 PM PST 23 Dec 27 01:27:02 PM PST 23 149363883 ps
T102 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3702594295 Dec 27 01:26:20 PM PST 23 Dec 27 01:26:22 PM PST 23 86159375 ps
T173 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1525186968 Dec 27 01:26:33 PM PST 23 Dec 27 01:26:37 PM PST 23 53479459 ps
T105 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.320194315 Dec 27 01:26:59 PM PST 23 Dec 27 01:27:03 PM PST 23 566267974 ps
T103 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4193474414 Dec 27 01:26:22 PM PST 23 Dec 27 01:26:33 PM PST 23 724817232 ps
T104 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1906082928 Dec 27 01:26:25 PM PST 23 Dec 27 01:26:44 PM PST 23 3549589041 ps
T174 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3682891038 Dec 27 01:26:34 PM PST 23 Dec 27 01:26:37 PM PST 23 52134735 ps
T175 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.3435493946 Dec 27 01:26:36 PM PST 23 Dec 27 01:26:39 PM PST 23 614615252 ps
T176 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1033701552 Dec 27 01:26:09 PM PST 23 Dec 27 01:26:16 PM PST 23 1970289056 ps
T177 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1746346899 Dec 27 01:26:30 PM PST 23 Dec 27 01:26:32 PM PST 23 189135662 ps
T185 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3600581775 Dec 27 01:26:42 PM PST 23 Dec 27 01:26:44 PM PST 23 36520894 ps
T178 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3928312557 Dec 27 01:26:33 PM PST 23 Dec 27 01:26:36 PM PST 23 1021046054 ps
T106 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3073081187 Dec 27 01:26:10 PM PST 23 Dec 27 01:26:14 PM PST 23 932152164 ps
T234 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.990674067 Dec 27 01:26:22 PM PST 23 Dec 27 01:26:24 PM PST 23 569207019 ps
T225 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.474808252 Dec 27 01:26:34 PM PST 23 Dec 27 01:26:38 PM PST 23 1669194961 ps
T224 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2232268611 Dec 27 01:26:46 PM PST 23 Dec 27 01:27:06 PM PST 23 2179277787 ps
T235 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2724511374 Dec 27 01:26:26 PM PST 23 Dec 27 01:26:28 PM PST 23 151598831 ps
T236 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.4242161610 Dec 27 01:26:45 PM PST 23 Dec 27 01:26:47 PM PST 23 43135717 ps
T237 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2907021830 Dec 27 01:26:48 PM PST 23 Dec 27 01:26:50 PM PST 23 37927456 ps
T376 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3630414287 Dec 27 01:26:12 PM PST 23 Dec 27 01:26:14 PM PST 23 43280889 ps
T226 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1519282871 Dec 27 01:26:16 PM PST 23 Dec 27 01:26:33 PM PST 23 2641188629 ps
T318 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.71313764 Dec 27 01:26:49 PM PST 23 Dec 27 01:26:51 PM PST 23 143927712 ps
T228 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2521592993 Dec 27 01:26:14 PM PST 23 Dec 27 01:26:23 PM PST 23 537624490 ps
T229 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1516127642 Dec 27 01:26:31 PM PST 23 Dec 27 01:26:34 PM PST 23 127554500 ps
T219 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3555315302 Dec 27 01:26:22 PM PST 23 Dec 27 01:26:48 PM PST 23 18323539677 ps
T227 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.4185642730 Dec 27 01:26:45 PM PST 23 Dec 27 01:27:04 PM PST 23 2746077381 ps
T179 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1178486696 Dec 27 01:26:30 PM PST 23 Dec 27 01:26:33 PM PST 23 85895245 ps
T284 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1154325151 Dec 27 01:26:18 PM PST 23 Dec 27 01:26:20 PM PST 23 72662158 ps
T292 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1926649748 Dec 27 01:26:02 PM PST 23 Dec 27 01:26:04 PM PST 23 493458907 ps
T107 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1004440068 Dec 27 01:26:14 PM PST 23 Dec 27 01:26:16 PM PST 23 62541917 ps
T230 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3225056330 Dec 27 01:26:23 PM PST 23 Dec 27 01:26:25 PM PST 23 74585653 ps
T180 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2388391095 Dec 27 01:26:23 PM PST 23 Dec 27 01:26:29 PM PST 23 139401409 ps
T181 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2397897420 Dec 27 01:26:28 PM PST 23 Dec 27 01:26:34 PM PST 23 152691475 ps
T231 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2934888198 Dec 27 01:26:15 PM PST 23 Dec 27 01:26:17 PM PST 23 650475116 ps
T238 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1677920921 Dec 27 01:26:58 PM PST 23 Dec 27 01:27:00 PM PST 23 113762281 ps
T182 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2197989728 Dec 27 01:26:54 PM PST 23 Dec 27 01:26:58 PM PST 23 96447145 ps
T183 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2993240770 Dec 27 01:26:44 PM PST 23 Dec 27 01:26:49 PM PST 23 232902913 ps
T184 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1275951186 Dec 27 01:26:19 PM PST 23 Dec 27 01:26:23 PM PST 23 102419975 ps
T248 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3010743597 Dec 27 01:26:52 PM PST 23 Dec 27 01:26:54 PM PST 23 131650675 ps
T377 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2610254131 Dec 27 01:26:35 PM PST 23 Dec 27 01:26:37 PM PST 23 129870537 ps
T375 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1564089656 Dec 27 01:26:48 PM PST 23 Dec 27 01:26:52 PM PST 23 1082851352 ps
T378 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2455855112 Dec 27 01:26:08 PM PST 23 Dec 27 01:26:16 PM PST 23 545959885 ps
T379 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1728180764 Dec 27 01:26:53 PM PST 23 Dec 27 01:26:57 PM PST 23 507093627 ps
T232 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2322244983 Dec 27 01:26:10 PM PST 23 Dec 27 01:26:14 PM PST 23 1619232919 ps
T320 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.103077307 Dec 27 01:26:30 PM PST 23 Dec 27 01:26:40 PM PST 23 1252814865 ps
T221 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2092903964 Dec 27 01:26:48 PM PST 23 Dec 27 01:26:52 PM PST 23 158244884 ps
T233 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1081768476 Dec 27 01:26:16 PM PST 23 Dec 27 01:26:20 PM PST 23 139265166 ps
T319 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.4225223927 Dec 27 01:26:29 PM PST 23 Dec 27 01:26:31 PM PST 23 67231514 ps
T239 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.898215690 Dec 27 01:26:32 PM PST 23 Dec 27 01:26:35 PM PST 23 861794335 ps
T240 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.4121134278 Dec 27 01:26:53 PM PST 23 Dec 27 01:26:57 PM PST 23 756075577 ps
T380 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3514724306 Dec 27 01:26:21 PM PST 23 Dec 27 01:26:38 PM PST 23 2297479435 ps
T381 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2017316224 Dec 27 01:25:59 PM PST 23 Dec 27 01:26:02 PM PST 23 132341031 ps
T322 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.113296884 Dec 27 01:26:29 PM PST 23 Dec 27 01:26:39 PM PST 23 670467922 ps
T321 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.806251551 Dec 27 01:26:22 PM PST 23 Dec 27 01:26:41 PM PST 23 3243149298 ps
T241 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3545126561 Dec 27 01:26:43 PM PST 23 Dec 27 01:26:46 PM PST 23 150393202 ps
T108 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1092382493 Dec 27 01:26:10 PM PST 23 Dec 27 01:26:12 PM PST 23 228684885 ps
T285 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1785083295 Dec 27 01:26:49 PM PST 23 Dec 27 01:26:53 PM PST 23 928647221 ps
T382 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.2138320954 Dec 27 01:26:46 PM PST 23 Dec 27 01:26:48 PM PST 23 38920327 ps
T220 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3109508954 Dec 27 01:26:18 PM PST 23 Dec 27 01:26:24 PM PST 23 144064889 ps
T295 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.889131465 Dec 27 01:26:19 PM PST 23 Dec 27 01:26:27 PM PST 23 2809286505 ps
T286 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2545946102 Dec 27 01:26:23 PM PST 23 Dec 27 01:26:46 PM PST 23 3307349406 ps
T383 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.731270750 Dec 27 01:26:45 PM PST 23 Dec 27 01:26:47 PM PST 23 88482823 ps
T242 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3952959615 Dec 27 01:25:52 PM PST 23 Dec 27 01:25:54 PM PST 23 72178002 ps
T249 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2209056227 Dec 27 01:26:53 PM PST 23 Dec 27 01:26:55 PM PST 23 43044558 ps
T243 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1340391049 Dec 27 01:26:11 PM PST 23 Dec 27 01:26:14 PM PST 23 996501095 ps
T250 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3201451775 Dec 27 01:26:38 PM PST 23 Dec 27 01:26:41 PM PST 23 37550246 ps
T251 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2054225106 Dec 27 01:26:37 PM PST 23 Dec 27 01:26:39 PM PST 23 564255330 ps
T244 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2900555417 Dec 27 01:26:21 PM PST 23 Dec 27 01:26:23 PM PST 23 78946498 ps
T252 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1029289513 Dec 27 01:26:28 PM PST 23 Dec 27 01:26:38 PM PST 23 1646433473 ps
T253 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.3226742006 Dec 27 01:26:20 PM PST 23 Dec 27 01:26:22 PM PST 23 46009886 ps
T254 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.862240269 Dec 27 01:26:55 PM PST 23 Dec 27 01:26:57 PM PST 23 42293373 ps
T255 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2558967816 Dec 27 01:26:34 PM PST 23 Dec 27 01:26:37 PM PST 23 517904443 ps
T245 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1958087334 Dec 27 01:26:20 PM PST 23 Dec 27 01:26:23 PM PST 23 44838281 ps
T384 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2120192351 Dec 27 01:26:22 PM PST 23 Dec 27 01:26:24 PM PST 23 606374675 ps
T246 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.984887909 Dec 27 01:26:36 PM PST 23 Dec 27 01:26:39 PM PST 23 121641270 ps
T385 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.593722057 Dec 27 01:26:33 PM PST 23 Dec 27 01:26:35 PM PST 23 42502097 ps
T386 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.773143465 Dec 27 01:26:38 PM PST 23 Dec 27 01:26:40 PM PST 23 512779887 ps
T387 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1736310515 Dec 27 01:26:41 PM PST 23 Dec 27 01:26:43 PM PST 23 157700264 ps
T388 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1341823330 Dec 27 01:26:33 PM PST 23 Dec 27 01:26:39 PM PST 23 421458985 ps
T389 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1545912519 Dec 27 01:26:59 PM PST 23 Dec 27 01:27:02 PM PST 23 72012328 ps
T390 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3538236895 Dec 27 01:26:24 PM PST 23 Dec 27 01:26:29 PM PST 23 1453647136 ps
T287 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.41856426 Dec 27 01:26:44 PM PST 23 Dec 27 01:26:48 PM PST 23 386397464 ps
T391 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3756571243 Dec 27 01:26:11 PM PST 23 Dec 27 01:26:14 PM PST 23 48452988 ps
T392 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.1856453881 Dec 27 01:26:52 PM PST 23 Dec 27 01:26:54 PM PST 23 72034946 ps
T393 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2989349933 Dec 27 01:26:54 PM PST 23 Dec 27 01:26:57 PM PST 23 78879134 ps
T394 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3367037956 Dec 27 01:26:14 PM PST 23 Dec 27 01:26:16 PM PST 23 73120163 ps
T395 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3934557628 Dec 27 01:26:33 PM PST 23 Dec 27 01:26:35 PM PST 23 71401078 ps
T396 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.561856480 Dec 27 01:26:33 PM PST 23 Dec 27 01:26:36 PM PST 23 101432906 ps
T397 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.1505443510 Dec 27 01:26:50 PM PST 23 Dec 27 01:26:52 PM PST 23 43562037 ps
T247 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.4101073072 Dec 27 01:27:57 PM PST 23 Dec 27 01:28:00 PM PST 23 150734316 ps
T222 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3860496242 Dec 27 01:26:53 PM PST 23 Dec 27 01:26:59 PM PST 23 388979431 ps
T264 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.38181146 Dec 27 01:26:39 PM PST 23 Dec 27 01:26:42 PM PST 23 259506442 ps
T265 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3281912927 Dec 27 01:26:40 PM PST 23 Dec 27 01:26:51 PM PST 23 858427891 ps
T266 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3749120021 Dec 27 01:26:53 PM PST 23 Dec 27 01:26:59 PM PST 23 402950563 ps
T267 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3263309260 Dec 27 01:26:18 PM PST 23 Dec 27 01:26:21 PM PST 23 563785467 ps
T268 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.749620802 Dec 27 01:26:12 PM PST 23 Dec 27 01:26:22 PM PST 23 1167720011 ps
T269 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.2501905486 Dec 27 01:26:10 PM PST 23 Dec 27 01:26:12 PM PST 23 591050479 ps
T270 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3608304553 Dec 27 01:26:33 PM PST 23 Dec 27 01:26:42 PM PST 23 9558086251 ps
T271 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3270855039 Dec 27 01:26:47 PM PST 23 Dec 27 01:26:49 PM PST 23 131019026 ps
T289 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.810640259 Dec 27 01:26:41 PM PST 23 Dec 27 01:26:47 PM PST 23 167364378 ps
T398 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.722342378 Dec 27 01:26:22 PM PST 23 Dec 27 01:26:30 PM PST 23 85785823 ps
T399 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.4193112577 Dec 27 01:26:59 PM PST 23 Dec 27 01:27:02 PM PST 23 51109934 ps
T400 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1774659135 Dec 27 01:26:24 PM PST 23 Dec 27 01:26:26 PM PST 23 77226475 ps
T401 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.492571876 Dec 27 01:26:03 PM PST 23 Dec 27 01:26:06 PM PST 23 154188269 ps
T402 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1864171453 Dec 27 01:26:32 PM PST 23 Dec 27 01:26:37 PM PST 23 108630374 ps
T403 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3677603864 Dec 27 01:26:27 PM PST 23 Dec 27 01:26:29 PM PST 23 525979647 ps
T288 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3859888014 Dec 27 01:26:45 PM PST 23 Dec 27 01:26:47 PM PST 23 253469944 ps
T404 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3007056655 Dec 27 01:26:27 PM PST 23 Dec 27 01:26:29 PM PST 23 67413233 ps
T405 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3517259587 Dec 27 01:26:40 PM PST 23 Dec 27 01:26:46 PM PST 23 1065871354 ps
T406 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.3246788578 Dec 27 01:26:48 PM PST 23 Dec 27 01:26:50 PM PST 23 94929206 ps
T407 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2626029542 Dec 27 01:25:54 PM PST 23 Dec 27 01:25:59 PM PST 23 174244977 ps
T408 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2299600923 Dec 27 01:26:45 PM PST 23 Dec 27 01:26:47 PM PST 23 510366570 ps
T409 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.4029452194 Dec 27 01:26:53 PM PST 23 Dec 27 01:26:55 PM PST 23 553043633 ps
T410 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3268023396 Dec 27 01:26:09 PM PST 23 Dec 27 01:26:11 PM PST 23 83387487 ps
T256 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1462615304 Dec 27 01:26:10 PM PST 23 Dec 27 01:26:13 PM PST 23 68854785 ps
T290 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3028537866 Dec 27 01:26:21 PM PST 23 Dec 27 01:26:27 PM PST 23 232315870 ps
T257 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1418189830 Dec 27 01:26:15 PM PST 23 Dec 27 01:26:20 PM PST 23 417518952 ps
T258 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1473003604 Dec 27 01:26:27 PM PST 23 Dec 27 01:26:29 PM PST 23 38603362 ps
T223 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.478038881 Dec 27 01:26:46 PM PST 23 Dec 27 01:27:25 PM PST 23 18932358418 ps
T411 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2700677765 Dec 27 01:26:33 PM PST 23 Dec 27 01:26:37 PM PST 23 1637446948 ps
T412 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3649230986 Dec 27 01:26:59 PM PST 23 Dec 27 01:27:02 PM PST 23 76945703 ps
T291 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4062826447 Dec 27 01:26:19 PM PST 23 Dec 27 01:26:23 PM PST 23 154806251 ps
T413 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3711999185 Dec 27 01:26:15 PM PST 23 Dec 27 01:26:18 PM PST 23 70045018 ps
T414 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.4288310258 Dec 27 01:26:42 PM PST 23 Dec 27 01:26:44 PM PST 23 50532000 ps
T323 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2310156116 Dec 27 01:26:19 PM PST 23 Dec 27 01:26:29 PM PST 23 1194934814 ps
T415 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.920163203 Dec 27 01:26:48 PM PST 23 Dec 27 01:26:51 PM PST 23 565918326 ps
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