Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
creator_sw_lock	2	0	2	100.00	100	1	1	2
hw_cfg_lock	2	0	2	100.00	100	1	1	2
lc_esc	2	0	2	100.00	100	1	1	2
owner_sw_lock	2	0	2	100.00	100	1	1	2
secret0_lock	2	0	2	100.00	100	1	1	2
secret1_lock	2	0	2	100.00	100	1	1	2
secret2_lock	2	0	2	100.00	100	1	1	2
vendor_sw_lock	2	0	2	100.00	100	1	1	2

Summary for Variable creator_sw_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for creator_sw_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7373

1

T101

2

T102

2

T173

2

auto[1]

5044

1

T2

10

T3

17

T4

17

---

Summary for Variable hw_cfg_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_cfg_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7551

1

T101

2

T102

2

T173

2

auto[1]

4866

1

T2

10

T3

17

T4

17

---

Summary for Variable lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12361

1

T101

2

T102

2

T173

2

auto[1]

56

1

T159

1

T99

1

T199

1

---

Summary for Variable owner_sw_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for owner_sw_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7781

1

T101

2

T102

2

T173

2

auto[1]

4636

1

T2

10

T3

11

T4

17

---

Summary for Variable secret0_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret0_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7599

1

T101

2

T102

2

T173

2

auto[1]

4818

1

T2

6

T3

11

T4

17

---

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7564

1

T101

2

T102

2

T173

2

auto[1]

4853

1

T3

13

T4

19

T5

1

---

Summary for Variable secret2_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret2_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8667

1

T101

2

T102

2

T173

2

auto[1]

3750

1

T2

8

T3

17

T4

15

---

Summary for Variable vendor_sw_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for vendor_sw_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10643

1

T101

2

T102

2

T173

2

auto[1]

1774

1

T2

10

T4

13

T6

7