Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	91.07	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

28 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if	10.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if	20.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
10.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	9	1	10.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	9	1	10.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
20.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	8	2	20.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	8	2	20.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	9	1	10.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1
true	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

14106

1

T19

1

T107

1

T108

1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	8	2	20.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

10106

1

T19

1

T107

1

T108

1

true

16340

1

T19

1

T107

1

T108

1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	98	1			T101	2		T139	2		T336	2
others[1]	88	1			T104	2		T85	2		T92	2
others[2]	116	1			T206	2		T93	2		T42	2
others[3]	80	1			T87	2		T337	2		T43	2
others[4]	84	1			T84	2		T101	2		T78	2
others[5]	90	1			T139	2		T180	2		T338	2
others[6]	90	1			T14	2		T101	2		T85	2
others[7]	116	1			T102	2		T180	2		T338	2
false	14106	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	108	1			T84	2		T85	2		T87	2
others[1]	100	1			T101	2		T180	2		T339	2
others[2]	74	1			T85	2		T90	2		T340	2
others[3]	101	1			T84	2		T78	2		T89	4
others[4]	106	1			T84	4		T85	2		T90	2
others[5]	84	1			T4	2		T35	2		T14	2
others[6]	96	1			T84	2		T102	2		T180	2
others[7]	74	1			T14	2		T92	2		T139	2
false	14105	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	80	1			T84	2		T102	2		T92	2
others[1]	80	1			T180	2		T341	2		T340	2
others[2]	62	1			T88	2		T342	2		T337	2
others[3]	95	1			T84	2		T86	2		T90	2
others[4]	84	1			T104	2		T101	4		T90	2
others[5]	122	1			T103	2		T90	4		T91	2
others[6]	92	1			T87	2		T78	2		T89	2
others[7]	98	1			T84	4		T87	2		T337	2
false	14105	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	100	1			T84	6		T87	2		T88	2
others[1]	100	1			T83	2		T90	2		T91	4
others[2]	120	1			T83	2		T84	2		T86	2
others[3]	104	1			T4	2		T15	2		T90	2
others[4]	90	1			T84	2		T86	2		T90	2
others[5]	114	1			T52	2		T84	2		T87	2
others[6]	66	1			T91	2		T42	2		T182	2
others[7]	132	1			T85	2		T102	2		T206	2
false	14106	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	88	1			T89	2		T90	2		T180	6
others[1]	78	1			T88	2		T180	2		T340	2
others[2]	68	1			T84	2		T90	2		T92	2
others[3]	92	1			T91	2		T343	2		T344	2
others[4]	68	1			T84	4		T90	2		T336	4
others[5]	96	1			T83	2		T84	2		T85	2
others[6]	74	1			T85	2		T90	2		T92	2
others[7]	94	1			T4	2		T84	2		T180	2
false	14106	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	86	1			T15	2		T84	2		T86	2
others[1]	98	1			T86	2		T93	2		T210	2
others[2]	96	1			T35	2		T84	2		T92	2
others[3]	76	1			T52	2		T90	2		T210	2
others[4]	86	1			T35	2		T84	2		T343	2
others[5]	88	1			T84	4		T78	2		T343	2
others[6]	96	1			T91	2		T210	2		T345	2
others[7]	82	1			T84	4		T91	2		T92	2
false	14106	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	82	1			T93	2		T346	2		T347	2
others[1]	106	1			T35	2		T87	2		T90	4
others[2]	86	1			T87	2		T78	2		T89	2
others[3]	94	1			T14	2		T102	2		T210	4
others[4]	68	1			T180	4		T31	2		T210	2
others[5]	88	1			T14	2		T101	2		T87	2
others[6]	88	1			T84	2		T90	2		T102	2
others[7]	110	1			T84	2		T93	2		T338	2
false	14106	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	26	1			T92	2		T304	6		T348	2
others[1]	30	1			T92	2		T158	4		T349	2
others[2]	32	1			T183	2		T301	2		T304	2
others[3]	28	1			T139	2		T181	2		T350	2
others[4]	42	1			T78	2		T182	2		T151	2
others[5]	24	1			T89	2		T139	2		T180	2
others[6]	24	1			T89	2		T42	2		T158	2
others[7]	28	1			T158	4		T159	2		T349	2
false	14106	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	29	1			T11	1		T16	1		T118	1
others[1]	33	1			T11	1		T12	1		T13	1
others[2]	33	1			T17	1		T351	1		T352	1
others[3]	36	1			T127	2		T13	1		T121	1
others[4]	39	1			T12	2		T118	1		T351	2
others[5]	53	1			T11	2		T12	1		T17	1
others[6]	41	1			T13	1		T34	1		T93	2
others[7]	55	1			T16	2		T204	2		T118	1
false	14106	1			T19	1		T107	1		T108	1
true	2342	1			T112	1		T113	2		T114	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	38	1			T11	2		T13	1		T16	1
others[1]	34	1			T34	1		T333	1		T353	1
others[2]	38	1			T12	1		T121	1		T118	1
others[3]	44	1			T12	1		T127	2		T16	3
others[4]	36	1			T12	1		T16	1		T118	1
others[5]	40	1			T11	1		T351	1		T352	1
others[6]	42	1			T12	1		T13	1		T34	1
others[7]	47	1			T11	1		T13	1		T17	2
false	11438	1			T19	1		T107	1		T108	1
true	18665	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	100	1			T101	2		T336	4		T210	2
others[1]	82	1			T101	2		T102	2		T92	2
others[2]	120	1			T14	2		T87	2		T139	2
others[3]	72	1			T101	2		T102	2		T180	2
others[4]	92	1			T90	2		T206	2		T343	2
others[5]	84	1			T104	2		T84	2		T85	4
others[6]	82	1			T180	2		T68	2		T151	2
others[7]	130	1			T91	2		T181	2		T42	2
false	7364	1			T19	1		T107	1		T108	1
true	16391	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	98	1			T14	2		T84	2		T341	2
others[1]	92	1			T14	2		T139	2		T336	2
others[2]	84	1			T85	4		T78	2		T89	2
others[3]	130	1			T87	2		T90	2		T91	2
others[4]	90	1			T84	2		T180	2		T336	2
others[5]	68	1			T4	2		T35	2		T89	2
others[6]	75	1			T84	4		T85	2		T180	2
others[7]	106	1			T84	2		T101	2		T88	2
false	6793	1			T19	1		T107	1		T108	1
true	16199	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	29	1			T85	2		T16	1		T17	1
others[1]	28	1			T11	1		T13	1		T16	1
others[2]	37	1			T11	1		T12	1		T13	1
others[3]	41	1			T12	2		T84	2		T16	1
others[4]	53	1			T103	2		T12	1		T13	1
others[5]	37	1			T11	2		T13	1		T123	1
others[6]	44	1			T116	2		T354	2		T203	1
others[7]	46	1			T11	1		T12	2		T203	1
false	11370	1			T19	1		T107	1		T108	1
true	18594	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	82	1			T103	2		T104	2		T87	2
others[1]	88	1			T90	2		T210	2		T347	2
others[2]	98	1			T139	2		T337	2		T42	2
others[3]	106	1			T84	4		T86	2		T88	2
others[4]	81	1			T338	2		T32	2		T347	2
others[5]	84	1			T89	2		T337	2		T336	2
others[6]	100	1			T101	4		T91	2		T92	2
others[7]	74	1			T84	4		T87	2		T341	2
false	7581	1			T19	1		T107	1		T108	1
true	16355	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	116	1			T84	4		T87	2		T337	2
others[1]	96	1			T86	2		T91	2		T180	2
others[2]	102	1			T15	2		T89	2		T91	4
others[3]	114	1			T52	2		T83	2		T84	4
others[4]	96	1			T83	2		T84	2		T90	2
others[5]	90	1			T4	2		T84	2		T85	2
others[6]	88	1			T87	2		T343	2		T344	2
others[7]	124	1			T92	2		T338	2		T182	2
false	6995	1			T19	1		T107	1		T108	1
true	16186	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	62	1			T90	2		T92	2		T180	2
others[1]	94	1			T91	2		T180	4		T344	2
others[2]	70	1			T83	2		T84	2		T90	2
others[3]	74	1			T89	2		T180	2		T341	2
others[4]	86	1			T84	4		T87	2		T90	4
others[5]	66	1			T85	2		T180	2		T210	6
others[6]	78	1			T92	2		T355	2		T356	2
others[7]	128	1			T4	2		T84	4		T85	2
false	6995	1			T19	1		T107	1		T108	1
true	16186	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	76	1			T35	2		T91	2		T346	4
others[1]	88	1			T343	2		T357	2		T158	2
others[2]	68	1			T84	2		T78	2		T93	2
others[3]	112	1			T52	2		T15	2		T84	2
others[4]	106	1			T84	6		T86	2		T181	2
others[5]	88	1			T35	2		T90	2		T92	2
others[6]	90	1			T343	2		T339	2		T210	2
others[7]	80	1			T84	4		T86	2		T91	2
false	6285	1			T19	1		T107	1		T108	1
true	16186	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	70	1			T87	2		T358	2		T205	2
others[1]	76	1			T90	2		T139	2		T180	4
others[2]	108	1			T14	2		T78	2		T102	2
others[3]	62	1			T93	2		T355	2		T164	4
others[4]	100	1			T14	2		T84	2		T87	4
others[5]	86	1			T101	2		T90	2		T102	2
others[6]	86	1			T180	2		T31	2		T359	2
others[7]	134	1			T35	2		T84	2		T89	2
false	6285	1			T19	1		T107	1		T108	1
true	16186	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	66	1			T84	2		T88	2		T360	2
others[1]	40	1			T343	2		T355	2		T158	4
others[2]	52	1			T101	2		T341	4		T210	4
others[3]	56	1			T87	2		T89	2		T346	2
others[4]	80	1			T88	2		T89	2		T93	2
others[5]	82	1			T87	2		T93	2		T343	2
others[6]	82	1			T35	2		T14	2		T101	2
others[7]	100	1			T84	4		T86	2		T90	2
false	6740	1			T19	1		T107	1		T108	1
true	17607	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	72	1			T85	2		T340	2		T158	2
others[1]	44	1			T84	2		T87	2		T340	2
others[2]	90	1			T90	2		T139	2		T42	2
others[3]	60	1			T182	2		T210	2		T359	2
others[4]	44	1			T92	2		T340	2		T355	2
others[5]	62	1			T346	2		T345	2		T164	2
others[6]	38	1			T92	2		T158	2		T361	2
others[7]	90	1			T35	2		T86	2		T87	2
false	6740	1			T19	1		T107	1		T108	1
true	17607	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	37	1			T11	1		T13	1		T16	1
others[1]	27	1			T16	1		T17	1		T34	2
others[2]	41	1			T13	1		T34	1		T93	2
others[3]	28	1			T11	1		T16	1		T17	2
others[4]	37	1			T12	1		T17	1		T34	1
others[5]	28	1			T11	1		T209	1		T203	1
others[6]	32	1			T16	2		T34	2		T118	1
others[7]	53	1			T11	1		T13	1		T16	2
false	11499	1			T19	1		T107	1		T108	1
true	18703	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	28	1			T89	2		T92	2		T181	2
others[1]	24	1			T139	2		T362	2		T350	2
others[2]	28	1			T180	2		T183	2		T158	4
others[3]	22	1			T78	2		T182	2		T158	2
others[4]	24	1			T42	2		T151	2		T158	4
others[5]	40	1			T89	2		T92	2		T139	2
others[6]	28	1			T158	2		T363	2		T364	2
others[7]	40	1			T350	2		T365	2		T301	2
false	10192	1			T19	1		T107	1		T108	1
true	16527	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30	1			T103	2		T11	2		T13	1
others[1]	41	1			T12	1		T84	2		T16	1
others[2]	34	1			T12	1		T17	1		T34	1
others[3]	46	1			T16	2		T118	1		T203	1
others[4]	35	1			T16	1		T354	1		T203	1
others[5]	43	1			T11	3		T12	2		T13	1
others[6]	46	1			T12	2		T85	2		T13	1
others[7]	40	1			T13	1		T118	1		T209	2
false	14106	1			T19	1		T107	1		T108	1
true	2332	1			T112	1		T113	1		T1	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	76	1			T35	2		T14	2		T84	2
others[1]	60	1			T88	2		T343	2		T341	2
others[2]	64	1			T86	2		T346	2		T158	4
others[3]	58	1			T139	2		T153	2		T158	4
others[4]	76	1			T84	4		T87	2		T88	2
others[5]	76	1			T93	2		T339	2		T340	2
others[6]	76	1			T101	4		T89	4		T42	2
others[7]	72	1			T87	2		T90	2		T180	2
false	14023	1			T19	1		T107	1		T108	1
true	16608	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	66	1			T92	2		T340	2		T210	2
others[1]	50	1			T85	2		T59	2		T210	2
others[2]	62	1			T87	4		T340	2		T355	2
others[3]	78	1			T84	2		T88	2		T139	2
others[4]	68	1			T86	2		T182	2		T340	2
others[5]	46	1			T92	2		T42	2		T210	2
others[6]	66	1			T90	2		T346	2		T366	2
others[7]	64	1			T35	2		T210	2		T158	2
false	14023	1			T19	1		T107	1		T108	1
true	16636	1			T19	1		T107	1		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35	1			T12	1		T13	1		T16	1
others[1]	44	1			T11	1		T13	1		T16	2
others[2]	37	1			T11	1		T16	1		T34	1
others[3]	33	1			T11	1		T16	1		T17	1
others[4]	33	1			T11	1		T34	2		T118	1
others[5]	28	1			T16	1		T34	1		T91	2
others[6]	38	1			T13	1		T121	1		T34	1
others[7]	35	1			T16	1		T17	2		T34	1
false	14106	1			T19	1		T107	1		T108	1
true	2319	1			T112	1		T113	1		T114	1